Searched refs:VLV_DISPLAY_BASE (Results 1 - 11 of 11) sorted by last modified time

/linux-master/drivers/gpu/drm/i915/
H A Di915_reg.h164 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
186 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
187 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
192 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
392 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
416 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
417 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
425 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
428 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
429 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE
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/linux-master/drivers/gpu/drm/i915/display/
H A Dvlv_dsi_regs.h11 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
H A Dintel_sprite_regs.h202 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
228 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
229 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
230 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
235 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
240 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
241 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
242 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
244 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
245 #define _SPATILEOFF (VLV_DISPLAY_BASE
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H A Dintel_gmbus.c873 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
H A Dintel_display_reg_defs.h13 #define VLV_DISPLAY_BASE 0x180000 macro
H A Dintel_display_device.c384 .mmio_offset = VLV_DISPLAY_BASE,
439 .mmio_offset = VLV_DISPLAY_BASE,
H A Dintel_color_regs.h267 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
268 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
269 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
270 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
271 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
272 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
278 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
284 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
289 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
290 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE
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H A Dintel_audio_regs.h41 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
42 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
44 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
45 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
47 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
55 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
56 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
152 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
155 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
161 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (por
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H A Dintel_dp_aux_regs.h30 #define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \
79 #define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \
H A Dintel_pps_regs.h13 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
H A Dintel_backlight_regs.h11 #define _VLV_BLC_PWM_CTL2_A (VLV_DISPLAY_BASE + 0x61250)
12 #define _VLV_BLC_PWM_CTL2_B (VLV_DISPLAY_BASE + 0x61350)
15 #define _VLV_BLC_PWM_CTL_A (VLV_DISPLAY_BASE + 0x61254)
16 #define _VLV_BLC_PWM_CTL_B (VLV_DISPLAY_BASE + 0x61354)
19 #define _VLV_BLC_HIST_CTL_A (VLV_DISPLAY_BASE + 0x61260)
20 #define _VLV_BLC_HIST_CTL_B (VLV_DISPLAY_BASE + 0x61360)

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