1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright �� 2023 Intel Corporation 4 */ 5 6#ifndef __INTEL_COLOR_REGS_H__ 7#define __INTEL_COLOR_REGS_H__ 8 9#include "intel_display_reg_defs.h" 10 11/* legacy palette */ 12#define _LGC_PALETTE_A 0x4a000 13#define _LGC_PALETTE_B 0x4a800 14/* see PALETTE_* for the bits */ 15#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 16 17/* ilk/snb precision palette */ 18#define _PREC_PALETTE_A 0x4b000 19#define _PREC_PALETTE_B 0x4c000 20/* 10bit mode */ 21#define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20) 22#define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10) 23#define PREC_PALETTE_10_BLUE_MASK REG_GENMASK(9, 0) 24/* 12.4 interpolated mode ldw */ 25#define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24) 26#define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14) 27#define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4) 28/* 12.4 interpolated mode udw */ 29#define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20) 30#define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10) 31#define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0) 32#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 33 34#define _PREC_PIPEAGCMAX 0x4d000 35#define _PREC_PIPEBGCMAX 0x4d010 36#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */ 37 38#define _GAMMA_MODE_A 0x4a480 39#define _GAMMA_MODE_B 0x4ac80 40#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 41#define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */ 42#define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */ 43#define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */ 44#define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0) 45#define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0) 46#define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1) 47#define GAMMA_MODE_MODE_12BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2) 48#define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */ 49#define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */ 50 51/* pipe CSC */ 52#define _PIPE_A_CSC_COEFF_RY_GY 0x49010 53#define _PIPE_A_CSC_COEFF_BY 0x49014 54#define _PIPE_A_CSC_COEFF_RU_GU 0x49018 55#define _PIPE_A_CSC_COEFF_BU 0x4901c 56#define _PIPE_A_CSC_COEFF_RV_GV 0x49020 57#define _PIPE_A_CSC_COEFF_BV 0x49024 58 59#define _PIPE_A_CSC_MODE 0x49028 60#define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 61#define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 62#define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 63#define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 64#define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 65 66#define _PIPE_A_CSC_PREOFF_HI 0x49030 67#define _PIPE_A_CSC_PREOFF_ME 0x49034 68#define _PIPE_A_CSC_PREOFF_LO 0x49038 69#define _PIPE_A_CSC_POSTOFF_HI 0x49040 70#define _PIPE_A_CSC_POSTOFF_ME 0x49044 71#define _PIPE_A_CSC_POSTOFF_LO 0x49048 72 73#define _PIPE_B_CSC_COEFF_RY_GY 0x49110 74#define _PIPE_B_CSC_COEFF_BY 0x49114 75#define _PIPE_B_CSC_COEFF_RU_GU 0x49118 76#define _PIPE_B_CSC_COEFF_BU 0x4911c 77#define _PIPE_B_CSC_COEFF_RV_GV 0x49120 78#define _PIPE_B_CSC_COEFF_BV 0x49124 79#define _PIPE_B_CSC_MODE 0x49128 80#define _PIPE_B_CSC_PREOFF_HI 0x49130 81#define _PIPE_B_CSC_PREOFF_ME 0x49134 82#define _PIPE_B_CSC_PREOFF_LO 0x49138 83#define _PIPE_B_CSC_POSTOFF_HI 0x49140 84#define _PIPE_B_CSC_POSTOFF_ME 0x49144 85#define _PIPE_B_CSC_POSTOFF_LO 0x49148 86 87#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 88#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 89#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 90#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 91#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 92#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 93#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 94#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 95#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 96#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 97#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 98#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 99#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 100 101/* Pipe Output CSC */ 102#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 103#define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 104#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 105#define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 106#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 107#define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 108#define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 109#define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 110#define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 111#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 112#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 113#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 114 115#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 116#define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 117#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 118#define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 119#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 120#define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 121#define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 122#define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 123#define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 124#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 125#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 126#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 127 128#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 129 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 130 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 131#define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 132 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 133 _PIPE_B_OUTPUT_CSC_COEFF_BY) 134#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 135 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 136 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 137#define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 138 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 139 _PIPE_B_OUTPUT_CSC_COEFF_BU) 140#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 141 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 142 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 143#define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 144 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 145 _PIPE_B_OUTPUT_CSC_COEFF_BV) 146#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 147 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 148 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 149#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 150 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 151 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 152#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 153 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 154 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 155#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 156 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 157 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 158#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 159 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 160 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 161#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 162 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 163 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 164 165/* pipe degamma/gamma LUTs on IVB+ */ 166#define _PAL_PREC_INDEX_A 0x4A400 167#define _PAL_PREC_INDEX_B 0x4AC00 168#define _PAL_PREC_INDEX_C 0x4B400 169#define PAL_PREC_SPLIT_MODE REG_BIT(31) 170#define PAL_PREC_AUTO_INCREMENT REG_BIT(15) 171#define PAL_PREC_INDEX_VALUE_MASK REG_GENMASK(9, 0) 172#define PAL_PREC_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_INDEX_VALUE_MASK, (x)) 173#define _PAL_PREC_DATA_A 0x4A404 174#define _PAL_PREC_DATA_B 0x4AC04 175#define _PAL_PREC_DATA_C 0x4B404 176/* see PREC_PALETTE_* for the bits */ 177#define _PAL_PREC_GC_MAX_A 0x4A410 178#define _PAL_PREC_GC_MAX_B 0x4AC10 179#define _PAL_PREC_GC_MAX_C 0x4B410 180#define _PAL_PREC_EXT_GC_MAX_A 0x4A420 181#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 182#define _PAL_PREC_EXT_GC_MAX_C 0x4B420 183#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 184#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 185#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 186 187#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 188#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 189#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */ 190#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */ 191#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */ 192 193#define _PRE_CSC_GAMC_INDEX_A 0x4A484 194#define _PRE_CSC_GAMC_INDEX_B 0x4AC84 195#define _PRE_CSC_GAMC_INDEX_C 0x4B484 196#define PRE_CSC_GAMC_AUTO_INCREMENT REG_BIT(10) 197#define PRE_CSC_GAMC_INDEX_VALUE_MASK REG_GENMASK(7, 0) 198#define PRE_CSC_GAMC_INDEX_VALUE(x) REG_FIELD_PREP(PRE_CSC_GAMC_INDEX_VALUE_MASK, (x)) 199#define _PRE_CSC_GAMC_DATA_A 0x4A488 200#define _PRE_CSC_GAMC_DATA_B 0x4AC88 201#define _PRE_CSC_GAMC_DATA_C 0x4B488 202 203#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 204#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 205 206/* ICL Multi segmented gamma */ 207#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 208#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 209#define PAL_PREC_MULTI_SEG_AUTO_INCREMENT REG_BIT(15) 210#define PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK REG_GENMASK(4, 0) 211#define PAL_PREC_MULTI_SEG_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK, (x)) 212 213#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 214#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 215/* see PREC_PALETTE_12P4_* for the bits */ 216 217#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 218 _PAL_PREC_MULTI_SEG_INDEX_A, \ 219 _PAL_PREC_MULTI_SEG_INDEX_B) 220#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 221 _PAL_PREC_MULTI_SEG_DATA_A, \ 222 _PAL_PREC_MULTI_SEG_DATA_B) 223 224#define _PIPE_A_WGC_C01_C00 0x600B0 /* s2.10 */ 225#define _PIPE_A_WGC_C02 0x600B4 /* s2.10 */ 226#define _PIPE_A_WGC_C11_C10 0x600B8 /* s2.10 */ 227#define _PIPE_A_WGC_C12 0x600BC /* s2.10 */ 228#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */ 229#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */ 230 231#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00) 232#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02) 233#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10) 234#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12) 235#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20) 236#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22) 237 238/* pipe CSC & degamma/gamma LUTs on CHV */ 239#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 240#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 241#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 242#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 243#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 244#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 245/* cgm degamma ldw */ 246#define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16) 247#define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0) 248/* cgm degamma udw */ 249#define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0) 250#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 251/* cgm gamma ldw */ 252#define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16) 253#define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0) 254/* cgm gamma udw */ 255#define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0) 256#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 257#define CGM_PIPE_MODE_GAMMA (1 << 2) 258#define CGM_PIPE_MODE_CSC (1 << 1) 259#define CGM_PIPE_MODE_DEGAMMA (1 << 0) 260 261#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 262#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 263#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 264#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 265#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 266#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 267#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 268#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 269 270#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 271#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 272#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 273#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 274#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 275#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 276#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 277#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 278 279/* Skylake+ pipe bottom (background) color */ 280#define _SKL_BOTTOM_COLOR_A 0x70034 281#define _SKL_BOTTOM_COLOR_B 0x71034 282#define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31) 283#define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30) 284#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B) 285 286#endif /* __INTEL_COLOR_REGS_H__ */ 287