1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright �� 2023 Intel Corporation 4 */ 5 6#ifndef __INTEL_PPS_REGS_H__ 7#define __INTEL_PPS_REGS_H__ 8 9#include "intel_display_reg_defs.h" 10 11/* Panel power sequencing */ 12#define PPS_BASE 0x61200 13#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 14#define PCH_PPS_BASE 0xC7200 15 16#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \ 17 PPS_BASE + (reg) + \ 18 (pps_idx) * 0x100) 19 20#define _PP_STATUS 0x61200 21#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 22#define PP_ON REG_BIT(31) 23/* 24 * Indicates that all dependencies of the panel are on: 25 * 26 * - PLL enabled 27 * - pipe enabled 28 * - LVDS/DVOB/DVOC on 29 */ 30#define PP_READY REG_BIT(30) 31#define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 32#define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 33#define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 34#define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 35#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 36#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 37#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 38#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 39#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 40#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 41#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 42#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 43#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 44#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 45#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 46 47#define _PP_CONTROL 0x61204 48#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 49#define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 50#define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 51#define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 52#define EDP_FORCE_VDD REG_BIT(3) 53#define EDP_BLC_ENABLE REG_BIT(2) 54#define PANEL_POWER_RESET REG_BIT(1) 55#define PANEL_POWER_ON REG_BIT(0) 56 57#define _PP_ON_DELAYS 0x61208 58#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 59#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 60#define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 61#define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 62#define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 63#define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 64#define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 65#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 66#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 67 68#define _PP_OFF_DELAYS 0x6120C 69#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 70#define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 71#define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 72 73#define _PP_DIVISOR 0x61210 74#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 75#define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 76#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 77 78#endif /* __INTEL_PPS_REGS_H__ */ 79