1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright �� 2022 Intel Corporation 4 */ 5 6#ifndef __INTEL_AUDIO_REGS_H__ 7#define __INTEL_AUDIO_REGS_H__ 8 9#include "intel_display_reg_defs.h" 10 11#define G4X_AUD_CNTL_ST _MMIO(0x620B4) 12#define G4X_ELD_VALID REG_BIT(14) 13#define G4X_ELD_BUFFER_SIZE_MASK REG_GENMASK(13, 9) 14#define G4X_ELD_ADDRESS_MASK REG_GENMASK(8, 5) 15#define G4X_ELD_ACK REG_BIT(4) 16#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 17 18#define _IBX_HDMIW_HDMIEDID_A 0xE2050 19#define _IBX_HDMIW_HDMIEDID_B 0xE2150 20#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 21 _IBX_HDMIW_HDMIEDID_B) 22#define _IBX_AUD_CNTL_ST_A 0xE20B4 23#define _IBX_AUD_CNTL_ST_B 0xE21B4 24#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 25 _IBX_AUD_CNTL_ST_B) 26#define IBX_ELD_BUFFER_SIZE_MASK REG_GENMASK(14, 10) 27#define IBX_ELD_ADDRESS_MASK REG_GENMASK(9, 5) 28#define IBX_ELD_ACK REG_BIT(4) 29#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 30#define IBX_CP_READY(port) REG_BIT(((port) - 1) * 4 + 1) 31#define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0) 32 33#define _CPT_HDMIW_HDMIEDID_A 0xE5050 34#define _CPT_HDMIW_HDMIEDID_B 0xE5150 35#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 36#define _CPT_AUD_CNTL_ST_A 0xE50B4 37#define _CPT_AUD_CNTL_ST_B 0xE51B4 38#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 39#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 40 41#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 42#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 43#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 44#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 45#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 46#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 47#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 48 49#define _IBX_AUD_CONFIG_A 0xe2000 50#define _IBX_AUD_CONFIG_B 0xe2100 51#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 52#define _CPT_AUD_CONFIG_A 0xe5000 53#define _CPT_AUD_CONFIG_B 0xe5100 54#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 55#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 56#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 57#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 58#define AUD_CONFIG_N_VALUE_INDEX REG_BIT(29) 59#define AUD_CONFIG_N_PROG_ENABLE REG_BIT(28) 60#define AUD_CONFIG_UPPER_N_MASK REG_GENMASK(27, 20) 61#define AUD_CONFIG_LOWER_N_MASK REG_GENMASK(15, 4) 62#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | \ 63 AUD_CONFIG_LOWER_N_MASK) 64#define AUD_CONFIG_N(n) (REG_FIELD_PREP(AUD_CONFIG_UPPER_N_MASK, (n) >> 12) | \ 65 REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff)) 66#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK REG_GENMASK(19, 16) 67#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 0) 68#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 1) 69#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 2) 70#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 3) 71#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 4) 72#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 5) 73#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 6) 74#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 7) 75#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 8) 76#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 9) 77#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 10) 78#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 11) 79#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 12) 80#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 13) 81#define AUD_CONFIG_DISABLE_NCTS REG_BIT(3) 82 83#define _HSW_AUD_CONFIG_A 0x65000 84#define _HSW_AUD_CONFIG_B 0x65100 85#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 86 87#define _HSW_AUD_MISC_CTRL_A 0x65010 88#define _HSW_AUD_MISC_CTRL_B 0x65110 89#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 90 91#define _HSW_AUD_M_CTS_ENABLE_A 0x65028 92#define _HSW_AUD_M_CTS_ENABLE_B 0x65128 93#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) 94#define AUD_M_CTS_M_VALUE_INDEX REG_BIT(21) 95#define AUD_M_CTS_M_PROG_ENABLE REG_BIT(20) 96#define AUD_CONFIG_M_MASK REG_GENMASK(19, 0) 97 98#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 99#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 100#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 101 102/* Audio Digital Converter */ 103#define _HSW_AUD_DIG_CNVT_1 0x65080 104#define _HSW_AUD_DIG_CNVT_2 0x65180 105#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 106#define DIP_PORT_SEL_MASK 0x3 107 108#define _HSW_AUD_EDID_DATA_A 0x65050 109#define _HSW_AUD_EDID_DATA_B 0x65150 110#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 111 112#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 113#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 114#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 115#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 116#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 117#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 118 119#define _AUD_TCA_DP_2DOT0_CTRL 0x650bc 120#define _AUD_TCB_DP_2DOT0_CTRL 0x651bc 121#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL) 122#define AUD_ENABLE_SDP_SPLIT REG_BIT(31) 123 124#define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 125#define SKL_AUD_CODEC_WAKE_SIGNAL REG_BIT(15) 126 127#define AUD_FREQ_CNTRL _MMIO(0x65900) 128#define AUD_PIN_BUF_CTL _MMIO(0x48414) 129#define AUD_PIN_BUF_ENABLE REG_BIT(31) 130 131#define AUD_TS_CDCLK_M _MMIO(0x65ea0) 132#define AUD_TS_CDCLK_M_EN REG_BIT(31) 133#define AUD_TS_CDCLK_N _MMIO(0x65ea4) 134 135/* Display Audio Config Reg */ 136#define AUD_CONFIG_BE _MMIO(0x65ef0) 137#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) 138#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) 139#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) 140#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) 141#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) 142#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) 143 144#define HBLANK_START_COUNT_8 0 145#define HBLANK_START_COUNT_16 1 146#define HBLANK_START_COUNT_32 2 147#define HBLANK_START_COUNT_64 3 148#define HBLANK_START_COUNT_96 4 149#define HBLANK_START_COUNT_128 5 150 151#endif /* __INTEL_AUDIO_REGS_H__ */ 152