Searched refs:UVD_MPC_SET_MUX__SET_2__SHIFT (Results 1 - 21 of 21) sorted by last modified time
| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v4_0_5.c | 897 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
1033 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
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| H A D | vcn_v4_0_3.c | 791 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
1117 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
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| H A D | vcn_v3_0.c | 1011 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
1175 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
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| H A D | vcn_v4_0.c | 983 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
1122 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
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| H A D | vcn_v2_5.c | 888 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
1042 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
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| H A D | vcn_v2_0.c | 860 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
993 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
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| H A D | vcn_v1_0.c | 845 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1028 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
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| /linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_4_0_5_sh_mask.h | 4074 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | vcn_4_0_0_sh_mask.h | 4207 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | vcn_4_0_3_sh_mask.h | 4250 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | vcn_2_5_sh_mask.h | 2884 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | vcn_2_6_0_sh_mask.h | 2876 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | vcn_3_0_0_sh_mask.h | 3957 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | vcn_2_0_0_sh_mask.h | 2649 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | vcn_1_0_sh_mask.h | 1143 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| /linux-master/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_7_0_sh_mask.h | 636 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | uvd_3_1_sh_mask.h | 514 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | uvd_4_0_sh_mask.h | 533 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x00000006 macro
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| H A D | uvd_4_2_sh_mask.h | 518 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | uvd_5_0_sh_mask.h | 550 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| H A D | uvd_6_0_sh_mask.h | 552 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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