Searched refs:UVD_MPC_SET_MUXA0__VARA_3__SHIFT (Results 1 - 21 of 21) sorted by path

/linux-master/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h503 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x00000012 macro
H A Duvd_4_2_sh_mask.h488 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
H A Duvd_5_0_sh_mask.h520 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
H A Duvd_6_0_sh_mask.h522 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
H A Duvd_3_1_sh_mask.h484 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
H A Duvd_7_0_sh_mask.h601 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1108 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
H A Dvcn_2_0_0_sh_mask.h2614 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
H A Dvcn_2_5_sh_mask.h2849 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
H A Dvcn_2_6_0_sh_mask.h2841 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
H A Dvcn_3_0_0_sh_mask.h3922 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
H A Dvcn_4_0_0_sh_mask.h4172 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
H A Dvcn_4_0_3_sh_mask.h4215 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
[all...]
H A Dvcn_4_0_5_sh_mask.h4039 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 macro
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c833 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1016 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
H A Dvcn_v2_0.c846 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
979 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
H A Dvcn_v2_5.c874 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1028 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
H A Dvcn_v3_0.c997 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1161 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
H A Dvcn_v4_0.c969 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1108 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
H A Dvcn_v4_0_3.c777 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1103 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
H A Dvcn_v4_0_5.c883 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1019 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |

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