Searched refs:MAX_INSTANCE (Results 1 - 25 of 25) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_vbios_smu.c33 #define MAX_INSTANCE 5 macro
41 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Ddimgrey_cavefish_reg_init.c34 for (i = 0 ; i < MAX_INSTANCE ; ++i) {
H A Daldebaran_reg_init.c33 for (i = 0 ; i < MAX_INSTANCE ; ++i) {
H A Darct_reg_init.c33 for (i = 0 ; i < MAX_INSTANCE ; ++i) {
H A Dvega10_reg_init.c33 for (i = 0 ; i < MAX_INSTANCE ; ++i) {
H A Dvega20_reg_init.c33 for (i = 0 ; i < MAX_INSTANCE ; ++i) {
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.c33 #define MAX_INSTANCE 6 macro
42 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.c34 #define MAX_INSTANCE 7 macro
42 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Ddcn316_clk_mgr.c45 #define MAX_INSTANCE 7 macro
53 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
/linux-master/drivers/gpu/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h24 #define MAX_INSTANCE 6 macro
33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Dnavi10_ip_offset.h24 #define MAX_INSTANCE 6 macro
33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Dvega20_ip_offset.h24 #define MAX_INSTANCE 6 macro
33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Dyellow_carp_offset.h6 #define MAX_INSTANCE 7 macro
15 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Drenoir_ip_offset.h24 #define MAX_INSTANCE 7 macro
33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Dvega10_ip_offset.h24 #define MAX_INSTANCE 5 macro
32 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Dsienna_cichlid_ip_offset.h24 #define MAX_INSTANCE 7 macro
33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Dbeige_goby_ip_offset.h25 #define MAX_INSTANCE 7 macro
34 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Dnavi12_ip_offset.h24 #define MAX_INSTANCE 7 macro
33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Dnavi14_ip_offset.h24 #define MAX_INSTANCE 7 macro
33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Ddimgrey_cavefish_ip_offset.h24 #define MAX_INSTANCE 7 macro
33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Daldebaran_ip_offset.h24 #define MAX_INSTANCE 7 macro
32 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Dvangogh_ip_offset.h27 #define MAX_INSTANCE 8 macro
36 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
H A Darct_ip_offset.h24 #define MAX_INSTANCE 8 macro
33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c61 #define MAX_INSTANCE 7 macro
69 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c111 #define MAX_INSTANCE 7 macro

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