Searched refs:FMT_CONTROL (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_opp.h46 SRI(FMT_CONTROL, FMT, id), \
88 SRI(FMT_CONTROL, FMT, id), \
122 OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
131 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
132 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
133 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh)
137 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
138 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
139 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
143 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MA
288 uint32_t FMT_CONTROL; member in struct:dce_opp_registers
[all...]
H A Ddce_opp.c227 REG_UPDATE_2(FMT_CONTROL,
231 REG_UPDATE_2(FMT_CONTROL,
237 REG_UPDATE_2(FMT_CONTROL,
476 REG_UPDATE_3(FMT_CONTROL,
481 REG_UPDATE_2(FMT_CONTROL,
486 REG_UPDATE_2(FMT_CONTROL,
491 REG_UPDATE_3(FMT_CONTROL,
502 * DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL reg
512 REG_UPDATE_2(FMT_CONTROL,
516 REG_UPDATE(FMT_CONTROL,
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_opp.c78 REG_UPDATE_2(FMT_CONTROL,
82 REG_UPDATE_2(FMT_CONTROL,
89 REG_UPDATE_2(FMT_CONTROL,
171 REG_UPDATE_3(FMT_CONTROL,
175 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
178 REG_UPDATE_3(FMT_CONTROL,
184 REG_UPDATE_3(FMT_CONTROL,
194 REG_UPDATE(FMT_CONTROL, FMT_SUBSAMPLING_MODE, 0);
342 REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);
H A Ddcn10_opp.h38 SRI(FMT_CONTROL, FMT, id), \
55 uint32_t FMT_CONTROL; \
/linux-master/drivers/gpu/drm/radeon/
H A Dcikd.h984 #define FMT_CONTROL 0x6fb8 macro
H A Dr600d.h1242 #define FMT_CONTROL 0x6700 macro
H A Devergreend.h1373 #define FMT_CONTROL 0x6fb8 macro
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h535 SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \

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