1/* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27#ifndef R600D_H 28#define R600D_H 29 30#define CP_PACKET2 0x80000000 31#define PACKET2_PAD_SHIFT 0 32#define PACKET2_PAD_MASK (0x3fffffff << 0) 33 34#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 35 36#define R6XX_MAX_SH_GPRS 256 37#define R6XX_MAX_TEMP_GPRS 16 38#define R6XX_MAX_SH_THREADS 256 39#define R6XX_MAX_SH_STACK_ENTRIES 4096 40#define R6XX_MAX_BACKENDS 8 41#define R6XX_MAX_BACKENDS_MASK 0xff 42#define R6XX_MAX_SIMDS 8 43#define R6XX_MAX_SIMDS_MASK 0xff 44#define R6XX_MAX_PIPES 8 45#define R6XX_MAX_PIPES_MASK 0xff 46 47/* tiling bits */ 48#define ARRAY_LINEAR_GENERAL 0x00000000 49#define ARRAY_LINEAR_ALIGNED 0x00000001 50#define ARRAY_1D_TILED_THIN1 0x00000002 51#define ARRAY_2D_TILED_THIN1 0x00000004 52 53/* Registers */ 54#define ARB_POP 0x2418 55#define ENABLE_TC128 (1 << 30) 56#define ARB_GDEC_RD_CNTL 0x246C 57 58#define CC_GC_SHADER_PIPE_CONFIG 0x8950 59#define CC_RB_BACKEND_DISABLE 0x98F4 60#define BACKEND_DISABLE(x) ((x) << 16) 61 62#define R_028808_CB_COLOR_CONTROL 0x28808 63#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) 64#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) 65#define C_028808_SPECIAL_OP 0xFFFFFF8F 66#define V_028808_SPECIAL_NORMAL 0x00 67#define V_028808_SPECIAL_DISABLE 0x01 68#define V_028808_SPECIAL_RESOLVE_BOX 0x07 69 70#define CB_COLOR0_BASE 0x28040 71#define CB_COLOR1_BASE 0x28044 72#define CB_COLOR2_BASE 0x28048 73#define CB_COLOR3_BASE 0x2804C 74#define CB_COLOR4_BASE 0x28050 75#define CB_COLOR5_BASE 0x28054 76#define CB_COLOR6_BASE 0x28058 77#define CB_COLOR7_BASE 0x2805C 78#define CB_COLOR7_FRAG 0x280FC 79 80#define CB_COLOR0_SIZE 0x28060 81#define CB_COLOR0_VIEW 0x28080 82#define R_028080_CB_COLOR0_VIEW 0x028080 83#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) 84#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) 85#define C_028080_SLICE_START 0xFFFFF800 86#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) 87#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 88#define C_028080_SLICE_MAX 0xFF001FFF 89#define R_028084_CB_COLOR1_VIEW 0x028084 90#define R_028088_CB_COLOR2_VIEW 0x028088 91#define R_02808C_CB_COLOR3_VIEW 0x02808C 92#define R_028090_CB_COLOR4_VIEW 0x028090 93#define R_028094_CB_COLOR5_VIEW 0x028094 94#define R_028098_CB_COLOR6_VIEW 0x028098 95#define R_02809C_CB_COLOR7_VIEW 0x02809C 96#define R_028100_CB_COLOR0_MASK 0x028100 97#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) 98#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) 99#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 100#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) 101#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) 102#define C_028100_FMASK_TILE_MAX 0x00000FFF 103#define R_028104_CB_COLOR1_MASK 0x028104 104#define R_028108_CB_COLOR2_MASK 0x028108 105#define R_02810C_CB_COLOR3_MASK 0x02810C 106#define R_028110_CB_COLOR4_MASK 0x028110 107#define R_028114_CB_COLOR5_MASK 0x028114 108#define R_028118_CB_COLOR6_MASK 0x028118 109#define R_02811C_CB_COLOR7_MASK 0x02811C 110#define CB_COLOR0_INFO 0x280a0 111# define CB_FORMAT(x) ((x) << 2) 112# define CB_ARRAY_MODE(x) ((x) << 8) 113# define CB_SOURCE_FORMAT(x) ((x) << 27) 114# define CB_SF_EXPORT_FULL 0 115# define CB_SF_EXPORT_NORM 1 116#define CB_COLOR0_TILE 0x280c0 117#define CB_COLOR0_FRAG 0x280e0 118#define CB_COLOR0_MASK 0x28100 119 120#define SQ_ALU_CONST_CACHE_PS_0 0x28940 121#define SQ_ALU_CONST_CACHE_PS_1 0x28944 122#define SQ_ALU_CONST_CACHE_PS_2 0x28948 123#define SQ_ALU_CONST_CACHE_PS_3 0x2894c 124#define SQ_ALU_CONST_CACHE_PS_4 0x28950 125#define SQ_ALU_CONST_CACHE_PS_5 0x28954 126#define SQ_ALU_CONST_CACHE_PS_6 0x28958 127#define SQ_ALU_CONST_CACHE_PS_7 0x2895c 128#define SQ_ALU_CONST_CACHE_PS_8 0x28960 129#define SQ_ALU_CONST_CACHE_PS_9 0x28964 130#define SQ_ALU_CONST_CACHE_PS_10 0x28968 131#define SQ_ALU_CONST_CACHE_PS_11 0x2896c 132#define SQ_ALU_CONST_CACHE_PS_12 0x28970 133#define SQ_ALU_CONST_CACHE_PS_13 0x28974 134#define SQ_ALU_CONST_CACHE_PS_14 0x28978 135#define SQ_ALU_CONST_CACHE_PS_15 0x2897c 136#define SQ_ALU_CONST_CACHE_VS_0 0x28980 137#define SQ_ALU_CONST_CACHE_VS_1 0x28984 138#define SQ_ALU_CONST_CACHE_VS_2 0x28988 139#define SQ_ALU_CONST_CACHE_VS_3 0x2898c 140#define SQ_ALU_CONST_CACHE_VS_4 0x28990 141#define SQ_ALU_CONST_CACHE_VS_5 0x28994 142#define SQ_ALU_CONST_CACHE_VS_6 0x28998 143#define SQ_ALU_CONST_CACHE_VS_7 0x2899c 144#define SQ_ALU_CONST_CACHE_VS_8 0x289a0 145#define SQ_ALU_CONST_CACHE_VS_9 0x289a4 146#define SQ_ALU_CONST_CACHE_VS_10 0x289a8 147#define SQ_ALU_CONST_CACHE_VS_11 0x289ac 148#define SQ_ALU_CONST_CACHE_VS_12 0x289b0 149#define SQ_ALU_CONST_CACHE_VS_13 0x289b4 150#define SQ_ALU_CONST_CACHE_VS_14 0x289b8 151#define SQ_ALU_CONST_CACHE_VS_15 0x289bc 152#define SQ_ALU_CONST_CACHE_GS_0 0x289c0 153#define SQ_ALU_CONST_CACHE_GS_1 0x289c4 154#define SQ_ALU_CONST_CACHE_GS_2 0x289c8 155#define SQ_ALU_CONST_CACHE_GS_3 0x289cc 156#define SQ_ALU_CONST_CACHE_GS_4 0x289d0 157#define SQ_ALU_CONST_CACHE_GS_5 0x289d4 158#define SQ_ALU_CONST_CACHE_GS_6 0x289d8 159#define SQ_ALU_CONST_CACHE_GS_7 0x289dc 160#define SQ_ALU_CONST_CACHE_GS_8 0x289e0 161#define SQ_ALU_CONST_CACHE_GS_9 0x289e4 162#define SQ_ALU_CONST_CACHE_GS_10 0x289e8 163#define SQ_ALU_CONST_CACHE_GS_11 0x289ec 164#define SQ_ALU_CONST_CACHE_GS_12 0x289f0 165#define SQ_ALU_CONST_CACHE_GS_13 0x289f4 166#define SQ_ALU_CONST_CACHE_GS_14 0x289f8 167#define SQ_ALU_CONST_CACHE_GS_15 0x289fc 168 169#define CONFIG_MEMSIZE 0x5428 170#define CONFIG_CNTL 0x5424 171#define CP_STALLED_STAT1 0x8674 172#define CP_STALLED_STAT2 0x8678 173#define CP_BUSY_STAT 0x867C 174#define CP_STAT 0x8680 175#define CP_COHER_BASE 0x85F8 176#define CP_DEBUG 0xC1FC 177#define R_0086D8_CP_ME_CNTL 0x86D8 178#define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26) 179#define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF) 180#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 181#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 182#define CP_ME_RAM_DATA 0xC160 183#define CP_ME_RAM_RADDR 0xC158 184#define CP_ME_RAM_WADDR 0xC15C 185#define CP_MEQ_THRESHOLDS 0x8764 186#define MEQ_END(x) ((x) << 16) 187#define ROQ_END(x) ((x) << 24) 188#define CP_PERFMON_CNTL 0x87FC 189#define CP_PFP_UCODE_ADDR 0xC150 190#define CP_PFP_UCODE_DATA 0xC154 191#define CP_QUEUE_THRESHOLDS 0x8760 192#define ROQ_IB1_START(x) ((x) << 0) 193#define ROQ_IB2_START(x) ((x) << 8) 194#define CP_RB_BASE 0xC100 195#define CP_RB_CNTL 0xC104 196#define RB_BUFSZ(x) ((x) << 0) 197#define RB_BLKSZ(x) ((x) << 8) 198#define RB_NO_UPDATE (1 << 27) 199#define RB_RPTR_WR_ENA (1 << 31) 200#define BUF_SWAP_32BIT (2 << 16) 201#define CP_RB_RPTR 0x8700 202#define CP_RB_RPTR_ADDR 0xC10C 203#define RB_RPTR_SWAP(x) ((x) << 0) 204#define CP_RB_RPTR_ADDR_HI 0xC110 205#define CP_RB_RPTR_WR 0xC108 206#define CP_RB_WPTR 0xC114 207#define CP_RB_WPTR_ADDR 0xC118 208#define CP_RB_WPTR_ADDR_HI 0xC11C 209#define CP_RB_WPTR_DELAY 0x8704 210#define CP_ROQ_IB1_STAT 0x8784 211#define CP_ROQ_IB2_STAT 0x8788 212#define CP_SEM_WAIT_TIMER 0x85BC 213 214#define DB_DEBUG 0x9830 215#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 216#define DB_DEPTH_BASE 0x2800C 217#define DB_HTILE_DATA_BASE 0x28014 218#define DB_HTILE_SURFACE 0x28D24 219#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) 220#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 221#define C_028D24_HTILE_WIDTH 0xFFFFFFFE 222#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 223#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 224#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD 225#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) 226#define DB_WATERMARKS 0x9838 227#define DEPTH_FREE(x) ((x) << 0) 228#define DEPTH_FLUSH(x) ((x) << 5) 229#define DEPTH_PENDING_FREE(x) ((x) << 15) 230#define DEPTH_CACHELINE_FREE(x) ((x) << 20) 231 232#define DCP_TILING_CONFIG 0x6CA0 233#define PIPE_TILING(x) ((x) << 1) 234#define BANK_TILING(x) ((x) << 4) 235#define GROUP_SIZE(x) ((x) << 6) 236#define ROW_TILING(x) ((x) << 8) 237#define BANK_SWAPS(x) ((x) << 11) 238#define SAMPLE_SPLIT(x) ((x) << 14) 239#define BACKEND_MAP(x) ((x) << 16) 240 241#define GB_TILING_CONFIG 0x98F0 242#define PIPE_TILING__SHIFT 1 243#define PIPE_TILING__MASK 0x0000000e 244 245#define GC_USER_SHADER_PIPE_CONFIG 0x8954 246#define INACTIVE_QD_PIPES(x) ((x) << 8) 247#define INACTIVE_QD_PIPES_MASK 0x0000FF00 248#define INACTIVE_SIMDS(x) ((x) << 16) 249#define INACTIVE_SIMDS_MASK 0x00FF0000 250 251#define SQ_CONFIG 0x8c00 252# define VC_ENABLE (1 << 0) 253# define EXPORT_SRC_C (1 << 1) 254# define DX9_CONSTS (1 << 2) 255# define ALU_INST_PREFER_VECTOR (1 << 3) 256# define DX10_CLAMP (1 << 4) 257# define CLAUSE_SEQ_PRIO(x) ((x) << 8) 258# define PS_PRIO(x) ((x) << 24) 259# define VS_PRIO(x) ((x) << 26) 260# define GS_PRIO(x) ((x) << 28) 261# define ES_PRIO(x) ((x) << 30) 262#define SQ_GPR_RESOURCE_MGMT_1 0x8c04 263# define NUM_PS_GPRS(x) ((x) << 0) 264# define NUM_VS_GPRS(x) ((x) << 16) 265# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 266#define SQ_GPR_RESOURCE_MGMT_2 0x8c08 267# define NUM_GS_GPRS(x) ((x) << 0) 268# define NUM_ES_GPRS(x) ((x) << 16) 269#define SQ_THREAD_RESOURCE_MGMT 0x8c0c 270# define NUM_PS_THREADS(x) ((x) << 0) 271# define NUM_VS_THREADS(x) ((x) << 8) 272# define NUM_GS_THREADS(x) ((x) << 16) 273# define NUM_ES_THREADS(x) ((x) << 24) 274#define SQ_STACK_RESOURCE_MGMT_1 0x8c10 275# define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 276# define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 277#define SQ_STACK_RESOURCE_MGMT_2 0x8c14 278# define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 279# define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 280#define SQ_ESGS_RING_BASE 0x8c40 281#define SQ_GSVS_RING_BASE 0x8c48 282#define SQ_ESTMP_RING_BASE 0x8c50 283#define SQ_GSTMP_RING_BASE 0x8c58 284#define SQ_VSTMP_RING_BASE 0x8c60 285#define SQ_PSTMP_RING_BASE 0x8c68 286#define SQ_FBUF_RING_BASE 0x8c70 287#define SQ_REDUC_RING_BASE 0x8c78 288 289#define GRBM_CNTL 0x8000 290# define GRBM_READ_TIMEOUT(x) ((x) << 0) 291#define GRBM_STATUS 0x8010 292#define CMDFIFO_AVAIL_MASK 0x0000001F 293#define GUI_ACTIVE (1<<31) 294#define GRBM_STATUS2 0x8014 295#define GRBM_SOFT_RESET 0x8020 296#define SOFT_RESET_CP (1<<0) 297 298#define CG_THERMAL_CTRL 0x7F0 299#define DIG_THERM_DPM(x) ((x) << 12) 300#define DIG_THERM_DPM_MASK 0x000FF000 301#define DIG_THERM_DPM_SHIFT 12 302#define CG_THERMAL_STATUS 0x7F4 303#define ASIC_T(x) ((x) << 0) 304#define ASIC_T_MASK 0x1FF 305#define ASIC_T_SHIFT 0 306#define CG_THERMAL_INT 0x7F8 307#define DIG_THERM_INTH(x) ((x) << 8) 308#define DIG_THERM_INTH_MASK 0x0000FF00 309#define DIG_THERM_INTH_SHIFT 8 310#define DIG_THERM_INTL(x) ((x) << 16) 311#define DIG_THERM_INTL_MASK 0x00FF0000 312#define DIG_THERM_INTL_SHIFT 16 313#define THERM_INT_MASK_HIGH (1 << 24) 314#define THERM_INT_MASK_LOW (1 << 25) 315 316#define RV770_CG_THERMAL_INT 0x734 317 318#define HDP_HOST_PATH_CNTL 0x2C00 319#define HDP_NONSURFACE_BASE 0x2C04 320#define HDP_NONSURFACE_INFO 0x2C08 321#define HDP_NONSURFACE_SIZE 0x2C0C 322#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 323#define HDP_TILING_CONFIG 0x2F3C 324#define HDP_DEBUG1 0x2F34 325 326#define MC_CONFIG 0x2000 327#define MC_VM_AGP_TOP 0x2184 328#define MC_VM_AGP_BOT 0x2188 329#define MC_VM_AGP_BASE 0x218C 330#define MC_VM_FB_LOCATION 0x2180 331#define MC_VM_L1_TLB_MCB_RD_UVD_CNTL 0x2124 332#define ENABLE_L1_TLB (1 << 0) 333#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 334#define ENABLE_L1_STRICT_ORDERING (1 << 2) 335#define SYSTEM_ACCESS_MODE_MASK 0x000000C0 336#define SYSTEM_ACCESS_MODE_SHIFT 6 337#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 338#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 339#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 340#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 341#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 342#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 343#define ENABLE_SEMAPHORE_MODE (1 << 10) 344#define ENABLE_WAIT_L2_QUERY (1 << 11) 345#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 346#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 347#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 348#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 349#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 350#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 351#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 352#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 353#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 354#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 355#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 356#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 357#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 358#define MC_VM_L1_TLB_MCB_WR_UVD_CNTL 0x212c 359#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 360#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 361#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 362#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 363#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 364#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 365#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 366#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 367#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 368#define LOGICAL_PAGE_NUMBER_SHIFT 0 369#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 370#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 371 372#define RS_DQ_RD_RET_CONF 0x2348 373 374#define PA_CL_ENHANCE 0x8A14 375#define CLIP_VTX_REORDER_ENA (1 << 0) 376#define NUM_CLIP_SEQ(x) ((x) << 1) 377#define PA_SC_AA_CONFIG 0x28C04 378#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 379#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 380#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 381#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 382#define S0_X(x) ((x) << 0) 383#define S0_Y(x) ((x) << 4) 384#define S1_X(x) ((x) << 8) 385#define S1_Y(x) ((x) << 12) 386#define S2_X(x) ((x) << 16) 387#define S2_Y(x) ((x) << 20) 388#define S3_X(x) ((x) << 24) 389#define S3_Y(x) ((x) << 28) 390#define S4_X(x) ((x) << 0) 391#define S4_Y(x) ((x) << 4) 392#define S5_X(x) ((x) << 8) 393#define S5_Y(x) ((x) << 12) 394#define S6_X(x) ((x) << 16) 395#define S6_Y(x) ((x) << 20) 396#define S7_X(x) ((x) << 24) 397#define S7_Y(x) ((x) << 28) 398#define PA_SC_CLIPRECT_RULE 0x2820c 399#define PA_SC_ENHANCE 0x8BF0 400#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 401#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 402#define PA_SC_LINE_STIPPLE 0x28A0C 403#define PA_SC_LINE_STIPPLE_STATE 0x8B10 404#define PA_SC_MODE_CNTL 0x28A4C 405#define PA_SC_MULTI_CHIP_CNTL 0x8B20 406 407#define PA_SC_SCREEN_SCISSOR_TL 0x28030 408#define PA_SC_GENERIC_SCISSOR_TL 0x28240 409#define PA_SC_WINDOW_SCISSOR_TL 0x28204 410 411#define PCIE_PORT_INDEX 0x0038 412#define PCIE_PORT_DATA 0x003C 413 414#define CHMAP 0x2004 415#define NOOFCHAN_SHIFT 12 416#define NOOFCHAN_MASK 0x00003000 417 418#define RAMCFG 0x2408 419#define NOOFBANK_SHIFT 0 420#define NOOFBANK_MASK 0x00000001 421#define NOOFRANK_SHIFT 1 422#define NOOFRANK_MASK 0x00000002 423#define NOOFROWS_SHIFT 2 424#define NOOFROWS_MASK 0x0000001C 425#define NOOFCOLS_SHIFT 5 426#define NOOFCOLS_MASK 0x00000060 427#define CHANSIZE_SHIFT 7 428#define CHANSIZE_MASK 0x00000080 429#define BURSTLENGTH_SHIFT 8 430#define BURSTLENGTH_MASK 0x00000100 431#define CHANSIZE_OVERRIDE (1 << 10) 432 433#define SCRATCH_REG0 0x8500 434#define SCRATCH_REG1 0x8504 435#define SCRATCH_REG2 0x8508 436#define SCRATCH_REG3 0x850C 437#define SCRATCH_REG4 0x8510 438#define SCRATCH_REG5 0x8514 439#define SCRATCH_REG6 0x8518 440#define SCRATCH_REG7 0x851C 441#define SCRATCH_UMSK 0x8540 442#define SCRATCH_ADDR 0x8544 443 444#define SPI_CONFIG_CNTL 0x9100 445#define GPR_WRITE_PRIORITY(x) ((x) << 0) 446#define DISABLE_INTERP_1 (1 << 5) 447#define SPI_CONFIG_CNTL_1 0x913C 448#define VTX_DONE_DELAY(x) ((x) << 0) 449#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 450#define SPI_INPUT_Z 0x286D8 451#define SPI_PS_IN_CONTROL_0 0x286CC 452#define NUM_INTERP(x) ((x)<<0) 453#define POSITION_ENA (1<<8) 454#define POSITION_CENTROID (1<<9) 455#define POSITION_ADDR(x) ((x)<<10) 456#define PARAM_GEN(x) ((x)<<15) 457#define PARAM_GEN_ADDR(x) ((x)<<19) 458#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 459#define PERSP_GRADIENT_ENA (1<<28) 460#define LINEAR_GRADIENT_ENA (1<<29) 461#define POSITION_SAMPLE (1<<30) 462#define BARYC_AT_SAMPLE_ENA (1<<31) 463#define SPI_PS_IN_CONTROL_1 0x286D0 464#define GEN_INDEX_PIX (1<<0) 465#define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 466#define FRONT_FACE_ENA (1<<8) 467#define FRONT_FACE_CHAN(x) ((x)<<9) 468#define FRONT_FACE_ALL_BITS (1<<11) 469#define FRONT_FACE_ADDR(x) ((x)<<12) 470#define FOG_ADDR(x) ((x)<<17) 471#define FIXED_PT_POSITION_ENA (1<<24) 472#define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 473 474#define SQ_MS_FIFO_SIZES 0x8CF0 475#define CACHE_FIFO_SIZE(x) ((x) << 0) 476#define FETCH_FIFO_HIWATER(x) ((x) << 8) 477#define DONE_FIFO_HIWATER(x) ((x) << 16) 478#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 479#define SQ_PGM_START_ES 0x28880 480#define SQ_PGM_START_FS 0x28894 481#define SQ_PGM_START_GS 0x2886C 482#define SQ_PGM_START_PS 0x28840 483#define SQ_PGM_RESOURCES_PS 0x28850 484#define SQ_PGM_EXPORTS_PS 0x28854 485#define SQ_PGM_CF_OFFSET_PS 0x288cc 486#define SQ_PGM_START_VS 0x28858 487#define SQ_PGM_RESOURCES_VS 0x28868 488#define SQ_PGM_CF_OFFSET_VS 0x288d0 489 490#define SQ_VTX_CONSTANT_WORD0_0 0x30000 491#define SQ_VTX_CONSTANT_WORD1_0 0x30004 492#define SQ_VTX_CONSTANT_WORD2_0 0x30008 493# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 494# define SQ_VTXC_STRIDE(x) ((x) << 8) 495# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 496# define SQ_ENDIAN_NONE 0 497# define SQ_ENDIAN_8IN16 1 498# define SQ_ENDIAN_8IN32 2 499#define SQ_VTX_CONSTANT_WORD3_0 0x3000c 500#define SQ_VTX_CONSTANT_WORD6_0 0x38018 501#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 502#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 503#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 504#define SQ_TEX_VTX_INVALID_BUFFER 0x1 505#define SQ_TEX_VTX_VALID_TEXTURE 0x2 506#define SQ_TEX_VTX_VALID_BUFFER 0x3 507 508 509#define SX_MISC 0x28350 510#define SX_MEMORY_EXPORT_BASE 0x9010 511#define SX_DEBUG_1 0x9054 512#define SMX_EVENT_RELEASE (1 << 0) 513#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 514 515#define TA_CNTL_AUX 0x9508 516#define DISABLE_CUBE_WRAP (1 << 0) 517#define DISABLE_CUBE_ANISO (1 << 1) 518#define SYNC_GRADIENT (1 << 24) 519#define SYNC_WALKER (1 << 25) 520#define SYNC_ALIGNER (1 << 26) 521#define BILINEAR_PRECISION_6_BIT (0 << 31) 522#define BILINEAR_PRECISION_8_BIT (1 << 31) 523 524#define TC_CNTL 0x9608 525#define TC_L2_SIZE(x) ((x)<<5) 526#define L2_DISABLE_LATE_HIT (1<<9) 527 528#define VC_ENHANCE 0x9714 529 530#define VGT_CACHE_INVALIDATION 0x88C4 531#define CACHE_INVALIDATION(x) ((x)<<0) 532#define VC_ONLY 0 533#define TC_ONLY 1 534#define VC_AND_TC 2 535#define VGT_DMA_BASE 0x287E8 536#define VGT_DMA_BASE_HI 0x287E4 537#define VGT_ES_PER_GS 0x88CC 538#define VGT_GS_PER_ES 0x88C8 539#define VGT_GS_PER_VS 0x88E8 540#define VGT_GS_VERTEX_REUSE 0x88D4 541#define VGT_PRIMITIVE_TYPE 0x8958 542#define VGT_NUM_INSTANCES 0x8974 543#define VGT_OUT_DEALLOC_CNTL 0x28C5C 544#define DEALLOC_DIST_MASK 0x0000007F 545#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 546#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 547#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 548#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 549#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 550#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 551#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 552#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 553#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 554#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 555#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 556#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 557#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 558#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 559#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 560#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 561#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 562#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 563#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 564#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 565 566#define VGT_STRMOUT_EN 0x28AB0 567#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 568#define VTX_REUSE_DEPTH_MASK 0x000000FF 569#define VGT_EVENT_INITIATOR 0x28a90 570# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 571# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 572 573#define VM_CONTEXT0_CNTL 0x1410 574#define ENABLE_CONTEXT (1 << 0) 575#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 576#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 577#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 578#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 579#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 580#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 581#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 582#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 583#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 584#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 585#define RESPONSE_TYPE_MASK 0x000000F0 586#define RESPONSE_TYPE_SHIFT 4 587#define VM_L2_CNTL 0x1400 588#define ENABLE_L2_CACHE (1 << 0) 589#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 590#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 591#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 592#define VM_L2_CNTL2 0x1404 593#define INVALIDATE_ALL_L1_TLBS (1 << 0) 594#define INVALIDATE_L2_CACHE (1 << 1) 595#define VM_L2_CNTL3 0x1408 596#define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 597#define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 598#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 599#define VM_L2_STATUS 0x140C 600#define L2_BUSY (1 << 0) 601 602#define WAIT_UNTIL 0x8040 603#define WAIT_CP_DMA_IDLE_bit (1 << 8) 604#define WAIT_2D_IDLE_bit (1 << 14) 605#define WAIT_3D_IDLE_bit (1 << 15) 606#define WAIT_2D_IDLECLEAN_bit (1 << 16) 607#define WAIT_3D_IDLECLEAN_bit (1 << 17) 608 609/* async DMA */ 610#define DMA_TILING_CONFIG 0x3ec4 611#define DMA_CONFIG 0x3e4c 612 613#define DMA_RB_CNTL 0xd000 614# define DMA_RB_ENABLE (1 << 0) 615# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 616# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 617# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 618# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 619# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 620#define DMA_RB_BASE 0xd004 621#define DMA_RB_RPTR 0xd008 622#define DMA_RB_WPTR 0xd00c 623 624#define DMA_RB_RPTR_ADDR_HI 0xd01c 625#define DMA_RB_RPTR_ADDR_LO 0xd020 626 627#define DMA_IB_CNTL 0xd024 628# define DMA_IB_ENABLE (1 << 0) 629# define DMA_IB_SWAP_ENABLE (1 << 4) 630#define DMA_IB_RPTR 0xd028 631#define DMA_CNTL 0xd02c 632# define TRAP_ENABLE (1 << 0) 633# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 634# define SEM_WAIT_INT_ENABLE (1 << 2) 635# define DATA_SWAP_ENABLE (1 << 3) 636# define FENCE_SWAP_ENABLE (1 << 4) 637# define CTXEMPTY_INT_ENABLE (1 << 28) 638#define DMA_STATUS_REG 0xd034 639# define DMA_IDLE (1 << 0) 640#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 641#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 642#define DMA_MODE 0xd0bc 643 644/* async DMA packets */ 645#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 646 (((t) & 0x1) << 23) | \ 647 (((s) & 0x1) << 22) | \ 648 (((n) & 0xFFFF) << 0)) 649/* async DMA Packet types */ 650#define DMA_PACKET_WRITE 0x2 651#define DMA_PACKET_COPY 0x3 652#define DMA_PACKET_INDIRECT_BUFFER 0x4 653#define DMA_PACKET_SEMAPHORE 0x5 654#define DMA_PACKET_FENCE 0x6 655#define DMA_PACKET_TRAP 0x7 656#define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */ 657#define DMA_PACKET_NOP 0xf 658 659#define IH_RB_CNTL 0x3e00 660# define IH_RB_ENABLE (1 << 0) 661# define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 662# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 663# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 664# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 665# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 666# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 667#define IH_RB_BASE 0x3e04 668#define IH_RB_RPTR 0x3e08 669#define IH_RB_WPTR 0x3e0c 670# define RB_OVERFLOW (1 << 0) 671# define WPTR_OFFSET_MASK 0x3fffc 672#define IH_RB_WPTR_ADDR_HI 0x3e10 673#define IH_RB_WPTR_ADDR_LO 0x3e14 674#define IH_CNTL 0x3e18 675# define ENABLE_INTR (1 << 0) 676# define IH_MC_SWAP(x) ((x) << 1) 677# define IH_MC_SWAP_NONE 0 678# define IH_MC_SWAP_16BIT 1 679# define IH_MC_SWAP_32BIT 2 680# define IH_MC_SWAP_64BIT 3 681# define RPTR_REARM (1 << 4) 682# define MC_WRREQ_CREDIT(x) ((x) << 15) 683# define MC_WR_CLEAN_CNT(x) ((x) << 20) 684 685#define RLC_CNTL 0x3f00 686# define RLC_ENABLE (1 << 0) 687#define RLC_HB_BASE 0x3f10 688#define RLC_HB_CNTL 0x3f0c 689#define RLC_HB_RPTR 0x3f20 690#define RLC_HB_WPTR 0x3f1c 691#define RLC_HB_WPTR_LSB_ADDR 0x3f14 692#define RLC_HB_WPTR_MSB_ADDR 0x3f18 693#define RLC_GPU_CLOCK_COUNT_LSB 0x3f38 694#define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c 695#define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40 696#define RLC_MC_CNTL 0x3f44 697#define RLC_UCODE_CNTL 0x3f48 698#define RLC_UCODE_ADDR 0x3f2c 699#define RLC_UCODE_DATA 0x3f30 700 701#define SRBM_SOFT_RESET 0xe60 702# define SOFT_RESET_BIF (1 << 1) 703# define SOFT_RESET_DMA (1 << 12) 704# define SOFT_RESET_RLC (1 << 13) 705# define SOFT_RESET_UVD (1 << 18) 706# define RV770_SOFT_RESET_DMA (1 << 20) 707 708#define BIF_SCRATCH0 0x5438 709 710#define BUS_CNTL 0x5420 711# define BIOS_ROM_DIS (1 << 1) 712# define VGA_COHE_SPEC_TIMER_DIS (1 << 9) 713 714#define CP_INT_CNTL 0xc124 715# define CNTX_BUSY_INT_ENABLE (1 << 19) 716# define CNTX_EMPTY_INT_ENABLE (1 << 20) 717# define SCRATCH_INT_ENABLE (1 << 25) 718# define TIME_STAMP_INT_ENABLE (1 << 26) 719# define IB2_INT_ENABLE (1 << 29) 720# define IB1_INT_ENABLE (1 << 30) 721# define RB_INT_ENABLE (1 << 31) 722#define CP_INT_STATUS 0xc128 723# define SCRATCH_INT_STAT (1 << 25) 724# define TIME_STAMP_INT_STAT (1 << 26) 725# define IB2_INT_STAT (1 << 29) 726# define IB1_INT_STAT (1 << 30) 727# define RB_INT_STAT (1 << 31) 728 729#define GRBM_INT_CNTL 0x8060 730# define RDERR_INT_ENABLE (1 << 0) 731# define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 732# define GUI_IDLE_INT_ENABLE (1 << 19) 733 734#define INTERRUPT_CNTL 0x5468 735# define IH_DUMMY_RD_OVERRIDE (1 << 0) 736# define IH_DUMMY_RD_EN (1 << 1) 737# define IH_REQ_NONSNOOP_EN (1 << 3) 738# define GEN_IH_INT_EN (1 << 8) 739#define INTERRUPT_CNTL2 0x546c 740 741#define D1MODE_VBLANK_STATUS 0x6534 742#define D2MODE_VBLANK_STATUS 0x6d34 743# define DxMODE_VBLANK_OCCURRED (1 << 0) 744# define DxMODE_VBLANK_ACK (1 << 4) 745# define DxMODE_VBLANK_STAT (1 << 12) 746# define DxMODE_VBLANK_INTERRUPT (1 << 16) 747# define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 748#define D1MODE_VLINE_STATUS 0x653c 749#define D2MODE_VLINE_STATUS 0x6d3c 750# define DxMODE_VLINE_OCCURRED (1 << 0) 751# define DxMODE_VLINE_ACK (1 << 4) 752# define DxMODE_VLINE_STAT (1 << 12) 753# define DxMODE_VLINE_INTERRUPT (1 << 16) 754# define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 755#define DxMODE_INT_MASK 0x6540 756# define D1MODE_VBLANK_INT_MASK (1 << 0) 757# define D1MODE_VLINE_INT_MASK (1 << 4) 758# define D2MODE_VBLANK_INT_MASK (1 << 8) 759# define D2MODE_VLINE_INT_MASK (1 << 12) 760#define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 761# define DC_HPD1_INTERRUPT (1 << 18) 762# define DC_HPD2_INTERRUPT (1 << 19) 763#define DISP_INTERRUPT_STATUS 0x7edc 764# define LB_D1_VLINE_INTERRUPT (1 << 2) 765# define LB_D2_VLINE_INTERRUPT (1 << 3) 766# define LB_D1_VBLANK_INTERRUPT (1 << 4) 767# define LB_D2_VBLANK_INTERRUPT (1 << 5) 768# define DACA_AUTODETECT_INTERRUPT (1 << 16) 769# define DACB_AUTODETECT_INTERRUPT (1 << 17) 770# define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 771# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 772# define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 773# define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 774#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 775#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 776# define DC_HPD4_INTERRUPT (1 << 14) 777# define DC_HPD4_RX_INTERRUPT (1 << 15) 778# define DC_HPD3_INTERRUPT (1 << 28) 779# define DC_HPD1_RX_INTERRUPT (1 << 29) 780# define DC_HPD2_RX_INTERRUPT (1 << 30) 781#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 782# define DC_HPD3_RX_INTERRUPT (1 << 0) 783# define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 784# define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 785# define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 786# define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 787# define AUX1_SW_DONE_INTERRUPT (1 << 5) 788# define AUX1_LS_DONE_INTERRUPT (1 << 6) 789# define AUX2_SW_DONE_INTERRUPT (1 << 7) 790# define AUX2_LS_DONE_INTERRUPT (1 << 8) 791# define AUX3_SW_DONE_INTERRUPT (1 << 9) 792# define AUX3_LS_DONE_INTERRUPT (1 << 10) 793# define AUX4_SW_DONE_INTERRUPT (1 << 11) 794# define AUX4_LS_DONE_INTERRUPT (1 << 12) 795# define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 796# define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 797/* DCE 3.2 */ 798# define AUX5_SW_DONE_INTERRUPT (1 << 15) 799# define AUX5_LS_DONE_INTERRUPT (1 << 16) 800# define AUX6_SW_DONE_INTERRUPT (1 << 17) 801# define AUX6_LS_DONE_INTERRUPT (1 << 18) 802# define DC_HPD5_INTERRUPT (1 << 19) 803# define DC_HPD5_RX_INTERRUPT (1 << 20) 804# define DC_HPD6_INTERRUPT (1 << 21) 805# define DC_HPD6_RX_INTERRUPT (1 << 22) 806 807#define DACA_AUTO_DETECT_CONTROL 0x7828 808#define DACB_AUTO_DETECT_CONTROL 0x7a28 809#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 810#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 811# define DACx_AUTODETECT_MODE(x) ((x) << 0) 812# define DACx_AUTODETECT_MODE_NONE 0 813# define DACx_AUTODETECT_MODE_CONNECT 1 814# define DACx_AUTODETECT_MODE_DISCONNECT 2 815# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 816/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 817# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 818 819#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 820#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 821#define DACA_AUTODETECT_INT_CONTROL 0x7838 822#define DACB_AUTODETECT_INT_CONTROL 0x7a38 823# define DACx_AUTODETECT_ACK (1 << 0) 824# define DACx_AUTODETECT_INT_ENABLE (1 << 16) 825 826#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 827#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 828#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 829# define DC_HOT_PLUG_DETECTx_EN (1 << 0) 830 831#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 832#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 833#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 834# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 835# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 836 837/* DCE 3.0 */ 838#define DC_HPD1_INT_STATUS 0x7d00 839#define DC_HPD2_INT_STATUS 0x7d0c 840#define DC_HPD3_INT_STATUS 0x7d18 841#define DC_HPD4_INT_STATUS 0x7d24 842/* DCE 3.2 */ 843#define DC_HPD5_INT_STATUS 0x7dc0 844#define DC_HPD6_INT_STATUS 0x7df4 845# define DC_HPDx_INT_STATUS (1 << 0) 846# define DC_HPDx_SENSE (1 << 1) 847# define DC_HPDx_RX_INT_STATUS (1 << 8) 848 849#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 850#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 851#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 852# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 853# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 854# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 855/* DCE 3.0 */ 856#define DC_HPD1_INT_CONTROL 0x7d04 857#define DC_HPD2_INT_CONTROL 0x7d10 858#define DC_HPD3_INT_CONTROL 0x7d1c 859#define DC_HPD4_INT_CONTROL 0x7d28 860/* DCE 3.2 */ 861#define DC_HPD5_INT_CONTROL 0x7dc4 862#define DC_HPD6_INT_CONTROL 0x7df8 863# define DC_HPDx_INT_ACK (1 << 0) 864# define DC_HPDx_INT_POLARITY (1 << 8) 865# define DC_HPDx_INT_EN (1 << 16) 866# define DC_HPDx_RX_INT_ACK (1 << 20) 867# define DC_HPDx_RX_INT_EN (1 << 24) 868 869/* DCE 3.0 */ 870#define DC_HPD1_CONTROL 0x7d08 871#define DC_HPD2_CONTROL 0x7d14 872#define DC_HPD3_CONTROL 0x7d20 873#define DC_HPD4_CONTROL 0x7d2c 874/* DCE 3.2 */ 875#define DC_HPD5_CONTROL 0x7dc8 876#define DC_HPD6_CONTROL 0x7dfc 877# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 878# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 879/* DCE 3.2 */ 880# define DC_HPDx_EN (1 << 28) 881 882#define D1GRPH_INTERRUPT_STATUS 0x6158 883#define D2GRPH_INTERRUPT_STATUS 0x6958 884# define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) 885# define DxGRPH_PFLIP_INT_CLEAR (1 << 8) 886#define D1GRPH_INTERRUPT_CONTROL 0x615c 887#define D2GRPH_INTERRUPT_CONTROL 0x695c 888# define DxGRPH_PFLIP_INT_MASK (1 << 0) 889# define DxGRPH_PFLIP_INT_TYPE (1 << 8) 890 891/* PCIE link stuff */ 892#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 893# define LC_POINT_7_PLUS_EN (1 << 6) 894#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 895# define LC_LINK_WIDTH_SHIFT 0 896# define LC_LINK_WIDTH_MASK 0x7 897# define LC_LINK_WIDTH_X0 0 898# define LC_LINK_WIDTH_X1 1 899# define LC_LINK_WIDTH_X2 2 900# define LC_LINK_WIDTH_X4 3 901# define LC_LINK_WIDTH_X8 4 902# define LC_LINK_WIDTH_X16 6 903# define LC_LINK_WIDTH_RD_SHIFT 4 904# define LC_LINK_WIDTH_RD_MASK 0x70 905# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 906# define LC_RECONFIG_NOW (1 << 8) 907# define LC_RENEGOTIATION_SUPPORT (1 << 9) 908# define LC_RENEGOTIATE_EN (1 << 10) 909# define LC_SHORT_RECONFIG_EN (1 << 11) 910# define LC_UPCONFIGURE_SUPPORT (1 << 12) 911# define LC_UPCONFIGURE_DIS (1 << 13) 912#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 913# define LC_GEN2_EN_STRAP (1 << 0) 914# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 915# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 916# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 917# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 918# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 919# define LC_CURRENT_DATA_RATE (1 << 11) 920# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 921# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 922# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 923# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 924#define MM_CFGREGS_CNTL 0x544c 925# define MM_WR_TO_CFG_EN (1 << 3) 926#define LINK_CNTL2 0x88 /* F0 */ 927# define TARGET_LINK_SPEED_MASK (0xf << 0) 928# define SELECTABLE_DEEMPHASIS (1 << 6) 929 930/* Audio */ 931#define AZ_HOT_PLUG_CONTROL 0x7300 932# define AZ_FORCE_CODEC_WAKE (1 << 0) 933# define JACK_DETECTION_ENABLE (1 << 4) 934# define UNSOLICITED_RESPONSE_ENABLE (1 << 8) 935# define CODEC_HOT_PLUG_ENABLE (1 << 12) 936# define AUDIO_ENABLED (1 << 31) 937/* DCE3 adds */ 938# define PIN0_JACK_DETECTION_ENABLE (1 << 4) 939# define PIN1_JACK_DETECTION_ENABLE (1 << 5) 940# define PIN2_JACK_DETECTION_ENABLE (1 << 6) 941# define PIN3_JACK_DETECTION_ENABLE (1 << 7) 942# define PIN0_AUDIO_ENABLED (1 << 24) 943# define PIN1_AUDIO_ENABLED (1 << 25) 944# define PIN2_AUDIO_ENABLED (1 << 26) 945# define PIN3_AUDIO_ENABLED (1 << 27) 946 947/* Audio clocks DCE 2.0/3.0 */ 948#define AUDIO_DTO 0x7340 949# define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0) 950# define AUDIO_DTO_MODULE(x) (((x) & 0xffff) << 16) 951 952/* Audio clocks DCE 3.2 */ 953#define DCCG_AUDIO_DTO0_PHASE 0x0514 954#define DCCG_AUDIO_DTO0_MODULE 0x0518 955#define DCCG_AUDIO_DTO0_LOAD 0x051c 956# define DTO_LOAD (1 << 31) 957#define DCCG_AUDIO_DTO0_CNTL 0x0520 958# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) 959# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 960# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 961 962#define DCCG_AUDIO_DTO1_PHASE 0x0524 963#define DCCG_AUDIO_DTO1_MODULE 0x0528 964#define DCCG_AUDIO_DTO1_LOAD 0x052c 965#define DCCG_AUDIO_DTO1_CNTL 0x0530 966 967#define DCCG_AUDIO_DTO_SELECT 0x0534 968 969/* digital blocks */ 970#define TMDSA_CNTL 0x7880 971# define TMDSA_HDMI_EN (1 << 2) 972#define LVTMA_CNTL 0x7a80 973# define LVTMA_HDMI_EN (1 << 2) 974#define DDIA_CNTL 0x7200 975# define DDIA_HDMI_EN (1 << 2) 976#define DIG0_CNTL 0x75a0 977# define DIG_MODE(x) (((x) & 7) << 8) 978# define DIG_MODE_DP 0 979# define DIG_MODE_LVDS 1 980# define DIG_MODE_TMDS_DVI 2 981# define DIG_MODE_TMDS_HDMI 3 982# define DIG_MODE_SDVO 4 983#define DIG1_CNTL 0x79a0 984 985#define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x71bc 986#define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) 987#define SPEAKER_ALLOCATION_MASK (0x7f << 0) 988#define SPEAKER_ALLOCATION_SHIFT 0 989#define HDMI_CONNECTION (1 << 16) 990#define DP_CONNECTION (1 << 17) 991 992#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */ 993#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */ 994#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */ 995#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */ 996#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */ 997#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */ 998#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */ 999#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */ 1000#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */ 1001#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */ 1002#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */ 1003#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */ 1004#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */ 1005#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */ 1006# define MAX_CHANNELS(x) (((x) & 0x7) << 0) 1007/* max channels minus one. 7 = 8 channels */ 1008# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 1009# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 1010# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 1011/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 1012 * bit0 = 32 kHz 1013 * bit1 = 44.1 kHz 1014 * bit2 = 48 kHz 1015 * bit3 = 88.2 kHz 1016 * bit4 = 96 kHz 1017 * bit5 = 176.4 kHz 1018 * bit6 = 192 kHz 1019 */ 1020 1021/* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one 1022 * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly 1023 * different due to the new DIG blocks, but also have 2 instances. 1024 * DCE 3.0 HDMI blocks are part of each DIG encoder. 1025 */ 1026 1027/* rs6xx/rs740/r6xx/dce3 */ 1028#define HDMI0_CONTROL 0x7400 1029/* rs6xx/rs740/r6xx */ 1030# define HDMI0_ENABLE (1 << 0) 1031# define HDMI0_STREAM(x) (((x) & 3) << 2) 1032# define HDMI0_STREAM_TMDSA 0 1033# define HDMI0_STREAM_LVTMA 1 1034# define HDMI0_STREAM_DVOA 2 1035# define HDMI0_STREAM_DDIA 3 1036/* rs6xx/r6xx/dce3 */ 1037# define HDMI0_ERROR_ACK (1 << 8) 1038# define HDMI0_ERROR_MASK (1 << 9) 1039#define HDMI0_STATUS 0x7404 1040# define HDMI0_ACTIVE_AVMUTE (1 << 0) 1041# define HDMI0_AUDIO_ENABLE (1 << 4) 1042# define HDMI0_AZ_FORMAT_WTRIG (1 << 28) 1043# define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) 1044#define HDMI0_AUDIO_PACKET_CONTROL 0x7408 1045# define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) 1046# define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 1047# define HDMI0_AUDIO_DELAY_EN_MASK (3 << 4) 1048# define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) 1049# define HDMI0_AUDIO_TEST_EN (1 << 12) 1050# define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 1051# define HDMI0_AUDIO_PACKETS_PER_LINE_MASK (0x1f << 16) 1052# define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) 1053# define HDMI0_60958_CS_UPDATE (1 << 26) 1054# define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) 1055# define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) 1056#define HDMI0_AUDIO_CRC_CONTROL 0x740c 1057# define HDMI0_AUDIO_CRC_EN (1 << 0) 1058#define DCE3_HDMI0_ACR_PACKET_CONTROL 0x740c 1059#define HDMI0_VBI_PACKET_CONTROL 0x7410 1060# define HDMI0_NULL_SEND (1 << 0) 1061# define HDMI0_GC_SEND (1 << 4) 1062# define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 1063#define HDMI0_INFOFRAME_CONTROL0 0x7414 1064# define HDMI0_AVI_INFO_SEND (1 << 0) 1065# define HDMI0_AVI_INFO_CONT (1 << 1) 1066# define HDMI0_AUDIO_INFO_SEND (1 << 4) 1067# define HDMI0_AUDIO_INFO_CONT (1 << 5) 1068# define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */ 1069# define HDMI0_AUDIO_INFO_UPDATE (1 << 7) 1070# define HDMI0_MPEG_INFO_SEND (1 << 8) 1071# define HDMI0_MPEG_INFO_CONT (1 << 9) 1072# define HDMI0_MPEG_INFO_UPDATE (1 << 10) 1073#define HDMI0_INFOFRAME_CONTROL1 0x7418 1074# define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 1075# define HDMI0_AVI_INFO_LINE_MASK (0x3f << 0) 1076# define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 1077# define HDMI0_AUDIO_INFO_LINE_MASK (0x3f << 8) 1078# define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 1079#define HDMI0_GENERIC_PACKET_CONTROL 0x741c 1080# define HDMI0_GENERIC0_SEND (1 << 0) 1081# define HDMI0_GENERIC0_CONT (1 << 1) 1082# define HDMI0_GENERIC0_UPDATE (1 << 2) 1083# define HDMI0_GENERIC1_SEND (1 << 4) 1084# define HDMI0_GENERIC1_CONT (1 << 5) 1085# define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 1086# define HDMI0_GENERIC0_LINE_MASK (0x3f << 16) 1087# define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 1088# define HDMI0_GENERIC1_LINE_MASK (0x3f << 24) 1089#define HDMI0_GC 0x7428 1090# define HDMI0_GC_AVMUTE (1 << 0) 1091#define HDMI0_AVI_INFO0 0x7454 1092# define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1093# define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) 1094# define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) 1095# define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) 1096# define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) 1097# define HDMI0_AVI_INFO_Y_RGB 0 1098# define HDMI0_AVI_INFO_Y_YCBCR422 1 1099# define HDMI0_AVI_INFO_Y_YCBCR444 2 1100# define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 1101# define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) 1102# define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) 1103# define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) 1104# define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 1105# define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) 1106# define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 1107#define HDMI0_AVI_INFO1 0x7458 1108# define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 1109# define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 1110# define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 1111#define HDMI0_AVI_INFO2 0x745c 1112# define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 1113# define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 1114#define HDMI0_AVI_INFO3 0x7460 1115# define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 1116# define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) 1117#define HDMI0_MPEG_INFO0 0x7464 1118# define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1119# define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 1120# define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 1121# define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 1122#define HDMI0_MPEG_INFO1 0x7468 1123# define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 1124# define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) 1125# define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) 1126#define HDMI0_GENERIC0_HDR 0x746c 1127#define HDMI0_GENERIC0_0 0x7470 1128#define HDMI0_GENERIC0_1 0x7474 1129#define HDMI0_GENERIC0_2 0x7478 1130#define HDMI0_GENERIC0_3 0x747c 1131#define HDMI0_GENERIC0_4 0x7480 1132#define HDMI0_GENERIC0_5 0x7484 1133#define HDMI0_GENERIC0_6 0x7488 1134#define HDMI0_GENERIC1_HDR 0x748c 1135#define HDMI0_GENERIC1_0 0x7490 1136#define HDMI0_GENERIC1_1 0x7494 1137#define HDMI0_GENERIC1_2 0x7498 1138#define HDMI0_GENERIC1_3 0x749c 1139#define HDMI0_GENERIC1_4 0x74a0 1140#define HDMI0_GENERIC1_5 0x74a4 1141#define HDMI0_GENERIC1_6 0x74a8 1142#define HDMI0_ACR_32_0 0x74ac 1143# define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 1144# define HDMI0_ACR_CTS_32_MASK (0xfffff << 12) 1145#define HDMI0_ACR_32_1 0x74b0 1146# define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) 1147# define HDMI0_ACR_N_32_MASK (0xfffff << 0) 1148#define HDMI0_ACR_44_0 0x74b4 1149# define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 1150# define HDMI0_ACR_CTS_44_MASK (0xfffff << 12) 1151#define HDMI0_ACR_44_1 0x74b8 1152# define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) 1153# define HDMI0_ACR_N_44_MASK (0xfffff << 0) 1154#define HDMI0_ACR_48_0 0x74bc 1155# define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 1156# define HDMI0_ACR_CTS_48_MASK (0xfffff << 12) 1157#define HDMI0_ACR_48_1 0x74c0 1158# define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) 1159# define HDMI0_ACR_N_48_MASK (0xfffff << 0) 1160#define HDMI0_ACR_STATUS_0 0x74c4 1161#define HDMI0_ACR_STATUS_1 0x74c8 1162#define HDMI0_AUDIO_INFO0 0x74cc 1163# define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1164# define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) 1165#define HDMI0_AUDIO_INFO1 0x74d0 1166# define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 1167# define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 1168# define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 1169# define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 1170#define HDMI0_60958_0 0x74d4 1171# define HDMI0_60958_CS_A(x) (((x) & 1) << 0) 1172# define HDMI0_60958_CS_B(x) (((x) & 1) << 1) 1173# define HDMI0_60958_CS_C(x) (((x) & 1) << 2) 1174# define HDMI0_60958_CS_D(x) (((x) & 3) << 3) 1175# define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) 1176# define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 1177# define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 1178# define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 1179# define HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK (0xf << 20) 1180# define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 1181# define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 1182# define HDMI0_60958_CS_CLOCK_ACCURACY_MASK (3 << 28) 1183#define HDMI0_60958_1 0x74d8 1184# define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 1185# define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 1186# define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) 1187# define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) 1188# define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 1189# define HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK (0xf << 20) 1190#define HDMI0_ACR_PACKET_CONTROL 0x74dc 1191# define HDMI0_ACR_SEND (1 << 0) 1192# define HDMI0_ACR_CONT (1 << 1) 1193# define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) 1194# define HDMI0_ACR_HW 0 1195# define HDMI0_ACR_32 1 1196# define HDMI0_ACR_44 2 1197# define HDMI0_ACR_48 3 1198# define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 1199# define HDMI0_ACR_AUTO_SEND (1 << 12) 1200#define DCE3_HDMI0_AUDIO_CRC_CONTROL 0x74dc 1201#define HDMI0_RAMP_CONTROL0 0x74e0 1202# define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 1203#define HDMI0_RAMP_CONTROL1 0x74e4 1204# define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 1205#define HDMI0_RAMP_CONTROL2 0x74e8 1206# define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 1207#define HDMI0_RAMP_CONTROL3 0x74ec 1208# define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 1209/* HDMI0_60958_2 is r7xx only */ 1210#define HDMI0_60958_2 0x74f0 1211# define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 1212# define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 1213# define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 1214# define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 1215# define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 1216# define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 1217/* r6xx only; second instance starts at 0x7700 */ 1218#define HDMI1_CONTROL 0x7700 1219#define HDMI1_STATUS 0x7704 1220#define HDMI1_AUDIO_PACKET_CONTROL 0x7708 1221/* DCE3; second instance starts at 0x7800 NOT 0x7700 */ 1222#define DCE3_HDMI1_CONTROL 0x7800 1223#define DCE3_HDMI1_STATUS 0x7804 1224#define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 1225/* DCE3.2 (for interrupts) */ 1226#define AFMT_STATUS 0x7600 1227# define AFMT_AUDIO_ENABLE (1 << 4) 1228# define AFMT_AZ_FORMAT_WTRIG (1 << 28) 1229# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 1230# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 1231#define AFMT_AUDIO_PACKET_CONTROL 0x7604 1232# define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 1233# define AFMT_AUDIO_TEST_EN (1 << 12) 1234# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 1235# define AFMT_60958_CS_UPDATE (1 << 26) 1236# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 1237# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 1238# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 1239# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 1240 1241/* DCE3 FMT blocks */ 1242#define FMT_CONTROL 0x6700 1243# define FMT_PIXEL_ENCODING (1 << 16) 1244 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ 1245#define FMT_BIT_DEPTH_CONTROL 0x6710 1246# define FMT_TRUNCATE_EN (1 << 0) 1247# define FMT_TRUNCATE_DEPTH (1 << 4) 1248# define FMT_SPATIAL_DITHER_EN (1 << 8) 1249# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 1250# define FMT_SPATIAL_DITHER_DEPTH (1 << 12) 1251# define FMT_FRAME_RANDOM_ENABLE (1 << 13) 1252# define FMT_RGB_RANDOM_ENABLE (1 << 14) 1253# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 1254# define FMT_TEMPORAL_DITHER_EN (1 << 16) 1255# define FMT_TEMPORAL_DITHER_DEPTH (1 << 20) 1256# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 1257# define FMT_TEMPORAL_LEVEL (1 << 24) 1258# define FMT_TEMPORAL_DITHER_RESET (1 << 25) 1259# define FMT_25FRC_SEL(x) ((x) << 26) 1260# define FMT_50FRC_SEL(x) ((x) << 28) 1261# define FMT_75FRC_SEL(x) ((x) << 30) 1262#define FMT_CLAMP_CONTROL 0x672c 1263# define FMT_CLAMP_DATA_EN (1 << 0) 1264# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) 1265# define FMT_CLAMP_6BPC 0 1266# define FMT_CLAMP_8BPC 1 1267# define FMT_CLAMP_10BPC 2 1268 1269/* Power management */ 1270#define CG_SPLL_FUNC_CNTL 0x600 1271# define SPLL_RESET (1 << 0) 1272# define SPLL_SLEEP (1 << 1) 1273# define SPLL_REF_DIV(x) ((x) << 2) 1274# define SPLL_REF_DIV_MASK (7 << 2) 1275# define SPLL_FB_DIV(x) ((x) << 5) 1276# define SPLL_FB_DIV_MASK (0xff << 5) 1277# define SPLL_PULSEEN (1 << 13) 1278# define SPLL_PULSENUM(x) ((x) << 14) 1279# define SPLL_PULSENUM_MASK (3 << 14) 1280# define SPLL_SW_HILEN(x) ((x) << 16) 1281# define SPLL_SW_HILEN_MASK (0xf << 16) 1282# define SPLL_SW_LOLEN(x) ((x) << 20) 1283# define SPLL_SW_LOLEN_MASK (0xf << 20) 1284# define SPLL_DIVEN (1 << 24) 1285# define SPLL_BYPASS_EN (1 << 25) 1286# define SPLL_CHG_STATUS (1 << 29) 1287# define SPLL_CTLREQ (1 << 30) 1288# define SPLL_CTLACK (1 << 31) 1289 1290#define GENERAL_PWRMGT 0x618 1291# define GLOBAL_PWRMGT_EN (1 << 0) 1292# define STATIC_PM_EN (1 << 1) 1293# define MOBILE_SU (1 << 2) 1294# define THERMAL_PROTECTION_DIS (1 << 3) 1295# define THERMAL_PROTECTION_TYPE (1 << 4) 1296# define ENABLE_GEN2PCIE (1 << 5) 1297# define SW_GPIO_INDEX(x) ((x) << 6) 1298# define SW_GPIO_INDEX_MASK (3 << 6) 1299# define LOW_VOLT_D2_ACPI (1 << 8) 1300# define LOW_VOLT_D3_ACPI (1 << 9) 1301# define VOLT_PWRMGT_EN (1 << 10) 1302#define CG_TPC 0x61c 1303# define TPCC(x) ((x) << 0) 1304# define TPCC_MASK (0x7fffff << 0) 1305# define TPU(x) ((x) << 23) 1306# define TPU_MASK (0x1f << 23) 1307#define SCLK_PWRMGT_CNTL 0x620 1308# define SCLK_PWRMGT_OFF (1 << 0) 1309# define SCLK_TURNOFF (1 << 1) 1310# define SPLL_TURNOFF (1 << 2) 1311# define SU_SCLK_USE_BCLK (1 << 3) 1312# define DYNAMIC_GFX_ISLAND_PWR_DOWN (1 << 4) 1313# define DYNAMIC_GFX_ISLAND_PWR_LP (1 << 5) 1314# define CLK_TURN_ON_STAGGER (1 << 6) 1315# define CLK_TURN_OFF_STAGGER (1 << 7) 1316# define FIR_FORCE_TREND_SEL (1 << 8) 1317# define FIR_TREND_MODE (1 << 9) 1318# define DYN_GFX_CLK_OFF_EN (1 << 10) 1319# define VDDC3D_TURNOFF_D1 (1 << 11) 1320# define VDDC3D_TURNOFF_D2 (1 << 12) 1321# define VDDC3D_TURNOFF_D3 (1 << 13) 1322# define SPLL_TURNOFF_D2 (1 << 14) 1323# define SCLK_LOW_D1 (1 << 15) 1324# define DYN_GFX_CLK_OFF_MC_EN (1 << 16) 1325#define MCLK_PWRMGT_CNTL 0x624 1326# define MPLL_PWRMGT_OFF (1 << 0) 1327# define YCLK_TURNOFF (1 << 1) 1328# define MPLL_TURNOFF (1 << 2) 1329# define SU_MCLK_USE_BCLK (1 << 3) 1330# define DLL_READY (1 << 4) 1331# define MC_BUSY (1 << 5) 1332# define MC_INT_CNTL (1 << 7) 1333# define MRDCKA_SLEEP (1 << 8) 1334# define MRDCKB_SLEEP (1 << 9) 1335# define MRDCKC_SLEEP (1 << 10) 1336# define MRDCKD_SLEEP (1 << 11) 1337# define MRDCKE_SLEEP (1 << 12) 1338# define MRDCKF_SLEEP (1 << 13) 1339# define MRDCKG_SLEEP (1 << 14) 1340# define MRDCKH_SLEEP (1 << 15) 1341# define MRDCKA_RESET (1 << 16) 1342# define MRDCKB_RESET (1 << 17) 1343# define MRDCKC_RESET (1 << 18) 1344# define MRDCKD_RESET (1 << 19) 1345# define MRDCKE_RESET (1 << 20) 1346# define MRDCKF_RESET (1 << 21) 1347# define MRDCKG_RESET (1 << 22) 1348# define MRDCKH_RESET (1 << 23) 1349# define DLL_READY_READ (1 << 24) 1350# define USE_DISPLAY_GAP (1 << 25) 1351# define USE_DISPLAY_URGENT_NORMAL (1 << 26) 1352# define USE_DISPLAY_GAP_CTXSW (1 << 27) 1353# define MPLL_TURNOFF_D2 (1 << 28) 1354# define USE_DISPLAY_URGENT_CTXSW (1 << 29) 1355 1356#define MPLL_TIME 0x634 1357# define MPLL_LOCK_TIME(x) ((x) << 0) 1358# define MPLL_LOCK_TIME_MASK (0xffff << 0) 1359# define MPLL_RESET_TIME(x) ((x) << 16) 1360# define MPLL_RESET_TIME_MASK (0xffff << 16) 1361 1362#define SCLK_FREQ_SETTING_STEP_0_PART1 0x648 1363# define STEP_0_SPLL_POST_DIV(x) ((x) << 0) 1364# define STEP_0_SPLL_POST_DIV_MASK (0xff << 0) 1365# define STEP_0_SPLL_FB_DIV(x) ((x) << 8) 1366# define STEP_0_SPLL_FB_DIV_MASK (0xff << 8) 1367# define STEP_0_SPLL_REF_DIV(x) ((x) << 16) 1368# define STEP_0_SPLL_REF_DIV_MASK (7 << 16) 1369# define STEP_0_SPLL_STEP_TIME(x) ((x) << 19) 1370# define STEP_0_SPLL_STEP_TIME_MASK (0x1fff << 19) 1371#define SCLK_FREQ_SETTING_STEP_0_PART2 0x64c 1372# define STEP_0_PULSE_HIGH_CNT(x) ((x) << 0) 1373# define STEP_0_PULSE_HIGH_CNT_MASK (0x1ff << 0) 1374# define STEP_0_POST_DIV_EN (1 << 9) 1375# define STEP_0_SPLL_STEP_ENABLE (1 << 30) 1376# define STEP_0_SPLL_ENTRY_VALID (1 << 31) 1377 1378#define VID_RT 0x6f8 1379# define VID_CRT(x) ((x) << 0) 1380# define VID_CRT_MASK (0x1fff << 0) 1381# define VID_CRTU(x) ((x) << 13) 1382# define VID_CRTU_MASK (7 << 13) 1383# define SSTU(x) ((x) << 16) 1384# define SSTU_MASK (7 << 16) 1385#define CTXSW_PROFILE_INDEX 0x6fc 1386# define CTXSW_FREQ_VIDS_CFG_INDEX(x) ((x) << 0) 1387# define CTXSW_FREQ_VIDS_CFG_INDEX_MASK (3 << 0) 1388# define CTXSW_FREQ_VIDS_CFG_INDEX_SHIFT 0 1389# define CTXSW_FREQ_MCLK_CFG_INDEX(x) ((x) << 2) 1390# define CTXSW_FREQ_MCLK_CFG_INDEX_MASK (3 << 2) 1391# define CTXSW_FREQ_MCLK_CFG_INDEX_SHIFT 2 1392# define CTXSW_FREQ_SCLK_CFG_INDEX(x) ((x) << 4) 1393# define CTXSW_FREQ_SCLK_CFG_INDEX_MASK (0x1f << 4) 1394# define CTXSW_FREQ_SCLK_CFG_INDEX_SHIFT 4 1395# define CTXSW_FREQ_STATE_SPLL_RESET_EN (1 << 9) 1396# define CTXSW_FREQ_STATE_ENABLE (1 << 10) 1397# define CTXSW_FREQ_DISPLAY_WATERMARK (1 << 11) 1398# define CTXSW_FREQ_GEN2PCIE_VOLT (1 << 12) 1399 1400#define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c 1401# define TARGET_PROFILE_INDEX_MASK (3 << 0) 1402# define TARGET_PROFILE_INDEX_SHIFT 0 1403# define CURRENT_PROFILE_INDEX_MASK (3 << 2) 1404# define CURRENT_PROFILE_INDEX_SHIFT 2 1405# define DYN_PWR_ENTER_INDEX(x) ((x) << 4) 1406# define DYN_PWR_ENTER_INDEX_MASK (3 << 4) 1407# define DYN_PWR_ENTER_INDEX_SHIFT 4 1408# define CURR_MCLK_INDEX_MASK (3 << 6) 1409# define CURR_MCLK_INDEX_SHIFT 6 1410# define CURR_SCLK_INDEX_MASK (0x1f << 8) 1411# define CURR_SCLK_INDEX_SHIFT 8 1412# define CURR_VID_INDEX_MASK (3 << 13) 1413# define CURR_VID_INDEX_SHIFT 13 1414 1415#define LOWER_GPIO_ENABLE 0x710 1416#define UPPER_GPIO_ENABLE 0x714 1417#define CTXSW_VID_LOWER_GPIO_CNTL 0x718 1418 1419#define VID_UPPER_GPIO_CNTL 0x740 1420#define CG_CTX_CGTT3D_R 0x744 1421# define PHC(x) ((x) << 0) 1422# define PHC_MASK (0x1ff << 0) 1423# define SDC(x) ((x) << 9) 1424# define SDC_MASK (0x3fff << 9) 1425#define CG_VDDC3D_OOR 0x748 1426# define SU(x) ((x) << 23) 1427# define SU_MASK (0xf << 23) 1428#define CG_FTV 0x74c 1429#define CG_FFCT_0 0x750 1430# define UTC_0(x) ((x) << 0) 1431# define UTC_0_MASK (0x3ff << 0) 1432# define DTC_0(x) ((x) << 10) 1433# define DTC_0_MASK (0x3ff << 10) 1434 1435#define CG_BSP 0x78c 1436# define BSP(x) ((x) << 0) 1437# define BSP_MASK (0xffff << 0) 1438# define BSU(x) ((x) << 16) 1439# define BSU_MASK (0xf << 16) 1440#define CG_RT 0x790 1441# define FLS(x) ((x) << 0) 1442# define FLS_MASK (0xffff << 0) 1443# define FMS(x) ((x) << 16) 1444# define FMS_MASK (0xffff << 16) 1445#define CG_LT 0x794 1446# define FHS(x) ((x) << 0) 1447# define FHS_MASK (0xffff << 0) 1448#define CG_GIT 0x798 1449# define CG_GICST(x) ((x) << 0) 1450# define CG_GICST_MASK (0xffff << 0) 1451# define CG_GIPOT(x) ((x) << 16) 1452# define CG_GIPOT_MASK (0xffff << 16) 1453 1454#define CG_SSP 0x7a8 1455# define CG_SST(x) ((x) << 0) 1456# define CG_SST_MASK (0xffff << 0) 1457# define CG_SSTU(x) ((x) << 16) 1458# define CG_SSTU_MASK (0xf << 16) 1459 1460#define CG_RLC_REQ_AND_RSP 0x7c4 1461# define RLC_CG_REQ_TYPE_MASK 0xf 1462# define RLC_CG_REQ_TYPE_SHIFT 0 1463# define CG_RLC_RSP_TYPE_MASK 0xf0 1464# define CG_RLC_RSP_TYPE_SHIFT 4 1465 1466#define CG_FC_T 0x7cc 1467# define FC_T(x) ((x) << 0) 1468# define FC_T_MASK (0xffff << 0) 1469# define FC_TU(x) ((x) << 16) 1470# define FC_TU_MASK (0x1f << 16) 1471 1472#define GPIOPAD_MASK 0x1798 1473#define GPIOPAD_A 0x179c 1474#define GPIOPAD_EN 0x17a0 1475 1476#define GRBM_PWR_CNTL 0x800c 1477# define REQ_TYPE_MASK 0xf 1478# define REQ_TYPE_SHIFT 0 1479# define RSP_TYPE_MASK 0xf0 1480# define RSP_TYPE_SHIFT 4 1481 1482/* 1483 * UVD 1484 */ 1485#define UVD_SEMA_ADDR_LOW 0xef00 1486#define UVD_SEMA_ADDR_HIGH 0xef04 1487#define UVD_SEMA_CMD 0xef08 1488 1489#define UVD_GPCOM_VCPU_CMD 0xef0c 1490#define UVD_GPCOM_VCPU_DATA0 0xef10 1491#define UVD_GPCOM_VCPU_DATA1 0xef14 1492#define UVD_ENGINE_CNTL 0xef18 1493#define UVD_NO_OP 0xeffc 1494 1495#define UVD_SEMA_CNTL 0xf400 1496#define UVD_RB_ARB_CTRL 0xf480 1497 1498#define UVD_LMI_EXT40_ADDR 0xf498 1499#define UVD_CGC_GATE 0xf4a8 1500#define UVD_LMI_CTRL2 0xf4f4 1501#define UVD_MASTINT_EN 0xf500 1502#define UVD_FW_START 0xf51C 1503#define UVD_LMI_ADDR_EXT 0xf594 1504#define UVD_LMI_CTRL 0xf598 1505#define UVD_LMI_SWAP_CNTL 0xf5b4 1506#define UVD_MP_SWAP_CNTL 0xf5bC 1507#define UVD_MPC_CNTL 0xf5dC 1508#define UVD_MPC_SET_MUXA0 0xf5e4 1509#define UVD_MPC_SET_MUXA1 0xf5e8 1510#define UVD_MPC_SET_MUXB0 0xf5eC 1511#define UVD_MPC_SET_MUXB1 0xf5f0 1512#define UVD_MPC_SET_MUX 0xf5f4 1513#define UVD_MPC_SET_ALU 0xf5f8 1514 1515#define UVD_VCPU_CACHE_OFFSET0 0xf608 1516#define UVD_VCPU_CACHE_SIZE0 0xf60c 1517#define UVD_VCPU_CACHE_OFFSET1 0xf610 1518#define UVD_VCPU_CACHE_SIZE1 0xf614 1519#define UVD_VCPU_CACHE_OFFSET2 0xf618 1520#define UVD_VCPU_CACHE_SIZE2 0xf61c 1521 1522#define UVD_VCPU_CNTL 0xf660 1523#define UVD_SOFT_RESET 0xf680 1524#define RBC_SOFT_RESET (1<<0) 1525#define LBSI_SOFT_RESET (1<<1) 1526#define LMI_SOFT_RESET (1<<2) 1527#define VCPU_SOFT_RESET (1<<3) 1528#define CSM_SOFT_RESET (1<<5) 1529#define CXW_SOFT_RESET (1<<6) 1530#define TAP_SOFT_RESET (1<<7) 1531#define LMI_UMC_SOFT_RESET (1<<13) 1532#define UVD_RBC_IB_BASE 0xf684 1533#define UVD_RBC_IB_SIZE 0xf688 1534#define UVD_RBC_RB_BASE 0xf68c 1535#define UVD_RBC_RB_RPTR 0xf690 1536#define UVD_RBC_RB_WPTR 0xf694 1537#define UVD_RBC_RB_WPTR_CNTL 0xf698 1538 1539#define UVD_STATUS 0xf6bc 1540 1541#define UVD_SEMA_TIMEOUT_STATUS 0xf6c0 1542#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0xf6c4 1543#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0xf6c8 1544#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0xf6cc 1545 1546#define UVD_RBC_RB_CNTL 0xf6a4 1547#define UVD_RBC_RB_RPTR_ADDR 0xf6a8 1548 1549#define UVD_CONTEXT_ID 0xf6f4 1550 1551/* rs780 only */ 1552#define GFX_MACRO_BYPASS_CNTL 0x30c0 1553#define SPLL_BYPASS_CNTL (1 << 0) 1554#define UPLL_BYPASS_CNTL (1 << 1) 1555 1556#define CG_UPLL_FUNC_CNTL 0x7e0 1557# define UPLL_RESET_MASK 0x00000001 1558# define UPLL_SLEEP_MASK 0x00000002 1559# define UPLL_BYPASS_EN_MASK 0x00000004 1560# define UPLL_CTLREQ_MASK 0x00000008 1561# define UPLL_FB_DIV(x) ((x) << 4) 1562# define UPLL_FB_DIV_MASK 0x0000FFF0 1563# define UPLL_REF_DIV(x) ((x) << 16) 1564# define UPLL_REF_DIV_MASK 0x003F0000 1565# define UPLL_REFCLK_SRC_SEL_MASK 0x20000000 1566# define UPLL_CTLACK_MASK 0x40000000 1567# define UPLL_CTLACK2_MASK 0x80000000 1568#define CG_UPLL_FUNC_CNTL_2 0x7e4 1569# define UPLL_SW_HILEN(x) ((x) << 0) 1570# define UPLL_SW_LOLEN(x) ((x) << 4) 1571# define UPLL_SW_HILEN2(x) ((x) << 8) 1572# define UPLL_SW_LOLEN2(x) ((x) << 12) 1573# define UPLL_DIVEN_MASK 0x00010000 1574# define UPLL_DIVEN2_MASK 0x00020000 1575# define UPLL_SW_MASK 0x0003FFFF 1576# define VCLK_SRC_SEL(x) ((x) << 20) 1577# define VCLK_SRC_SEL_MASK 0x01F00000 1578# define DCLK_SRC_SEL(x) ((x) << 25) 1579# define DCLK_SRC_SEL_MASK 0x3E000000 1580 1581/* 1582 * PM4 1583 */ 1584#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1585 (((reg) >> 2) & 0xFFFF) | \ 1586 ((n) & 0x3FFF) << 16) 1587#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1588 (((op) & 0xFF) << 8) | \ 1589 ((n) & 0x3FFF) << 16) 1590 1591/* Packet 3 types */ 1592#define PACKET3_NOP 0x10 1593#define PACKET3_INDIRECT_BUFFER_END 0x17 1594#define PACKET3_SET_PREDICATION 0x20 1595#define PACKET3_REG_RMW 0x21 1596#define PACKET3_COND_EXEC 0x22 1597#define PACKET3_PRED_EXEC 0x23 1598#define PACKET3_START_3D_CMDBUF 0x24 1599#define PACKET3_DRAW_INDEX_2 0x27 1600#define PACKET3_CONTEXT_CONTROL 0x28 1601#define PACKET3_DRAW_INDEX_IMMD_BE 0x29 1602#define PACKET3_INDEX_TYPE 0x2A 1603#define PACKET3_DRAW_INDEX 0x2B 1604#define PACKET3_DRAW_INDEX_AUTO 0x2D 1605#define PACKET3_DRAW_INDEX_IMMD 0x2E 1606#define PACKET3_NUM_INSTANCES 0x2F 1607#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1608#define PACKET3_INDIRECT_BUFFER_MP 0x38 1609#define PACKET3_MEM_SEMAPHORE 0x39 1610# define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 1611# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1612# define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1613#define PACKET3_MPEG_INDEX 0x3A 1614#define PACKET3_COPY_DW 0x3B 1615#define PACKET3_WAIT_REG_MEM 0x3C 1616#define PACKET3_MEM_WRITE 0x3D 1617#define PACKET3_INDIRECT_BUFFER 0x32 1618#define PACKET3_CP_DMA 0x41 1619/* 1. header 1620 * 2. SRC_ADDR_LO [31:0] 1621 * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0] 1622 * 4. DST_ADDR_LO [31:0] 1623 * 5. DST_ADDR_HI [7:0] 1624 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1625 */ 1626# define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1627/* COMMAND */ 1628# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1629 /* 0 - none 1630 * 1 - 8 in 16 1631 * 2 - 8 in 32 1632 * 3 - 8 in 64 1633 */ 1634# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1635 /* 0 - none 1636 * 1 - 8 in 16 1637 * 2 - 8 in 32 1638 * 3 - 8 in 64 1639 */ 1640# define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1641 /* 0 - memory 1642 * 1 - register 1643 */ 1644# define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1645 /* 0 - memory 1646 * 1 - register 1647 */ 1648# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1649# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1650#define PACKET3_PFP_SYNC_ME 0x42 /* r7xx+ only */ 1651#define PACKET3_SURFACE_SYNC 0x43 1652# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1653# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ 1654# define PACKET3_TC_ACTION_ENA (1 << 23) 1655# define PACKET3_VC_ACTION_ENA (1 << 24) 1656# define PACKET3_CB_ACTION_ENA (1 << 25) 1657# define PACKET3_DB_ACTION_ENA (1 << 26) 1658# define PACKET3_SH_ACTION_ENA (1 << 27) 1659# define PACKET3_SMX_ACTION_ENA (1 << 28) 1660#define PACKET3_ME_INITIALIZE 0x44 1661#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1662#define PACKET3_COND_WRITE 0x45 1663#define PACKET3_EVENT_WRITE 0x46 1664#define EVENT_TYPE(x) ((x) << 0) 1665#define EVENT_INDEX(x) ((x) << 8) 1666 /* 0 - any non-TS event 1667 * 1 - ZPASS_DONE 1668 * 2 - SAMPLE_PIPELINESTAT 1669 * 3 - SAMPLE_STREAMOUTSTAT* 1670 * 4 - *S_PARTIAL_FLUSH 1671 * 5 - TS events 1672 */ 1673#define PACKET3_EVENT_WRITE_EOP 0x47 1674#define DATA_SEL(x) ((x) << 29) 1675 /* 0 - discard 1676 * 1 - send low 32bit data 1677 * 2 - send 64bit data 1678 * 3 - send 64bit counter value 1679 */ 1680#define INT_SEL(x) ((x) << 24) 1681 /* 0 - none 1682 * 1 - interrupt only (DATA_SEL = 0) 1683 * 2 - interrupt when data write is confirmed 1684 */ 1685#define PACKET3_ONE_REG_WRITE 0x57 1686#define PACKET3_SET_CONFIG_REG 0x68 1687#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 1688#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1689#define PACKET3_SET_CONTEXT_REG 0x69 1690#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 1691#define PACKET3_SET_CONTEXT_REG_END 0x00029000 1692#define PACKET3_SET_ALU_CONST 0x6A 1693#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 1694#define PACKET3_SET_ALU_CONST_END 0x00032000 1695#define PACKET3_SET_BOOL_CONST 0x6B 1696#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 1697#define PACKET3_SET_BOOL_CONST_END 0x00040000 1698#define PACKET3_SET_LOOP_CONST 0x6C 1699#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 1700#define PACKET3_SET_LOOP_CONST_END 0x0003e380 1701#define PACKET3_SET_RESOURCE 0x6D 1702#define PACKET3_SET_RESOURCE_OFFSET 0x00038000 1703#define PACKET3_SET_RESOURCE_END 0x0003c000 1704#define PACKET3_SET_SAMPLER 0x6E 1705#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 1706#define PACKET3_SET_SAMPLER_END 0x0003cff0 1707#define PACKET3_SET_CTL_CONST 0x6F 1708#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 1709#define PACKET3_SET_CTL_CONST_END 0x0003e200 1710#define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ 1711#define PACKET3_SURFACE_BASE_UPDATE 0x73 1712 1713#define R_000011_K8_FB_LOCATION 0x11 1714#define R_000012_MC_MISC_UMA_CNTL 0x12 1715#define G_000012_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) 1716#define R_0028F8_MC_INDEX 0x28F8 1717#define S_0028F8_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) 1718#define C_0028F8_MC_IND_ADDR 0xFFFFFE00 1719#define S_0028F8_MC_IND_WR_EN(x) (((x) & 0x1) << 9) 1720#define R_0028FC_MC_DATA 0x28FC 1721 1722#define R_008020_GRBM_SOFT_RESET 0x8020 1723#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 1724#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 1725#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 1726#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 1727#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 1728#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 1729#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 1730#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 1731#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 1732#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 1733#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 1734#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 1735#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 1736#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 1737#define R_008010_GRBM_STATUS 0x8010 1738#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 1739#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 1740#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 1741#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 1742#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 1743#define S_008010_VC_BUSY(x) (((x) & 1) << 11) 1744#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 1745#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 1746#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 1747#define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 1748#define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 1749#define S_008010_TC_BUSY(x) (((x) & 1) << 19) 1750#define S_008010_SX_BUSY(x) (((x) & 1) << 20) 1751#define S_008010_SH_BUSY(x) (((x) & 1) << 21) 1752#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 1753#define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 1754#define S_008010_SC_BUSY(x) (((x) & 1) << 24) 1755#define S_008010_PA_BUSY(x) (((x) & 1) << 25) 1756#define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 1757#define S_008010_CR_BUSY(x) (((x) & 1) << 27) 1758#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 1759#define S_008010_CP_BUSY(x) (((x) & 1) << 29) 1760#define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 1761#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 1762#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 1763#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 1764#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 1765#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 1766#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 1767#define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 1768#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 1769#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 1770#define G_008010_TA_BUSY(x) (((x) >> 14) & 1) 1771#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 1772#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 1773#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 1774#define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 1775#define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 1776#define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 1777#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 1778#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 1779#define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 1780#define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 1781#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 1782#define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 1783#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 1784#define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 1785#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 1786#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 1787#define R_008014_GRBM_STATUS2 0x8014 1788#define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 1789#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 1790#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 1791#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 1792#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 1793#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 1794#define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 1795#define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 1796#define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 1797#define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 1798#define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 1799#define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 1800#define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 1801#define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 1802#define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 1803#define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 1804#define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 1805#define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 1806#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 1807#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 1808#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 1809#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 1810#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 1811#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 1812#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 1813#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 1814#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 1815#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 1816#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 1817#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 1818#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 1819#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 1820#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 1821#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 1822#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 1823#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 1824#define R_000E50_SRBM_STATUS 0x0E50 1825#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 1826#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 1827#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 1828#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 1829#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 1830#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 1831#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 1832#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 1833#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 1834#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 1835#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 1836#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 1837#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 1838#define G_000E50_IH_BUSY(x) (((x) >> 17) & 1) 1839#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 1840#define R_000E60_SRBM_SOFT_RESET 0x0E60 1841#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 1842#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 1843#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 1844#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 1845#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 1846#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 1847#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 1848#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 1849#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 1850#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 1851#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 1852#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 1853#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 1854#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 1855 1856#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 1857 1858#define R_028C04_PA_SC_AA_CONFIG 0x028C04 1859#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) 1860#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) 1861#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC 1862#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 1863#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 1864#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 1865#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) 1866#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) 1867#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF 1868#define R_0280E0_CB_COLOR0_FRAG 0x0280E0 1869#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1870#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1871#define C_0280E0_BASE_256B 0x00000000 1872#define R_0280E4_CB_COLOR1_FRAG 0x0280E4 1873#define R_0280E8_CB_COLOR2_FRAG 0x0280E8 1874#define R_0280EC_CB_COLOR3_FRAG 0x0280EC 1875#define R_0280F0_CB_COLOR4_FRAG 0x0280F0 1876#define R_0280F4_CB_COLOR5_FRAG 0x0280F4 1877#define R_0280F8_CB_COLOR6_FRAG 0x0280F8 1878#define R_0280FC_CB_COLOR7_FRAG 0x0280FC 1879#define R_0280C0_CB_COLOR0_TILE 0x0280C0 1880#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1881#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1882#define C_0280C0_BASE_256B 0x00000000 1883#define R_0280C4_CB_COLOR1_TILE 0x0280C4 1884#define R_0280C8_CB_COLOR2_TILE 0x0280C8 1885#define R_0280CC_CB_COLOR3_TILE 0x0280CC 1886#define R_0280D0_CB_COLOR4_TILE 0x0280D0 1887#define R_0280D4_CB_COLOR5_TILE 0x0280D4 1888#define R_0280D8_CB_COLOR6_TILE 0x0280D8 1889#define R_0280DC_CB_COLOR7_TILE 0x0280DC 1890#define R_0280A0_CB_COLOR0_INFO 0x0280A0 1891#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) 1892#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) 1893#define C_0280A0_ENDIAN 0xFFFFFFFC 1894#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) 1895#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) 1896#define C_0280A0_FORMAT 0xFFFFFF03 1897#define V_0280A0_COLOR_INVALID 0x00000000 1898#define V_0280A0_COLOR_8 0x00000001 1899#define V_0280A0_COLOR_4_4 0x00000002 1900#define V_0280A0_COLOR_3_3_2 0x00000003 1901#define V_0280A0_COLOR_16 0x00000005 1902#define V_0280A0_COLOR_16_FLOAT 0x00000006 1903#define V_0280A0_COLOR_8_8 0x00000007 1904#define V_0280A0_COLOR_5_6_5 0x00000008 1905#define V_0280A0_COLOR_6_5_5 0x00000009 1906#define V_0280A0_COLOR_1_5_5_5 0x0000000A 1907#define V_0280A0_COLOR_4_4_4_4 0x0000000B 1908#define V_0280A0_COLOR_5_5_5_1 0x0000000C 1909#define V_0280A0_COLOR_32 0x0000000D 1910#define V_0280A0_COLOR_32_FLOAT 0x0000000E 1911#define V_0280A0_COLOR_16_16 0x0000000F 1912#define V_0280A0_COLOR_16_16_FLOAT 0x00000010 1913#define V_0280A0_COLOR_8_24 0x00000011 1914#define V_0280A0_COLOR_8_24_FLOAT 0x00000012 1915#define V_0280A0_COLOR_24_8 0x00000013 1916#define V_0280A0_COLOR_24_8_FLOAT 0x00000014 1917#define V_0280A0_COLOR_10_11_11 0x00000015 1918#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 1919#define V_0280A0_COLOR_11_11_10 0x00000017 1920#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 1921#define V_0280A0_COLOR_2_10_10_10 0x00000019 1922#define V_0280A0_COLOR_8_8_8_8 0x0000001A 1923#define V_0280A0_COLOR_10_10_10_2 0x0000001B 1924#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C 1925#define V_0280A0_COLOR_32_32 0x0000001D 1926#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E 1927#define V_0280A0_COLOR_16_16_16_16 0x0000001F 1928#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 1929#define V_0280A0_COLOR_32_32_32_32 0x00000022 1930#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 1931#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) 1932#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1933#define C_0280A0_ARRAY_MODE 0xFFFFF0FF 1934#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 1935#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 1936#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 1937#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 1938#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1939#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1940#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF 1941#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) 1942#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) 1943#define C_0280A0_READ_SIZE 0xFFFF7FFF 1944#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) 1945#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) 1946#define C_0280A0_COMP_SWAP 0xFFFCFFFF 1947#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1948#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1949#define C_0280A0_TILE_MODE 0xFFF3FFFF 1950#define V_0280A0_TILE_DISABLE 0 1951#define V_0280A0_CLEAR_ENABLE 1 1952#define V_0280A0_FRAG_ENABLE 2 1953#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1954#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1955#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1956#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) 1957#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) 1958#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF 1959#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) 1960#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) 1961#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF 1962#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) 1963#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) 1964#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF 1965#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) 1966#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) 1967#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF 1968#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) 1969#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) 1970#define C_0280A0_ROUND_MODE 0xFDFFFFFF 1971#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) 1972#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1973#define C_0280A0_TILE_COMPACT 0xFBFFFFFF 1974#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) 1975#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) 1976#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF 1977#define R_0280A4_CB_COLOR1_INFO 0x0280A4 1978#define R_0280A8_CB_COLOR2_INFO 0x0280A8 1979#define R_0280AC_CB_COLOR3_INFO 0x0280AC 1980#define R_0280B0_CB_COLOR4_INFO 0x0280B0 1981#define R_0280B4_CB_COLOR5_INFO 0x0280B4 1982#define R_0280B8_CB_COLOR6_INFO 0x0280B8 1983#define R_0280BC_CB_COLOR7_INFO 0x0280BC 1984#define R_028060_CB_COLOR0_SIZE 0x028060 1985#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1986#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1987#define C_028060_PITCH_TILE_MAX 0xFFFFFC00 1988#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1989#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1990#define C_028060_SLICE_TILE_MAX 0xC00003FF 1991#define R_028064_CB_COLOR1_SIZE 0x028064 1992#define R_028068_CB_COLOR2_SIZE 0x028068 1993#define R_02806C_CB_COLOR3_SIZE 0x02806C 1994#define R_028070_CB_COLOR4_SIZE 0x028070 1995#define R_028074_CB_COLOR5_SIZE 0x028074 1996#define R_028078_CB_COLOR6_SIZE 0x028078 1997#define R_02807C_CB_COLOR7_SIZE 0x02807C 1998#define R_028238_CB_TARGET_MASK 0x028238 1999#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) 2000#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) 2001#define C_028238_TARGET0_ENABLE 0xFFFFFFF0 2002#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) 2003#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) 2004#define C_028238_TARGET1_ENABLE 0xFFFFFF0F 2005#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) 2006#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) 2007#define C_028238_TARGET2_ENABLE 0xFFFFF0FF 2008#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) 2009#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) 2010#define C_028238_TARGET3_ENABLE 0xFFFF0FFF 2011#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) 2012#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) 2013#define C_028238_TARGET4_ENABLE 0xFFF0FFFF 2014#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) 2015#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) 2016#define C_028238_TARGET5_ENABLE 0xFF0FFFFF 2017#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) 2018#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) 2019#define C_028238_TARGET6_ENABLE 0xF0FFFFFF 2020#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) 2021#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) 2022#define C_028238_TARGET7_ENABLE 0x0FFFFFFF 2023#define R_02823C_CB_SHADER_MASK 0x02823C 2024#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) 2025#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) 2026#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 2027#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) 2028#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) 2029#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 2030#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) 2031#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) 2032#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 2033#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) 2034#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) 2035#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 2036#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) 2037#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) 2038#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 2039#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) 2040#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) 2041#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 2042#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) 2043#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) 2044#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 2045#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) 2046#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) 2047#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 2048#define R_028AB0_VGT_STRMOUT_EN 0x028AB0 2049#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) 2050#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) 2051#define C_028AB0_STREAMOUT 0xFFFFFFFE 2052#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 2053#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) 2054#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) 2055#define C_028B20_BUFFER_0_EN 0xFFFFFFFE 2056#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) 2057#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) 2058#define C_028B20_BUFFER_1_EN 0xFFFFFFFD 2059#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) 2060#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) 2061#define C_028B20_BUFFER_2_EN 0xFFFFFFFB 2062#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) 2063#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) 2064#define C_028B20_BUFFER_3_EN 0xFFFFFFF7 2065#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2066#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2067#define C_028B20_SIZE 0x00000000 2068#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 2069#define S_038000_DIM(x) (((x) & 0x7) << 0) 2070#define G_038000_DIM(x) (((x) >> 0) & 0x7) 2071#define C_038000_DIM 0xFFFFFFF8 2072#define V_038000_SQ_TEX_DIM_1D 0x00000000 2073#define V_038000_SQ_TEX_DIM_2D 0x00000001 2074#define V_038000_SQ_TEX_DIM_3D 0x00000002 2075#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 2076#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 2077#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 2078#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 2079#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 2080#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 2081#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 2082#define C_038000_TILE_MODE 0xFFFFFF87 2083#define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 2084#define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 2085#define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 2086#define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 2087#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 2088#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 2089#define C_038000_TILE_TYPE 0xFFFFFF7F 2090#define S_038000_PITCH(x) (((x) & 0x7FF) << 8) 2091#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) 2092#define C_038000_PITCH 0xFFF800FF 2093#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) 2094#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) 2095#define C_038000_TEX_WIDTH 0x0007FFFF 2096#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 2097#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) 2098#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) 2099#define C_038004_TEX_HEIGHT 0xFFFFE000 2100#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) 2101#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) 2102#define C_038004_TEX_DEPTH 0xFC001FFF 2103#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) 2104#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) 2105#define C_038004_DATA_FORMAT 0x03FFFFFF 2106#define V_038004_COLOR_INVALID 0x00000000 2107#define V_038004_COLOR_8 0x00000001 2108#define V_038004_COLOR_4_4 0x00000002 2109#define V_038004_COLOR_3_3_2 0x00000003 2110#define V_038004_COLOR_16 0x00000005 2111#define V_038004_COLOR_16_FLOAT 0x00000006 2112#define V_038004_COLOR_8_8 0x00000007 2113#define V_038004_COLOR_5_6_5 0x00000008 2114#define V_038004_COLOR_6_5_5 0x00000009 2115#define V_038004_COLOR_1_5_5_5 0x0000000A 2116#define V_038004_COLOR_4_4_4_4 0x0000000B 2117#define V_038004_COLOR_5_5_5_1 0x0000000C 2118#define V_038004_COLOR_32 0x0000000D 2119#define V_038004_COLOR_32_FLOAT 0x0000000E 2120#define V_038004_COLOR_16_16 0x0000000F 2121#define V_038004_COLOR_16_16_FLOAT 0x00000010 2122#define V_038004_COLOR_8_24 0x00000011 2123#define V_038004_COLOR_8_24_FLOAT 0x00000012 2124#define V_038004_COLOR_24_8 0x00000013 2125#define V_038004_COLOR_24_8_FLOAT 0x00000014 2126#define V_038004_COLOR_10_11_11 0x00000015 2127#define V_038004_COLOR_10_11_11_FLOAT 0x00000016 2128#define V_038004_COLOR_11_11_10 0x00000017 2129#define V_038004_COLOR_11_11_10_FLOAT 0x00000018 2130#define V_038004_COLOR_2_10_10_10 0x00000019 2131#define V_038004_COLOR_8_8_8_8 0x0000001A 2132#define V_038004_COLOR_10_10_10_2 0x0000001B 2133#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C 2134#define V_038004_COLOR_32_32 0x0000001D 2135#define V_038004_COLOR_32_32_FLOAT 0x0000001E 2136#define V_038004_COLOR_16_16_16_16 0x0000001F 2137#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 2138#define V_038004_COLOR_32_32_32_32 0x00000022 2139#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 2140#define V_038004_FMT_1 0x00000025 2141#define V_038004_FMT_GB_GR 0x00000027 2142#define V_038004_FMT_BG_RG 0x00000028 2143#define V_038004_FMT_32_AS_8 0x00000029 2144#define V_038004_FMT_32_AS_8_8 0x0000002A 2145#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B 2146#define V_038004_FMT_8_8_8 0x0000002C 2147#define V_038004_FMT_16_16_16 0x0000002D 2148#define V_038004_FMT_16_16_16_FLOAT 0x0000002E 2149#define V_038004_FMT_32_32_32 0x0000002F 2150#define V_038004_FMT_32_32_32_FLOAT 0x00000030 2151#define V_038004_FMT_BC1 0x00000031 2152#define V_038004_FMT_BC2 0x00000032 2153#define V_038004_FMT_BC3 0x00000033 2154#define V_038004_FMT_BC4 0x00000034 2155#define V_038004_FMT_BC5 0x00000035 2156#define V_038004_FMT_BC6 0x00000036 2157#define V_038004_FMT_BC7 0x00000037 2158#define V_038004_FMT_32_AS_32_32_32_32 0x00000038 2159#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 2160#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 2161#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 2162#define C_038010_FORMAT_COMP_X 0xFFFFFFFC 2163#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 2164#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 2165#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 2166#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 2167#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 2168#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF 2169#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 2170#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 2171#define C_038010_FORMAT_COMP_W 0xFFFFFF3F 2172#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 2173#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 2174#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF 2175#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 2176#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 2177#define C_038010_SRF_MODE_ALL 0xFFFFFBFF 2178#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 2179#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 2180#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF 2181#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 2182#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 2183#define C_038010_ENDIAN_SWAP 0xFFFFCFFF 2184#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) 2185#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) 2186#define C_038010_REQUEST_SIZE 0xFFFF3FFF 2187#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) 2188#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) 2189#define C_038010_DST_SEL_X 0xFFF8FFFF 2190#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) 2191#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 2192#define C_038010_DST_SEL_Y 0xFFC7FFFF 2193#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) 2194#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 2195#define C_038010_DST_SEL_Z 0xFE3FFFFF 2196#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) 2197#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) 2198#define C_038010_DST_SEL_W 0xF1FFFFFF 2199# define SQ_SEL_X 0 2200# define SQ_SEL_Y 1 2201# define SQ_SEL_Z 2 2202# define SQ_SEL_W 3 2203# define SQ_SEL_0 4 2204# define SQ_SEL_1 5 2205#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) 2206#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 2207#define C_038010_BASE_LEVEL 0x0FFFFFFF 2208#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 2209#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) 2210#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 2211#define C_038014_LAST_LEVEL 0xFFFFFFF0 2212#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 2213#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 2214#define C_038014_BASE_ARRAY 0xFFFE000F 2215#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 2216#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 2217#define C_038014_LAST_ARRAY 0xC001FFFF 2218#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 2219#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2220#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2221#define C_0288A8_ITEMSIZE 0xFFFF8000 2222#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 2223#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2224#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2225#define C_008C44_MEM_SIZE 0x00000000 2226#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 2227#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2228#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2229#define C_0288B0_ITEMSIZE 0xFFFF8000 2230#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 2231#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2232#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2233#define C_008C54_MEM_SIZE 0x00000000 2234#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 2235#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2236#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2237#define C_0288C0_ITEMSIZE 0xFFFF8000 2238#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 2239#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2240#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2241#define C_008C74_MEM_SIZE 0x00000000 2242#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 2243#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2244#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2245#define C_0288B4_ITEMSIZE 0xFFFF8000 2246#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C 2247#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2248#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2249#define C_008C5C_MEM_SIZE 0x00000000 2250#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC 2251#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2252#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2253#define C_0288AC_ITEMSIZE 0xFFFF8000 2254#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C 2255#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2256#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2257#define C_008C4C_MEM_SIZE 0x00000000 2258#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC 2259#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2260#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2261#define C_0288BC_ITEMSIZE 0xFFFF8000 2262#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C 2263#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2264#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2265#define C_008C6C_MEM_SIZE 0x00000000 2266#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 2267#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2268#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2269#define C_0288C4_ITEMSIZE 0xFFFF8000 2270#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C 2271#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2272#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2273#define C_008C7C_MEM_SIZE 0x00000000 2274#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 2275#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2276#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2277#define C_0288B8_ITEMSIZE 0xFFFF8000 2278#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 2279#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2280#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2281#define C_008C64_MEM_SIZE 0x00000000 2282#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 2283#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2284#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2285#define C_0288C8_ITEMSIZE 0xFFFF8000 2286#define R_028010_DB_DEPTH_INFO 0x028010 2287#define S_028010_FORMAT(x) (((x) & 0x7) << 0) 2288#define G_028010_FORMAT(x) (((x) >> 0) & 0x7) 2289#define C_028010_FORMAT 0xFFFFFFF8 2290#define V_028010_DEPTH_INVALID 0x00000000 2291#define V_028010_DEPTH_16 0x00000001 2292#define V_028010_DEPTH_X8_24 0x00000002 2293#define V_028010_DEPTH_8_24 0x00000003 2294#define V_028010_DEPTH_X8_24_FLOAT 0x00000004 2295#define V_028010_DEPTH_8_24_FLOAT 0x00000005 2296#define V_028010_DEPTH_32_FLOAT 0x00000006 2297#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 2298#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) 2299#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) 2300#define C_028010_READ_SIZE 0xFFFFFFF7 2301#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 2302#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 2303#define C_028010_ARRAY_MODE 0xFFF87FFF 2304#define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 2305#define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 2306#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 2307#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 2308#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 2309#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) 2310#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) 2311#define C_028010_TILE_COMPACT 0xFBFFFFFF 2312#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 2313#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 2314#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF 2315#define R_028000_DB_DEPTH_SIZE 0x028000 2316#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 2317#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 2318#define C_028000_PITCH_TILE_MAX 0xFFFFFC00 2319#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 2320#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 2321#define C_028000_SLICE_TILE_MAX 0xC00003FF 2322#define R_028004_DB_DEPTH_VIEW 0x028004 2323#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) 2324#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) 2325#define C_028004_SLICE_START 0xFFFFF800 2326#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) 2327#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 2328#define C_028004_SLICE_MAX 0xFF001FFF 2329#define R_028800_DB_DEPTH_CONTROL 0x028800 2330#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 2331#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 2332#define C_028800_STENCIL_ENABLE 0xFFFFFFFE 2333#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 2334#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 2335#define C_028800_Z_ENABLE 0xFFFFFFFD 2336#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 2337#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 2338#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 2339#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 2340#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 2341#define C_028800_ZFUNC 0xFFFFFF8F 2342#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 2343#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 2344#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 2345#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 2346#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 2347#define C_028800_STENCILFUNC 0xFFFFF8FF 2348#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 2349#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 2350#define C_028800_STENCILFAIL 0xFFFFC7FF 2351#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 2352#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 2353#define C_028800_STENCILZPASS 0xFFFE3FFF 2354#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 2355#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 2356#define C_028800_STENCILZFAIL 0xFFF1FFFF 2357#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 2358#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 2359#define C_028800_STENCILFUNC_BF 0xFF8FFFFF 2360#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 2361#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 2362#define C_028800_STENCILFAIL_BF 0xFC7FFFFF 2363#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 2364#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 2365#define C_028800_STENCILZPASS_BF 0xE3FFFFFF 2366#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 2367#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 2368#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 2369 2370#endif 2371