1/* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25#ifndef __DC_OPP_DCN10_H__ 26#define __DC_OPP_DCN10_H__ 27 28#include "opp.h" 29 30#define TO_DCN10_OPP(opp)\ 31 container_of(opp, struct dcn10_opp, base) 32 33#define OPP_SF(reg_name, field_name, post_fix)\ 34 .field_name = reg_name ## __ ## field_name ## post_fix 35 36#define OPP_REG_LIST_DCN(id) \ 37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 38 SRI(FMT_CONTROL, FMT, id), \ 39 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 40 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 41 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 42 SRI(FMT_CLAMP_CNTL, FMT, id), \ 43 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 44 SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \ 45 SRI(OPPBUF_CONTROL, OPPBUF, id),\ 46 SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \ 47 SRI(OPPBUF_3D_PARAMETERS_1, OPPBUF, id), \ 48 SRI(OPP_PIPE_CONTROL, OPP_PIPE, id) 49 50#define OPP_REG_LIST_DCN10(id) \ 51 OPP_REG_LIST_DCN(id) 52 53#define OPP_COMMON_REG_VARIABLE_LIST \ 54 uint32_t FMT_BIT_DEPTH_CONTROL; \ 55 uint32_t FMT_CONTROL; \ 56 uint32_t FMT_DITHER_RAND_R_SEED; \ 57 uint32_t FMT_DITHER_RAND_G_SEED; \ 58 uint32_t FMT_DITHER_RAND_B_SEED; \ 59 uint32_t FMT_CLAMP_CNTL; \ 60 uint32_t FMT_DYNAMIC_EXP_CNTL; \ 61 uint32_t FMT_MAP420_MEMORY_CONTROL; \ 62 uint32_t OPPBUF_CONTROL; \ 63 uint32_t OPPBUF_CONTROL1; \ 64 uint32_t OPPBUF_3D_PARAMETERS_0; \ 65 uint32_t OPPBUF_3D_PARAMETERS_1; \ 66 uint32_t OPP_PIPE_CONTROL 67 68#define OPP_MASK_SH_LIST_DCN(mask_sh) \ 69 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ 70 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \ 71 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \ 72 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \ 73 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \ 74 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \ 75 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \ 76 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \ 77 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \ 78 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \ 79 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \ 80 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \ 81 OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \ 82 OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \ 83 OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \ 84 OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \ 85 OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \ 86 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \ 87 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \ 88 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \ 89 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \ 90 OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh), \ 91 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ 92 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, mask_sh),\ 93 OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh), \ 94 OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, mask_sh), \ 95 OPP_SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh) 96 97#define OPP_MASK_SH_LIST_DCN10(mask_sh) \ 98 OPP_MASK_SH_LIST_DCN(mask_sh), \ 99 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\ 100 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh) 101 102#define OPP_DCN10_REG_FIELD_LIST(type) \ 103 type FMT_TRUNCATE_EN; \ 104 type FMT_TRUNCATE_DEPTH; \ 105 type FMT_TRUNCATE_MODE; \ 106 type FMT_SPATIAL_DITHER_EN; \ 107 type FMT_SPATIAL_DITHER_MODE; \ 108 type FMT_SPATIAL_DITHER_DEPTH; \ 109 type FMT_TEMPORAL_DITHER_EN; \ 110 type FMT_HIGHPASS_RANDOM_ENABLE; \ 111 type FMT_FRAME_RANDOM_ENABLE; \ 112 type FMT_RGB_RANDOM_ENABLE; \ 113 type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ 114 type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ 115 type FMT_RAND_R_SEED; \ 116 type FMT_RAND_G_SEED; \ 117 type FMT_RAND_B_SEED; \ 118 type FMT_PIXEL_ENCODING; \ 119 type FMT_SUBSAMPLING_MODE; \ 120 type FMT_CBCR_BIT_REDUCTION_BYPASS; \ 121 type FMT_CLAMP_DATA_EN; \ 122 type FMT_CLAMP_COLOR_FORMAT; \ 123 type FMT_DYNAMIC_EXP_EN; \ 124 type FMT_DYNAMIC_EXP_MODE; \ 125 type FMT_MAP420MEM_PWR_FORCE; \ 126 type FMT_STEREOSYNC_OVERRIDE; \ 127 type OPPBUF_ACTIVE_WIDTH;\ 128 type OPPBUF_PIXEL_REPETITION;\ 129 type OPPBUF_DISPLAY_SEGMENTATION;\ 130 type OPPBUF_OVERLAP_PIXEL_NUM;\ 131 type OPPBUF_NUM_SEGMENT_PADDED_PIXELS; \ 132 type OPPBUF_3D_VACT_SPACE1_SIZE; \ 133 type OPPBUF_3D_VACT_SPACE2_SIZE; \ 134 type OPP_PIPE_CLOCK_EN 135 136struct dcn10_opp_registers { 137 OPP_COMMON_REG_VARIABLE_LIST; 138}; 139 140struct dcn10_opp_shift { 141 OPP_DCN10_REG_FIELD_LIST(uint8_t); 142}; 143 144struct dcn10_opp_mask { 145 OPP_DCN10_REG_FIELD_LIST(uint32_t); 146}; 147 148struct dcn10_opp { 149 struct output_pixel_processor base; 150 151 const struct dcn10_opp_registers *regs; 152 const struct dcn10_opp_shift *opp_shift; 153 const struct dcn10_opp_mask *opp_mask; 154 155 bool is_write_to_ram_a_safe; 156}; 157 158void dcn10_opp_construct(struct dcn10_opp *oppn10, 159 struct dc_context *ctx, 160 uint32_t inst, 161 const struct dcn10_opp_registers *regs, 162 const struct dcn10_opp_shift *opp_shift, 163 const struct dcn10_opp_mask *opp_mask); 164 165void opp1_set_dyn_expansion( 166 struct output_pixel_processor *opp, 167 enum dc_color_space color_sp, 168 enum dc_color_depth color_dpth, 169 enum signal_type signal); 170 171void opp1_program_fmt( 172 struct output_pixel_processor *opp, 173 struct bit_depth_reduction_params *fmt_bit_depth, 174 struct clamping_and_pixel_encoding_params *clamping); 175 176void opp1_program_bit_depth_reduction( 177 struct output_pixel_processor *opp, 178 const struct bit_depth_reduction_params *params); 179 180void opp1_program_stereo( 181 struct output_pixel_processor *opp, 182 bool enable, 183 const struct dc_crtc_timing *timing); 184 185void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable); 186 187void opp1_destroy(struct output_pixel_processor **opp); 188 189#endif 190