1/* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25#ifndef __DC_OPP_DCE_H__ 26#define __DC_OPP_DCE_H__ 27 28#include "dc_types.h" 29#include "opp.h" 30#include "core_types.h" 31 32#define FROM_DCE11_OPP(opp)\ 33 container_of(opp, struct dce110_opp, base) 34 35enum dce110_opp_reg_type { 36 DCE110_OPP_REG_DCP = 0, 37 DCE110_OPP_REG_DCFE, 38 DCE110_OPP_REG_FMT, 39 40 DCE110_OPP_REG_MAX 41}; 42 43#define OPP_COMMON_REG_LIST_BASE(id) \ 44 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 46 SRI(FMT_CONTROL, FMT, id), \ 47 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 48 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 49 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 50 SRI(FMT_CLAMP_CNTL, FMT, id), \ 51 SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \ 52 SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \ 53 SRI(FMT_CLAMP_COMPONENT_B, FMT, id) 54 55#define OPP_DCE_80_REG_LIST(id) \ 56 OPP_COMMON_REG_LIST_BASE(id), \ 57 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 58 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 59 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 60 61#define OPP_DCE_100_REG_LIST(id) \ 62 OPP_COMMON_REG_LIST_BASE(id), \ 63 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 64 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 65 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 66 67#define OPP_DCE_110_REG_LIST(id) \ 68 OPP_COMMON_REG_LIST_BASE(id), \ 69 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 70 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 71 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 72 73#define OPP_DCE_112_REG_LIST(id) \ 74 OPP_COMMON_REG_LIST_BASE(id), \ 75 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 76 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 77 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ 78 SRI(CONTROL, FMT_MEMORY, id) 79 80#define OPP_DCE_120_REG_LIST(id) \ 81 OPP_COMMON_REG_LIST_BASE(id), \ 82 SRI(CONTROL, FMT_MEMORY, id) 83 84#if defined(CONFIG_DRM_AMD_DC_SI) 85#define OPP_DCE_60_REG_LIST(id) \ 86 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 87 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 88 SRI(FMT_CONTROL, FMT, id), \ 89 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 90 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 91 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 92 SRI(FMT_CLAMP_CNTL, FMT, id) 93#endif 94 95#define OPP_SF(reg_name, field_name, post_fix)\ 96 .field_name = reg_name ## __ ## field_name ## post_fix 97 98#define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 99 OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 100 OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 101 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 102 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 103 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 104 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 105 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 106 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 107 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 108 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 109 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 110 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 111 OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 112 OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 113 OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 114 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 115 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 116 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 117 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 118 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 119 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 120 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 121 OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ 122 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 123 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 124 OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ 125 OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ 126 OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ 127 OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ 128 OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ 129 OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ 130 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ 131 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ 132 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh) 133 134#define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ 135 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 136 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 137 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 138 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 139 140#define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ 141 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 142 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 143 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 144 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 145 146#define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 147 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 148 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ 149 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ 150 OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ 151 OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ 152 OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\ 153 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 154 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 155 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 156 157#define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ 158 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) 159 160#define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ 161 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 162 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 163 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 164 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 165 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 166 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 167 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 168 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 169 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 170 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 171 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 172 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 173 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 174 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 175 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 176 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 177 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 178 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 179 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 180 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 181 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 182 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 183 OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\ 184 OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 185 OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 186 OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 187 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ 188 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ 189 OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ 190 OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ 191 OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ 192 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 193 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 194 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ 195 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ 196 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ 197 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ 198 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ 199 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ 200 OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ 201 OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ 202 OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ 203 OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) 204 205#if defined(CONFIG_DRM_AMD_DC_SI) 206#define OPP_COMMON_MASK_SH_LIST_DCE_60(mask_sh)\ 207 OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 208 OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 209 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 210 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 211 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 212 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 213 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 214 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 215 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 216 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 217 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 218 OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 219 OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 220 OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 221 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 222 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 223 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 224 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 225 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 226 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 227 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 228 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 229 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 230 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh) 231#endif 232 233#define OPP_REG_FIELD_LIST(type) \ 234 type FMT_DYNAMIC_EXP_EN; \ 235 type FMT_DYNAMIC_EXP_MODE; \ 236 type FMT_TRUNCATE_EN; \ 237 type FMT_TRUNCATE_DEPTH; \ 238 type FMT_TRUNCATE_MODE; \ 239 type FMT_SPATIAL_DITHER_EN; \ 240 type FMT_SPATIAL_DITHER_DEPTH; \ 241 type FMT_SPATIAL_DITHER_MODE; \ 242 type FMT_TEMPORAL_DITHER_EN; \ 243 type FMT_TEMPORAL_DITHER_RESET; \ 244 type FMT_TEMPORAL_DITHER_OFFSET; \ 245 type FMT_TEMPORAL_DITHER_DEPTH; \ 246 type FMT_TEMPORAL_LEVEL; \ 247 type FMT_25FRC_SEL; \ 248 type FMT_50FRC_SEL; \ 249 type FMT_75FRC_SEL; \ 250 type FMT_HIGHPASS_RANDOM_ENABLE; \ 251 type FMT_FRAME_RANDOM_ENABLE; \ 252 type FMT_RGB_RANDOM_ENABLE; \ 253 type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ 254 type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ 255 type FMT_STEREOSYNC_OVERRIDE; \ 256 type FMT_RAND_R_SEED; \ 257 type FMT_RAND_G_SEED; \ 258 type FMT_RAND_B_SEED; \ 259 type FMT420_MEM0_SOURCE_SEL; \ 260 type FMT420_MEM0_PWR_FORCE; \ 261 type FMT_SRC_SELECT; \ 262 type FMT_420_PIXEL_PHASE_LOCKED_CLEAR; \ 263 type FMT_420_PIXEL_PHASE_LOCKED; \ 264 type FMT_CLAMP_DATA_EN; \ 265 type FMT_CLAMP_COLOR_FORMAT; \ 266 type FMT_CLAMP_LOWER_R; \ 267 type FMT_CLAMP_UPPER_R; \ 268 type FMT_CLAMP_LOWER_G; \ 269 type FMT_CLAMP_UPPER_G; \ 270 type FMT_CLAMP_LOWER_B; \ 271 type FMT_CLAMP_UPPER_B; \ 272 type FMT_PIXEL_ENCODING; \ 273 type FMT_SUBSAMPLING_ORDER; \ 274 type FMT_SUBSAMPLING_MODE; \ 275 type FMT_CBCR_BIT_REDUCTION_BYPASS;\ 276 277struct dce_opp_shift { 278 OPP_REG_FIELD_LIST(uint8_t) 279}; 280 281struct dce_opp_mask { 282 OPP_REG_FIELD_LIST(uint32_t) 283}; 284 285struct dce_opp_registers { 286 uint32_t FMT_DYNAMIC_EXP_CNTL; 287 uint32_t FMT_BIT_DEPTH_CONTROL; 288 uint32_t FMT_CONTROL; 289 uint32_t FMT_DITHER_RAND_R_SEED; 290 uint32_t FMT_DITHER_RAND_G_SEED; 291 uint32_t FMT_DITHER_RAND_B_SEED; 292 uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL; 293 uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX; 294 uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX; 295 uint32_t CONTROL; 296 uint32_t FMT_CLAMP_CNTL; 297 uint32_t FMT_CLAMP_COMPONENT_R; 298 uint32_t FMT_CLAMP_COMPONENT_G; 299 uint32_t FMT_CLAMP_COMPONENT_B; 300}; 301 302/* OPP RELATED */ 303#define TO_DCE110_OPP(opp)\ 304 container_of(opp, struct dce110_opp, base) 305 306struct dce110_opp { 307 struct output_pixel_processor base; 308 const struct dce_opp_registers *regs; 309 const struct dce_opp_shift *opp_shift; 310 const struct dce_opp_mask *opp_mask; 311}; 312 313void dce110_opp_construct(struct dce110_opp *opp110, 314 struct dc_context *ctx, 315 uint32_t inst, 316 const struct dce_opp_registers *regs, 317 const struct dce_opp_shift *opp_shift, 318 const struct dce_opp_mask *opp_mask); 319 320#if defined(CONFIG_DRM_AMD_DC_SI) 321void dce60_opp_construct(struct dce110_opp *opp110, 322 struct dc_context *ctx, 323 uint32_t inst, 324 const struct dce_opp_registers *regs, 325 const struct dce_opp_shift *opp_shift, 326 const struct dce_opp_mask *opp_mask); 327#endif 328 329void dce110_opp_destroy(struct output_pixel_processor **opp); 330 331 332 333/* FORMATTER RELATED */ 334void dce110_opp_program_bit_depth_reduction( 335 struct output_pixel_processor *opp, 336 const struct bit_depth_reduction_params *params); 337 338void dce110_opp_program_clamping_and_pixel_encoding( 339 struct output_pixel_processor *opp, 340 const struct clamping_and_pixel_encoding_params *params); 341 342void dce110_opp_set_dyn_expansion( 343 struct output_pixel_processor *opp, 344 enum dc_color_space color_sp, 345 enum dc_color_depth color_dpth, 346 enum signal_type signal); 347 348void dce110_opp_program_fmt( 349 struct output_pixel_processor *opp, 350 struct bit_depth_reduction_params *fmt_bit_depth, 351 struct clamping_and_pixel_encoding_params *clamping); 352 353void dce110_opp_set_clamping( 354 struct dce110_opp *opp110, 355 const struct clamping_and_pixel_encoding_params *params); 356 357#endif 358