#
4d6bdbad |
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22-Aug-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add support for UVD_NO_OP register Writes to this register are the preferred way to do NOPs. Bump the driver version as well. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d3d8c141 |
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18-Sep-2014 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: split audio enable between eg and r600 (v2) Clean up the enable sequence as well. V2: clean up duplicate defines Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
64d8ee59 |
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16-Sep-2014 |
Kyle McMartin <kyle@redhat.com> |
drm/radeon: delete unused PTE_* defines They don't appear to be used anywhere... elsewhere uses R*_PTE_*. master@linux:U:.% git grep PTE_ -- drivers/gpu/drm/radeon | grep -v _PTE_ master@linux:U:.% (kyle@redacted:~/linux) ./arch/arm64/include/asm/pgtable.h:27:0: note: this is the location of the previous definition #define PTE_VALID (_AT(pteval_t, 1) << 0) ^ In file included from drivers/gpu/drm/radeon/r600_cs.c:31:0: drivers/gpu/drm/radeon/r600d.h:48:0: warning: "PTE_VALID" redefined [enabled by default] #define PTE_VALID (1 << 0) ^ In file included from ./arch/arm64/include/asm/io.h:29:0, from include/linux/clocksource.h:19, from include/clocksource/arm_arch_timer.h:19, from ./arch/arm64/include/asm/arch_timer.h:27, from ./arch/arm64/include/asm/timex.h:19, from include/linux/timex.h:65, <snip> from include/drm/drmP.h:51, from drivers/gpu/drm/radeon/r600_cs.c:29: ./arch/arm64/include/asm/pgtable.h:27:0: note: this is the location of the previous definition #define PTE_VALID (_AT(pteval_t, 1) << 0) ^ Signed-off-by: Kyle McMartin <kyle@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
115365e8 |
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25-Apr-2013 |
Christian König <christian.koenig@amd.com> |
drm/radeon: implement UVD hw workarounds for R6xx v3 Only the essentials, cause this hw generation is really buggy. v2: start supporting RV670,RV620 and RV635 as well v3: activate more workarounds Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
856754c3 |
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16-Apr-2013 |
Christian König <christian.koenig@amd.com> |
drm/radeon: add UVD support for older asics v4 v2: cleanup R600 support v3: rebased on current drm-fixes-3.12 v4: rebased on drm-next-3.14 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4a956a70 |
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28-Nov-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add set_uvd_clocks callback for r6xx v4 v2: wake up PLL, set [VD]CLK_SRC, cleanup code v3: handle RV670,RV635,RV620 as well v4: merge rv6xx and rs780/rs880 code, fix ref divider mask Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
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#
a8fba64a |
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25-Apr-2013 |
Christian König <christian.koenig@amd.com> |
drm/radeon: properly init UVD MC bits on R600 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
86302eea |
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18-Aug-2014 |
Christian König <christian.koenig@amd.com> |
drm/radeon: Sync ME and PFP after CP semaphore waits v4 Fixes lockups due to CP read GPUVM faults when running piglit on Cape Verde. v2 (chk): apply the fix to R600+ as well, on CIK only the GFX CP has a PFP, add more comments to R600 code, enable flushing again v3: (agd5f): only apply to 7xx+. r6xx does not have the packet. v4: (agd5f): split flush change into a separate patch, fix formatting Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com>
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#
68706337 |
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16-May-2014 |
Rafał Miłecki <zajec5@gmail.com> |
drm/radeon/hdmi: DCE2: update setmode Recent RE efforts revealed ops performed by fglrx during HDMI setup. This mostly adds masks to r/w ops plus few single missing bits. This has been tested for possible regressions on: 1) DCE2 HD2400 (RV610) 2) DCE3 HD3470 (RV620) For a reference and details see: https://bugzilla.kernel.org/show_bug.cgi?id=76231 Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2e93cac9 |
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16-May-2014 |
Rafał Miłecki <zajec5@gmail.com> |
drm/radeon/hdmi: DCE3: clean ACR control What initially seemed to be a typo in fglrx (using register 0x740c instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and CRC registers swapped which explains why we needed WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); This has been tested for possible regressions on DCE3 HD3470 (RV620). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d45b964a |
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16-Jan-2014 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: set the full cache bit for fences on r7xx+ Needed to properly flush the read caches for fences. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
de9ae744 |
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01-Nov-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: implement pci config reset for r6xx/7xx (v3) pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. There's not much information still available on r6xx, so r6xx is based on guess-work. v2: put behind module parameter v3: add IGP check Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
134b480f |
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22-Sep-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: Add support for programming the FMT blocks The FMT blocks control how data is sent from the backend of the display pipe to to monitor. Proper set up of the FMT blocks are required for 30bpp formats. Additionally, dithering can be enabled on for better display with 18 and 24bpp displays. The exception is LVDS/eDP which atom takes care of in the SelectCRTC_Source table. For now just enable truncation until we test dithering more. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aa3e146d |
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01-Oct-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: fix typo in CP DMA register headers Wrong bit offset for SRC endian swapping. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
d592fca9 |
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13-Sep-2013 |
Damien Lespiau <damien.lespiau@intel.com> |
drm/radeon: Fix hmdi typo I keep making that one, so checked if I was the only one. Apparently not. Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c1cbee0e |
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29-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/audio: set up the sads on DCE3.2 asics This sets up the short audio descriptors properly on DCE3.2 asics for hdmi audio. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0ffae60c |
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14-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: set speaker allocation for DCE3.2 This updates the audio driver to the speaker allocation block from the EDID. A similar change was just implemented for DCE4-8. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1518dd8e |
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30-Jul-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: fix audio dto calculation on DCE3+ (v3) Need to set the wallclock ratio and adjust the phase and module registers appropriately. May fix problems with audio timing at certain display timings. v2: properly handle clocks below 24mhz v3: rebase r600 changes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
072b5acc |
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11-Jul-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: implement bo copy callback using CP DMA (v2) Lighter weight than using the 3D engine. v2: fix ring count Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
66229b20 |
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25-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add dpm support for rv7xx (v4) This adds dpm support for rv7xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: reduce stack usage v3: fix 64 bit div v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4a6369e9 |
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12-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add dpm support for rv6xx (v3) This adds dpm support for rv6xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: remove duplicate line v3: fix thermal interrupt check noticed by Jerome Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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#
2e9d4c05 |
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12-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add common r600 dpm functions These are shared by rs780/rs880, rv6xx, and newer chips. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2948f5e6 |
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12-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: properly set up the RLC on ON/LN/TN (v3) This is required for certain advanced functionality. v2: save/restore list takes dword offsets v3: rebase on gpu reset changes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
65337e60 |
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05-Apr-2013 |
Samuel Li <samuel.li@amd.com> |
drm/radeon: Use direct mapping for fast fb access on RS780/RS880 (v2) v2: fix trailing whitespace Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
facd112d |
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29-Apr-2013 |
Christian König <christian.koenig@amd.com> |
drm/radeon: consolidate UVD clock programming Instead of duplicating the code over and over again, just use a single function to handle the clock calculations. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1586505a |
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22-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: fix up audio dto programming for DCE2 Uses a different register than DCE3 asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f2ba57b5 |
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07-Apr-2013 |
Christian König <deathsimple@vodafone.de> |
drm/radeon: UVD bringup v8 Just everything needed to decode videos using UVD. v6: just all the bugfixes and support for R7xx-SI merged in one patch v7: UVD_CGC_GATE is a write only register, lockup detection fix v8: split out VRAM fallback changes, remove support for RV770, add support for HEMLOCK, add buffer sizes checks Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f13f7731 |
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18-Jan-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: use status regs to determine what to reset (6xx/7xx) When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d3cb781e |
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18-Jan-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: rework GPU reset on r6xx/r7xx Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4e872ae2 |
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02-Jan-2013 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon: consolidate redundant macros and constants After refactoring the _cs logic, we ended up with many macros and constants that #define the same thing. Clean'em up. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b997a8ba |
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03-Dec-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add register headers for CP DMA on r6xx-SI Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4d75658b |
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27-Sep-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: Add initial support for async DMA on r6xx/r7xx Uses the new multi-ring infrastucture. 6xx/7xx has a single async DMA ring. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
523885de |
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24-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700 Checking of the second colorbuffer was skipped on r700, because CB_TARGET_MASK was 0xf. With r600, CB_TARGET_MASK is changed to 0xff, so we must set the number of samples of the second colorbuffer to 1 in order to pass the CS checker. The DRM version is bumped, because RESOLVE_BOX is always rejected without this fix on r600. Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c116cc94 |
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18-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon: allow CMASK and FMASK in the CS checker on r600-r700 MSAA is impossible without them. Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
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#
6759a0a7 |
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09-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: implement timestamp userspace query (v2) Returns a snapshot of the GPU clock counter. Needed for certain OpenGL extensions. v2: agd5f - address Jerome's comments - add function documentation Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
440a7cd8 |
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26-Jun-2012 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: improve GPU lockup debugging info on r6xx/r7xx/r8xx/r9xx Print various CP register that have valuable informations regarding GPU lockup. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
7c77bf2a |
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14-Jun-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add support for STRMOUT_BASE_UPDATE on 7xx Required for streamout. Bump drm minor. Marek v2: fix pkt->count check Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
b866d133 |
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14-Jun-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add some additional 6xx/7xx/EG register init - SMX_SAR_CTL0 needs to be programmed correctly to prevent problems with memory exports in certain cases. - VC_ENHANCE needs to be initialized on 6xx/7xx. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
416a2bd2 |
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31-May-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: fixup tiling group size and backendmap on r6xx-r9xx (v4) Tiling group size is always 256bits on r6xx/r7xx/r8xx/9xx. Also fix and simplify render backend map. This now properly sets up the backend map on r6xx-9xx which should improve 3D performance. Vadim benchmarked also: Some benchmarks on juniper (5750), fullscreen 1920x1080, first result - kernel 3.4.0+ (fb21affa), second - with these patches: Lightsmark: 91 fps => 123 fps +35% Doom3: 74 fps => 101 fps +36% Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
0783986a |
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14-May-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/hdmi: store info about all AFMT blocks Introduce special struct radeon_afmt for this purpose. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
c6543a6e |
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28-Apr-2012 |
Rafał Miłecki <zajec5@gmail.com> |
drm/radeon/kms/hdmi: use relative offsets, official regs Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Tested-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
3a2a67aa |
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28-Mar-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add register definitions for audio This adds register definitions for HDMI/DP audio on DCE2/3/4/5 hardware. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
88f50c80 |
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21-Mar-2012 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon/kms: add htile support to the cs checker v3 For 6xx+. Required for mesa to use htile support for HiZ/HiS. Userspace will check radeon version 2.14 with is bumped either by tiling patch or stream out patch. This patch only add support for htile relocation which should be enough for any userspace to implement the hyperz (using htile buffer) feature. v2: Jerome: Fix size checking for htile buffer. v3: Jerome: Adapt on top of r600/evergreen cs checker changes, also check htile surface in case only stencil is present. Signed-off-by: Pierre-Eric Pelloux-Prayer <pelloux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
c420c745 |
|
20-Mar-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add support for ucode loading on trinity (v2) v2: fix check for MC ucode from Tom. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
0be70439 |
|
07-Mar-2012 |
Christian König <deathsimple@vodafone.de> |
drm/radeon: fix a semaphore deadlock on pre cayman asics The out of order execution of semaphore commands on pre cayman asics doesn't work correctly and can cause deadlocks, so turn it off for now. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
285484e2 |
|
16-Dec-2011 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: add support for evergreen/ni tiling informations v11 evergreen and northern island gpu needs more informations for 2D tiling than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace to provide those. The v8 cs checking change to track color view on r6xx/r7xx doesn't affect old userspace as old userspace always emited 0 for this register. v2 fix r6xx/r7xx 2D tiling computation v3 fix r6xx/r7xx height align for untiled surface & add support for tile split on evergreen and newer v4 improve tiling debugging output v5 fix tile split code for evergreen and newer v6 set proper tile split for crtc register v7 fix tile split limit value v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs checking, update safe reg for r600, evergreen and cayman. Evergreen checking need some work around for stencil alignment issues v9 fix tile split value range, fix compressed texture handling and mipmap calculation, allow evergreen check to be silencious in front of current broken userspace (depth/stencil alignment issue) v10 fix eg 3d texture and compressed texture, fix r600 depth array, fix r600 color view computation, add support for evergreen stencil split v11 more verbose debugging in some case Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
dd220a00 |
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26-Jan-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: add support for streamout v7 v2: agd5f: add strmout CS checking, copy_dw register checking v3: agd5f: don't use cs_check_reg() for copy_dw checking as it will incorrectly patch the command stream for certain regs. v4: agd5f: add warning if safe reg check fails for copy_dw v5: agd5f: add stricter checking for 6xx/7xx v6: agd5f: add range checking for copy_dw on eg+, add sx_surface_sync to safe reg list for 7xx. v7: agd5f: add stricter checking for eg+ Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
15d3332f |
|
15-Sep-2011 |
Christian König <deathsimple@vodafone.de> |
drm/radeon/kms: add support for semaphores v3 They are used to sync between rings, while fences sync between a ring and the cpu. v2 Fix radeon_semaphore_driver_fini when no semaphore were allocated. v3 Initialize list early on to avoid issue in case or early error Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
|
#
3a38612e |
|
12-Oct-2011 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon/kms: demystify r600 blit code some 3d register bits look like magic in r600 blit functions use predefined constants to make it more intuitive what they are Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
|
#
fcb857ab |
|
06-Jul-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: fix typo in IH_CNTL swap bitfield Only affects BE systems. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
|
#
fe6f0bd0 |
|
06-May-2011 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: add missing Evergreen texture formats to the CS parser BC6 and BC7 are described in ARB_texture_compression_bptc. No idea what FMT_32_AS_32_32_32_32 is good for. Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
|
#
60b212f8 |
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17-Feb-2011 |
Dave Airlie <airlied@redhat.com> |
drm/radeon: overhaul texture checking. (v3) the texture checking code didn't work for block formats like s3tc, this overhauls it to work for all types. v2: add texture array support. v3: add subsampled formats Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
4eace7fd |
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11-Feb-2011 |
Cédric Cano <ccano@interfaceconcept.com> |
drm/radeon/kms: 6xx/7xx big endian fixes agd5f: minor cleanups Signed-off-by: Cédric Cano <ccano@interfaceconcept.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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9e46a48d |
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06-Jan-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add support for gen2 pcie link speeds Supported on rv6xx/r7xx/evergreen. Cards come up in gen1 mode. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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6f34be50 |
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21-Nov-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add pageflip ioctl support (v3) This adds support for dri2 pageflipping. v2: precision updates from Mario Kleiner. v3: Multihead fixes from Mario Kleiner; missing crtc offset add note about update pending bit on pre-avivo chips Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
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16790569 |
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14-Nov-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: fix and unify tiled buffer alignment checking for r6xx/7xx Tiled buffers have the same alignment requirements regardless of whether the surface is for db, cb, or textures. Previously, the calculations where inconsistent for each buffer type. - Unify the alignment calculations in a common function - Standardize the alignment units (pixels for pitch/height/depth, bytes for base) - properly check the buffer base alignments Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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fba4312e |
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14-Nov-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: fix and unify tiled buffer alignment checking for r6xx/7xx Tiled buffers have the same alignment requirements regardless of whether the surface is for db, cb, or textures. Previously, the calculations where inconsistent for each buffer type. - Unify the alignment calculations in a common function - Standardize the alignment units (pixels for pitch/height/depth, bytes for base) - properly check the buffer base alignments Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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d0f8a854 |
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04-Sep-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms/r6xx+: use new style fencing (v3) On r6xx+ a newer fence mechanism was implemented to replace the old wait_until plus scratch regs setup. A single EOP event will flush the destination caches, write a fence value, and generate an interrupt. This is the recommended fence mechanism on r6xx+ asics. This requires my previous writeback patch. v2: fix typo that enabled event fence checking on all asics rather than just r6xx+. v3: properly enable EOP interrupts Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=29972 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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812d0469 |
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26-Jul-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms/r7xx: add workaround for hw issue with HDP flush Use of HDP_*_COHERENCY_FLUSH_CNTL can cause a hang in certain situations. Add workaround. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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7f813377 |
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19-May-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add tiling support to the cs checker for r6xx/r7xx Check for relocs for DB_DEPTH_INFO, CB_COLOR*_INFO, and texture resources. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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21a8122a |
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01-Jul-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add support for internal thermal sensors (v3) rv6xx/rv7xx/evergreen families supported; older asics did not have an internal thermal sensor. Note, not all oems use the internal thermal sensor, so it's only exposed in cases where it is used. Note also, that most laptops use an oem specific ACPI solution for GPU thermal information rather than using the internal thermal sensor directly. v2: export millidegrees celsius, use hwmon device properly. v3: fix Kconfig Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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5f77df36 |
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26-Mar-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/r6xx/r7xx: CS parser fixes - Drop some more safe regs taht userspace shouldn't hit - Constant base regs need relocs. This allows us to use constant buffers rather than the constant register file. Also we don't want userspace to be able to set arbitrary mc base values for the const caches. - Track SQ_CONFIG so we know whether userspace is using the cfile or constant buffers. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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961fb597 |
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10-Feb-2010 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon/kms: r600/r700 command stream checker This patch add cs checker to r600/r700 hw. Command stream checking will rewrite some of the cs value in order to restrict GPU access to BO size. This doesn't break old userspace but just enforce safe value. It should break any things that was using the r600/r700 cs ioctl to do forbidden things (malicious software), though we are not aware of such things. Here is the list of thing we check : - enforcing resource size - enforcing color buffer slice tile max, will restrict cb access - enforcing db buffer slice tile max, will restrict db access We don't check for shader bigger than the BO in which they are supposed to be, such use would lead to GPU lockup and is harmless from security POV, as far as we can tell (note that even checking for this wouldn't prevent someone to write bogus shader that lead to lockup). This patch has received as much testing as humanly possible with old userspace to check that it didn't break such configuration. However not all the applications out there were tested, thus it might broke some odd, rare applications. [airlied: fix rules for cs checker for parallel builds] Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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c8c15ff1 |
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18-Jan-2010 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: r6xx/r7xx possible security issue, system ram access This patch workaround a possible security issue which can allow user to abuse drm on r6xx/r7xx hw to access any system ram memory. This patch doesn't break userspace, it detect "valid" old use of CB_COLOR[0-7]_FRAG & CB_COLOR[0-7]_TILE registers and overwritte the address these registers are pointing to with the one of the last color buffer. This workaround will work for old mesa & xf86-video-ati and any old user which did use similar register programming pattern as those (we expect that there is no others user of those ioctl except possibly a malicious one). This patch add a warning if it detects such usage, warning encourage people to update their mesa & xf86-video-ati. New userspace will submit proper relocation. Fix for xf86-video-ati / mesa (this kernel patch is enough to prevent abuse, fix for userspace are to set proper cs stream and avoid kernel warning) : http://cgit.freedesktop.org/xorg/driver/xf86-video-ati/commit/?id=95d63e408cc88b6934bec84a0b1ef94dfe8bee7b http://cgit.freedesktop.org/mesa/mesa/commit/?id=46dc6fd3ed5ef96cda53641a97bc68c3bc104a9f Abusing this register to perform system ram memory is not easy, here is outline on how it could be achieve. First attacker must have access to the drm device and be able to submit command stream throught cs ioctl. Then attacker must build a proper command stream for r6xx/r7xx hw which will abuse the FRAG or TILE buffer to overwrite the GPU GART which is in VRAM. To achieve so attacker as to setup CB_COLOR[0-7]_FRAG or CB_COLOR[0-7]_TILE to point to the GPU GART, then it has to find a way to write predictable value into those buffer (with little cleverness i believe this can be done but this is an hard task). Once attacker have such program it can overwritte GPU GART to program GPU gart to point anywhere in system memory. It then can reusse same method as he used to reprogram GART to overwritte the system ram through the GART mapping. In the process the attacker has to be carefull to not overwritte any sensitive area of the GART table, like ring or IB gart entry as it will more then likely lead to GPU lockup. Bottom line is that i think it's very hard to use this flaw to get system ram access but in theory one can achieve so. Side note: I am not aware of anyone ever using the GPU as an attack vector, nevertheless we take great care in the opensource driver to try to detect and forbid malicious use of GPU. I don't think the closed source driver are as cautious as we are. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
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b500f680 |
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03-Dec-2009 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add regs and irq tracking bits for hpd Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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d8f60cfc |
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01-Dec-2009 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: Add support for interrupts on r6xx/r7xx chips (v3) This enables the use of interrupts on r6xx/r7xx hardware. Interrupts are implemented via a ring buffer. The GPU adds interrupts vectors to the ring and the host reads them off in the interrupt handler. The interrupt controller requires firmware like the CP. This firmware must be installed and accessble to the firmware loader for interrupts to function. MSIs don't seem to work on my RS780. They work fine on all my discrete cards. I'm not sure about other RS780s or RS880s. I've disabled MSIs on RS780 and RS880, but it would probably be worth checking on some other systems. v2 - fix some checkpatch.pl problems; re-read the disp int status reg if we restart the ih; v3 - remove the irq handler if r600_irq_init() fails; remove spinlock in r600_ih_ring_fini(); move ih rb overflow check to r600_get_ih_wptr(); move irq ack to separate function; Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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23956dfa |
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22-Nov-2009 |
Dave Airlie <airlied@redhat.com> |
drm/radeon/kms: add HDP flushing for all GPUs. rendercheck under kms on r600s was failing due to HDP flushing not happening. This adds HDP flushing to the object wait function for r100->r700 families. rendercheck passes basic tests on r600 with this change. Acked-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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a39533b4 |
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09-Nov-2009 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/r600: CS parser updates Add some additional regs that require relocs. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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5885b7a9 |
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19-Oct-2009 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: fix vram_width calculation on r6xx/r7xx Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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1a029b76 |
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06-Oct-2009 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon/kms: Fix AGP support for R600/RV770 family (v2) For AGP to work unmapped access must cover VRAM & AGP as AGP is treated like VRAM by the GPU (ie physical address). This patch properly setup the virtual memory system aperture to cover AGP if AGP is enabled. It seems that there is memory corruption after resume when using AGP (RV770 seems unaffected thought). Version 2 just fix merge issue with updated AGP fallback patch. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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28d52043 |
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20-Sep-2009 |
Dave Airlie <airlied@redhat.com> |
drm/vgaarb: add VGA arbitration support to the drm and kms. VGA arb requires DRM support for non-kms drivers, to turn on/off irqs when disabling the mem/io regions. VGA arb requires KMS support for GPUs where we can turn off VGA decoding. Currently we know how to do this for intel and radeon kms drivers, which allows them to be removed from the arbiter. This patch comes from Fedora rawhide kernel. Signed-off-by: Dave Airlie <airlied@redhat.com>
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3ce0a23d |
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07-Sep-2009 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon/kms: add r600 KMS support This adds the r600 KMS + CS support to the Linux kernel. The r600 TTM support is quite basic and still needs more work esp around using interrupts, but the polled fencing should work okay for now. Also currently TTM is using memcpy to do VRAM moves, the code is here to use a 3D blit to do this, but isn't fully debugged yet. Authors: Alex Deucher <alexdeucher@gmail.com> Dave Airlie <airlied@redhat.com> Jerome Glisse <jglisse@redhat.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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