| /u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | clock-k2hk.h | 38 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
39 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
40 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
41 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram.h | 11 DDR3 = 3, enumerator in enum:__anon3
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| /u-boot/drivers/ram/rockchip/ |
| H A D | sdram-px30-ddr3-detect-333.inc | 28 .dramtype = DDR3,
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| H A D | sdram-rv1126-ddr3-detect-1056.inc | 28 .dramtype = DDR3,
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| H A D | sdram-rv1126-ddr3-detect-328.inc | 28 .dramtype = DDR3,
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| H A D | sdram-rv1126-ddr3-detect-396.inc | 28 .dramtype = DDR3,
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| H A D | sdram-rv1126-ddr3-detect-528.inc | 28 .dramtype = DDR3,
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| H A D | sdram-rv1126-ddr3-detect-664.inc | 28 .dramtype = DDR3,
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| H A D | sdram-rv1126-ddr3-detect-784.inc | 28 .dramtype = DDR3,
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| H A D | sdram-rv1126-ddr3-detect-924.inc | 28 .dramtype = DDR3,
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| H A D | sdram_pctl_px30.c | 38 if (dramtype == DDR3 || dramtype == DDR4) {
169 * If DDR3 or DDR4 MSTR.active_ranks=1,
173 if (cap_info->rank == 2 || dram_type == DDR3 ||
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| H A D | sdram_rv1126.c | 768 else if (dramtype == DDR3)
933 if (dramtype == DDR3) {
990 if (dramtype != DDR3 && dram_odt_ohm)
1059 if (dramtype == DDR3 || dramtype == DDR4) {
1069 if (dramtype == DDR3) {
1174 if (dramtype == DDR4 || dramtype == DDR3) {
1613 if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2)
1616 if (dramtype == DDR3 || dramtype == DDR4)
1647 if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2)
1680 if (dramtype == DDR3
[all...] |
| H A D | sdram_common.c | 17 case DDR3:
18 printascii("DDR3");
294 if (dram_type == DDR3 || dram_type == LPDDR4) {
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| H A D | sdram_phy_px30.c | 57 if (dram_type == DDR3) {
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| H A D | sdram_rk322x.c | 169 if (dramtype == DDR3) {
426 if (dramtype == DDR3) {
486 case DDR3:
608 if (sdram_params->base.dramtype == DDR3)
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| H A D | sdram_rk3188.c | 237 case DDR3:
285 case DDR3:
335 | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
720 if ((sdram_params->base.dramtype == DDR3 &&
788 /* DDR3 and LPDDR3 are always 8 bank, no need detect */
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| H A D | sdram_rk3066.c | 225 case DDR3:
272 case DDR3:
322 | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
690 if ((sdram_params->base.dramtype == DDR3 &&
760 /* DDR3 and LPDDR3 are always 8 bank, no need to detect. */
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| H A D | sdram_rk3288.c | 270 case DDR3:
344 case DDR3:
394 | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
793 if ((sdram_params->base.dramtype == DDR3 &&
905 /* DDR3 and LPDDR3 are always 8 bank, no need detect */
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| H A D | sdram_px30.c | 453 else if (sdram_params->base.dramtype == DDR3)
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| H A D | sdram_rk3399.c | 338 if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
433 } else if (params->base.dramtype == DDR3) {
1394 } else if (params->base.dramtype == DDR3) {
1410 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
1419 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
1428 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
1636 * DDR3 is not have CA training.
2588 if (cs_map == 1 && dramtype == DDR3)
2703 * DDR3 is not have CA training.
2912 if ((dramtype == DDR3
[all...] |
| H A D | dmc-rk3368.c | 165 /* Set to DDR3 mode */
252 * "16.6.2 Initialization (DDR3 Initialization Sequence)"
463 pr_err("%s: unimplemented DDR3 speed bin %d\n",
507 /* The DDR3 mode-register does only support even values for tWR > 8. */
516 pctl_timing->tdqs = 1; /* fixed for DDR3 */
525 pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
534 tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
568 /* DDR3 */
783 sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
860 /* DDR3 i
[all...] |
| /u-boot/arch/x86/include/asm/arch-quark/ |
| H A D | mrc.h | 44 DDR3, enumerator in enum:__anon476
114 uint8_t ddr_type; /* DDR3, DDR3L */
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| /u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a83t.c | 446 #error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3)
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| /u-boot/cmd/ |
| H A D | i2c.c | 1115 enum { unknown, EDO, SDRAM, DDR, DDR2, DDR3, DDR4 } type; enumerator in enum:__anon7
1221 type = DDR3;
1222 puts("DDR3\n");
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