1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * (C) Copyright 2015 Google, Inc 4 * Copyright 2014 Rockchip Inc. 5 * 6 * Adapted from the very similar rk3188 ddr init. 7 */ 8 9#include <common.h> 10#include <clk.h> 11#include <dm.h> 12#include <dt-structs.h> 13#include <errno.h> 14#include <hang.h> 15#include <init.h> 16#include <log.h> 17#include <ram.h> 18#include <regmap.h> 19#include <syscon.h> 20#include <asm/arch-rockchip/clock.h> 21#include <asm/arch-rockchip/cru_rk3066.h> 22#include <asm/arch-rockchip/ddr_rk3188.h> 23#include <asm/arch-rockchip/grf_rk3066.h> 24#include <asm/arch-rockchip/hardware.h> 25#include <asm/arch-rockchip/pmu_rk3188.h> 26#include <asm/arch-rockchip/sdram_rk3288.h> 27#include <asm/arch-rockchip/sdram.h> 28#include <linux/delay.h> 29#include <linux/err.h> 30 31struct rk3066_dmc_chan_info { 32 struct rk3288_ddr_pctl *pctl; 33 struct rk3288_ddr_publ *publ; 34 struct rk3188_msch *msch; 35}; 36 37struct rk3066_dmc_dram_info { 38 struct rk3066_dmc_chan_info chan[1]; 39 struct ram_info info; 40 struct clk ddr_clk; 41 struct rk3066_cru *cru; 42 struct rk3066_grf *grf; 43 struct rk3066_sgrf *sgrf; 44 struct rk3188_pmu *pmu; 45}; 46 47struct rk3066_dmc_sdram_params { 48#if CONFIG_IS_ENABLED(OF_PLATDATA) 49 struct dtd_rockchip_rk3066_dmc of_plat; 50#endif 51 struct rk3288_sdram_channel ch[2]; 52 struct rk3288_sdram_pctl_timing pctl_timing; 53 struct rk3288_sdram_phy_timing phy_timing; 54 struct rk3288_base_params base; 55 int num_channels; 56 struct regmap *map; 57}; 58 59const int rk3066_dmc_ddrconf_table[] = { 60 /* 61 * [5:4] row(13+n) 62 * [1:0] col(9+n), assume bw=2 63 * row col,bw 64 */ 65 0, 66 (2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, 67 (1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, 68 (0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, 69 (2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, 70 (1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, 71 (0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, 72 (1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT, 73 (0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT, 74 0, 75 0, 76 0, 77 0, 78 0, 79 0, 80 0, 81}; 82 83#define TEST_PATTERN 0x5aa5f00f 84#define DQS_GATE_TRAINING_ERROR_RANK0 BIT(4) 85#define DQS_GATE_TRAINING_ERROR_RANK1 BIT(5) 86 87static void rk3066_dmc_copy_to_reg(u32 *dest, const u32 *src, u32 n) 88{ 89 int i; 90 91 for (i = 0; i < n / sizeof(u32); i++) { 92 writel(*src, dest); 93 src++; 94 dest++; 95 } 96} 97 98static void rk3066_dmc_ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy) 99{ 100 u32 phy_ctl_srstn_shift = 13; 101 u32 ctl_psrstn_shift = 11; 102 u32 ctl_srstn_shift = 10; 103 u32 phy_psrstn_shift = 9; 104 u32 phy_srstn_shift = 8; 105 106 rk_clrsetreg(&cru->cru_softrst_con[5], 107 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | 108 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | 109 1 << phy_srstn_shift, 110 phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | 111 ctl << ctl_srstn_shift | phy << phy_psrstn_shift | 112 phy << phy_srstn_shift); 113} 114 115static void rk3066_dmc_ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n) 116{ 117 u32 phy_ctl_srstn_shift = 13; 118 119 rk_clrsetreg(&cru->cru_softrst_con[5], 120 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); 121} 122 123static void rk3066_dmc_phy_pctrl_reset(struct rk3066_cru *cru, 124 struct rk3288_ddr_publ *publ, 125 int channel) 126{ 127 int i; 128 129 rk3066_dmc_ddr_reset(cru, channel, 1, 1); 130 udelay(1); 131 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); 132 for (i = 0; i < 4; i++) 133 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); 134 135 udelay(10); 136 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); 137 for (i = 0; i < 4; i++) 138 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); 139 140 udelay(10); 141 rk3066_dmc_ddr_reset(cru, channel, 1, 0); 142 udelay(10); 143 rk3066_dmc_ddr_reset(cru, channel, 0, 0); 144 udelay(10); 145} 146 147static void rk3066_dmc_phy_dll_bypass_set(struct rk3288_ddr_publ *publ, u32 freq) 148{ 149 int i; 150 151 if (freq <= 250000000) { 152 if (freq <= 150000000) 153 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); 154 else 155 setbits_le32(&publ->dllgcr, SBIAS_BYPASS); 156 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); 157 for (i = 0; i < 4; i++) 158 setbits_le32(&publ->datx8[i].dxdllcr, 159 DXDLLCR_DLLDIS); 160 161 setbits_le32(&publ->pir, PIR_DLLBYP); 162 } else { 163 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); 164 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); 165 for (i = 0; i < 4; i++) { 166 clrbits_le32(&publ->datx8[i].dxdllcr, 167 DXDLLCR_DLLDIS); 168 } 169 170 clrbits_le32(&publ->pir, PIR_DLLBYP); 171 } 172} 173 174static void rk3066_dmc_dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) 175{ 176 writel(DFI_INIT_START, &pctl->dfistcfg0); 177 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, 178 &pctl->dfistcfg1); 179 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); 180 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, 181 &pctl->dfilpcfg0); 182 183 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); 184 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); 185 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); 186 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); 187 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); 188 writel(1, &pctl->dfitphyupdtype0); 189 190 /* CS0 and CS1 write ODT enable. */ 191 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), 192 &pctl->dfiodtcfg); 193 /* Write ODT length. */ 194 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); 195 /* Disable phyupd and ctrlupd. */ 196 writel(0, &pctl->dfiupdcfg); 197} 198 199static void rk3066_dmc_ddr_set_ddr3_mode(struct rk3066_grf *grf, uint channel, 200 bool ddr3_mode) 201{ 202 uint mask, val; 203 204 mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT; 205 val = ddr3_mode << MSCH4_MAINDDR3_SHIFT; 206 rk_clrsetreg(&grf->soc_con2, mask, val); 207} 208 209static void rk3066_dmc_ddr_rank_2_row15en(struct rk3066_grf *grf, bool enable) 210{ 211 uint mask, val; 212 213 mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT; 214 val = enable << RANK_TO_ROW15_EN_SHIFT; 215 rk_clrsetreg(&grf->soc_con2, mask, val); 216} 217 218static void rk3066_dmc_pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, 219 struct rk3066_dmc_sdram_params *sdram_params, 220 struct rk3066_grf *grf) 221{ 222 rk3066_dmc_copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, 223 sizeof(sdram_params->pctl_timing)); 224 switch (sdram_params->base.dramtype) { 225 case DDR3: 226 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { 227 writel(sdram_params->pctl_timing.tcl - 3, 228 &pctl->dfitrddataen); 229 } else { 230 writel(sdram_params->pctl_timing.tcl - 2, 231 &pctl->dfitrddataen); 232 } 233 writel(sdram_params->pctl_timing.tcwl - 1, 234 &pctl->dfitphywrlat); 235 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | 236 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | 237 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, 238 &pctl->mcfg); 239 rk3066_dmc_ddr_set_ddr3_mode(grf, channel, true); 240 break; 241 } 242 243 setbits_le32(&pctl->scfg, 1); 244} 245 246static void rk3066_dmc_phy_cfg(const struct rk3066_dmc_chan_info *chan, int channel, 247 struct rk3066_dmc_sdram_params *sdram_params) 248{ 249 struct rk3288_ddr_publ *publ = chan->publ; 250 struct rk3188_msch *msch = chan->msch; 251 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; 252 u32 dinit2; 253 int i; 254 255 dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); 256 /* Set DDR PHY timing. */ 257 rk3066_dmc_copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, 258 sizeof(sdram_params->phy_timing)); 259 writel(sdram_params->base.noc_timing, &msch->ddrtiming); 260 writel(0x3f, &msch->readlatency); 261 writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | 262 DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | 263 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); 264 writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | 265 DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, 266 &publ->ptr[1]); 267 writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | 268 DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, 269 &publ->ptr[2]); 270 271 switch (sdram_params->base.dramtype) { 272 case DDR3: 273 clrbits_le32(&publ->pgcr, 0x1f); 274 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, 275 DDRMD_DDR3 << DDRMD_SHIFT); 276 break; 277 } 278 if (sdram_params->base.odt) { 279 /* Enable dynamic RTT. */ 280 for (i = 0; i < 4; i++) 281 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); 282 } else { 283 /* Disable dynamic RTT. */ 284 for (i = 0; i < 4; i++) 285 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); 286 } 287} 288 289static void rk3066_dmc_phy_init(struct rk3288_ddr_publ *publ) 290{ 291 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST 292 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); 293 udelay(1); 294 while ((readl(&publ->pgsr) & 295 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != 296 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) 297 ; 298} 299 300static void rk3066_dmc_send_command(struct rk3288_ddr_pctl *pctl, u32 rank, 301 u32 cmd, u32 arg) 302{ 303 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); 304 udelay(1); 305 while (readl(&pctl->mcmd) & START_CMD) 306 ; 307} 308 309static inline void rk3066_dmc_send_command_op(struct rk3288_ddr_pctl *pctl, 310 u32 rank, u32 cmd, u32 ma, u32 op) 311{ 312 rk3066_dmc_send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | 313 (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); 314} 315 316static void rk3066_dmc_memory_init(struct rk3288_ddr_publ *publ, 317 u32 dramtype) 318{ 319 setbits_le32(&publ->pir, 320 (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP 321 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC 322 | (dramtype == DDR3 ? PIR_DRAMRST : 0))); 323 udelay(1); 324 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) 325 != (PGSR_IDONE | PGSR_DLDONE)) 326 ; 327} 328 329static void rk3066_dmc_move_to_config_state(struct rk3288_ddr_publ *publ, 330 struct rk3288_ddr_pctl *pctl) 331{ 332 unsigned int state; 333 334 while (1) { 335 state = readl(&pctl->stat) & PCTL_STAT_MSK; 336 337 switch (state) { 338 case LOW_POWER: 339 writel(WAKEUP_STATE, &pctl->sctl); 340 while ((readl(&pctl->stat) & PCTL_STAT_MSK) 341 != ACCESS) 342 ; 343 /* Wait DLL lock. */ 344 while ((readl(&publ->pgsr) & PGSR_DLDONE) 345 != PGSR_DLDONE) 346 ; 347 /* 348 * If at low power state we need to wakeup first 349 * and then enter the config. 350 */ 351 fallthrough; 352 case ACCESS: 353 fallthrough; 354 case INIT_MEM: 355 writel(CFG_STATE, &pctl->sctl); 356 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 357 ; 358 break; 359 case CONFIG: 360 return; 361 default: 362 break; 363 } 364 } 365} 366 367static void rk3066_dmc_set_bandwidth_ratio(const struct rk3066_dmc_chan_info *chan, int channel, 368 u32 n, struct rk3066_grf *grf) 369{ 370 struct rk3288_ddr_pctl *pctl = chan->pctl; 371 struct rk3288_ddr_publ *publ = chan->publ; 372 struct rk3188_msch *msch = chan->msch; 373 374 if (n == 1) { 375 setbits_le32(&pctl->ppcfg, 1); 376 setbits_le32(&msch->ddrtiming, 1 << 31); 377 /* Data byte disable. */ 378 clrbits_le32(&publ->datx8[2].dxgcr, 1); 379 clrbits_le32(&publ->datx8[3].dxgcr, 1); 380 /* Disable DLL. */ 381 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); 382 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); 383 } else { 384 clrbits_le32(&pctl->ppcfg, 1); 385 clrbits_le32(&msch->ddrtiming, 1 << 31); 386 /* Data byte enable.*/ 387 setbits_le32(&publ->datx8[2].dxgcr, 1); 388 setbits_le32(&publ->datx8[3].dxgcr, 1); 389 390 /* Enable DLL. */ 391 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); 392 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); 393 /* Reset DLL. */ 394 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); 395 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); 396 udelay(10); 397 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); 398 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); 399 } 400 setbits_le32(&pctl->dfistcfg0, 1 << 2); 401} 402 403static int rk3066_dmc_data_training(const struct rk3066_dmc_chan_info *chan, int channel, 404 struct rk3066_dmc_sdram_params *sdram_params) 405{ 406 unsigned int j; 407 int ret = 0; 408 u32 rank; 409 int i; 410 u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; 411 struct rk3288_ddr_publ *publ = chan->publ; 412 struct rk3288_ddr_pctl *pctl = chan->pctl; 413 414 /* Disable auto refresh. */ 415 writel(0, &pctl->trefi); 416 417 if (sdram_params->base.dramtype != LPDDR3) 418 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); 419 rank = sdram_params->ch[channel].rank | 1; 420 for (j = 0; j < ARRAY_SIZE(step); j++) { 421 /* 422 * Trigger QSTRN and RVTRN. 423 * Clear DTDONE status. 424 */ 425 setbits_le32(&publ->pir, PIR_CLRSR); 426 427 /* Trigger DTT. */ 428 setbits_le32(&publ->pir, 429 PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | 430 PIR_CLRSR); 431 udelay(1); 432 /* Wait echo byte DTDONE. */ 433 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) 434 != rank) 435 ; 436 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) 437 != rank) 438 ; 439 if (!(readl(&pctl->ppcfg) & 1)) { 440 while ((readl(&publ->datx8[2].dxgsr[0]) 441 & rank) != rank) 442 ; 443 while ((readl(&publ->datx8[3].dxgsr[0]) 444 & rank) != rank) 445 ; 446 } 447 if (readl(&publ->pgsr) & 448 (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { 449 ret = -1; 450 break; 451 } 452 } 453 /* Send some auto refresh to complement the lost while DTT. */ 454 for (i = 0; i < (rank > 1 ? 8 : 4); i++) 455 rk3066_dmc_send_command(pctl, rank, REF_CMD, 0); 456 457 if (sdram_params->base.dramtype != LPDDR3) 458 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); 459 460 /* Resume auto refresh. */ 461 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); 462 463 return ret; 464} 465 466static void rk3066_dmc_move_to_access_state(const struct rk3066_dmc_chan_info *chan) 467{ 468 struct rk3288_ddr_publ *publ = chan->publ; 469 struct rk3288_ddr_pctl *pctl = chan->pctl; 470 unsigned int state; 471 472 while (1) { 473 state = readl(&pctl->stat) & PCTL_STAT_MSK; 474 475 switch (state) { 476 case LOW_POWER: 477 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & 478 LP_TRIG_MASK) == 1) 479 return; 480 481 writel(WAKEUP_STATE, &pctl->sctl); 482 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) 483 ; 484 /* Wait DLL lock. */ 485 while ((readl(&publ->pgsr) & PGSR_DLDONE) 486 != PGSR_DLDONE) 487 ; 488 break; 489 case INIT_MEM: 490 writel(CFG_STATE, &pctl->sctl); 491 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 492 ; 493 fallthrough; 494 case CONFIG: 495 writel(GO_STATE, &pctl->sctl); 496 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) 497 ; 498 break; 499 case ACCESS: 500 return; 501 default: 502 break; 503 } 504 } 505} 506 507static void rk3066_dmc_dram_cfg_rbc(const struct rk3066_dmc_chan_info *chan, u32 chnum, 508 struct rk3066_dmc_sdram_params *sdram_params) 509{ 510 struct rk3288_ddr_publ *publ = chan->publ; 511 512 if (sdram_params->ch[chnum].bk == 3) 513 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, 514 1 << PDQ_SHIFT); 515 else 516 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); 517 518 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); 519} 520 521static void rk3066_dmc_dram_all_config(const struct rk3066_dmc_dram_info *dram, 522 struct rk3066_dmc_sdram_params *sdram_params) 523{ 524 unsigned int chan; 525 u32 sys_reg = 0; 526 527 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; 528 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; 529 for (chan = 0; chan < sdram_params->num_channels; chan++) { 530 const struct rk3288_sdram_channel *info = 531 &sdram_params->ch[chan]; 532 533 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); 534 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); 535 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); 536 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); 537 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); 538 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); 539 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); 540 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); 541 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); 542 543 rk3066_dmc_dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); 544 } 545 if (sdram_params->ch[0].rank == 2) 546 rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0); 547 else 548 rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1); 549 550 writel(sys_reg, &dram->pmu->sys_reg[2]); 551} 552 553static int rk3066_dmc_sdram_rank_bw_detect(struct rk3066_dmc_dram_info *dram, int channel, 554 struct rk3066_dmc_sdram_params *sdram_params) 555{ 556 int reg; 557 int need_trainig = 0; 558 const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; 559 struct rk3288_ddr_publ *publ = chan->publ; 560 561 rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0); 562 563 if (rk3066_dmc_data_training(chan, channel, sdram_params) < 0) { 564 debug("first data training fail!\n"); 565 reg = readl(&publ->datx8[0].dxgsr[0]); 566 /* Check the result for rank 0. */ 567 if (channel == 0 && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { 568 debug("data training fail!\n"); 569 return -EIO; 570 } 571 572 /* Check the result for rank 1. */ 573 if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { 574 sdram_params->ch[channel].rank = 1; 575 clrsetbits_le32(&publ->pgcr, 0xF << 18, 576 sdram_params->ch[channel].rank << 18); 577 need_trainig = 1; 578 } 579 reg = readl(&publ->datx8[2].dxgsr[0]); 580 if (reg & (1 << 4)) { 581 sdram_params->ch[channel].bw = 1; 582 rk3066_dmc_set_bandwidth_ratio(chan, channel, 583 sdram_params->ch[channel].bw, 584 dram->grf); 585 need_trainig = 1; 586 } 587 } 588 /* Assume that the die bit width is equel to the chip bit width. */ 589 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; 590 591 if (need_trainig && 592 (rk3066_dmc_data_training(chan, channel, sdram_params) < 0)) { 593 if (sdram_params->base.dramtype == LPDDR3) { 594 rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 1); 595 udelay(10); 596 rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 0); 597 udelay(10); 598 } 599 debug("2nd data training failed!"); 600 return -EIO; 601 } 602 603 return 0; 604} 605 606static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, int channel, 607 struct rk3066_dmc_sdram_params *sdram_params) 608{ 609 int row, col; 610 unsigned int addr; 611 const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; 612 struct rk3288_ddr_pctl *pctl = chan->pctl; 613 struct rk3288_ddr_publ *publ = chan->publ; 614 int ret = 0; 615 616 /* Detect col. */ 617 for (col = 11; col >= 9; col--) { 618 writel(0, CFG_SYS_SDRAM_BASE); 619 addr = CFG_SYS_SDRAM_BASE + 620 (1 << (col + sdram_params->ch[channel].bw - 1)); 621 writel(TEST_PATTERN, addr); 622 if ((readl(addr) == TEST_PATTERN) && 623 (readl(CFG_SYS_SDRAM_BASE) == 0)) 624 break; 625 } 626 if (col == 8) { 627 debug("Col detect error\n"); 628 ret = -EINVAL; 629 goto out; 630 } else { 631 sdram_params->ch[channel].col = col; 632 } 633 634 rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1); 635 rk3066_dmc_move_to_config_state(publ, pctl); 636 writel(1, &chan->msch->ddrconf); 637 rk3066_dmc_move_to_access_state(chan); 638 /* Detect row, max 15, min13 for rk3066 */ 639 for (row = 16; row >= 13; row--) { 640 writel(0, CFG_SYS_SDRAM_BASE); 641 addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); 642 writel(TEST_PATTERN, addr); 643 if ((readl(addr) == TEST_PATTERN) && 644 (readl(CFG_SYS_SDRAM_BASE) == 0)) 645 break; 646 } 647 if (row == 12) { 648 debug("Row detect error\n"); 649 ret = -EINVAL; 650 } else { 651 sdram_params->ch[channel].cs1_row = row; 652 sdram_params->ch[channel].row_3_4 = 0; 653 debug("chn %d col %d, row %d\n", channel, col, row); 654 sdram_params->ch[channel].cs0_row = row; 655 } 656 657out: 658 return ret; 659} 660 661static int rk3066_dmc_sdram_get_niu_config(struct rk3066_dmc_sdram_params *sdram_params) 662{ 663 int i, tmp, size, ret = 0; 664 665 tmp = sdram_params->ch[0].col - 9; 666 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; 667 tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4); 668 size = ARRAY_SIZE(rk3066_dmc_ddrconf_table) / sizeof(rk3066_dmc_ddrconf_table[0]); 669 for (i = 0; i < size; i++) 670 if (tmp == rk3066_dmc_ddrconf_table[i]) 671 break; 672 if (i >= size) { 673 debug("niu config not found\n"); 674 ret = -EINVAL; 675 } else { 676 debug("niu config %d\n", i); 677 sdram_params->base.ddrconfig = i; 678 } 679 680 return ret; 681} 682 683static int rk3066_dmc_sdram_init(struct rk3066_dmc_dram_info *dram, 684 struct rk3066_dmc_sdram_params *sdram_params) 685{ 686 int channel; 687 int zqcr; 688 int ret; 689 690 if ((sdram_params->base.dramtype == DDR3 && 691 sdram_params->base.ddr_freq > 800000000)) { 692 debug("SDRAM frequency is too high!"); 693 return -E2BIG; 694 } 695 696 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); 697 if (ret) { 698 debug("Could not set DDR clock\n"); 699 return ret; 700 } 701 702 for (channel = 0; channel < 1; channel++) { 703 const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; 704 struct rk3288_ddr_pctl *pctl = chan->pctl; 705 struct rk3288_ddr_publ *publ = chan->publ; 706 707 rk3066_dmc_phy_pctrl_reset(dram->cru, publ, channel); 708 rk3066_dmc_phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); 709 710 rk3066_dmc_dfi_cfg(pctl, sdram_params->base.dramtype); 711 712 rk3066_dmc_pctl_cfg(channel, pctl, sdram_params, dram->grf); 713 714 rk3066_dmc_phy_cfg(chan, channel, sdram_params); 715 716 rk3066_dmc_phy_init(publ); 717 718 writel(POWER_UP_START, &pctl->powctl); 719 while (!(readl(&pctl->powstat) & POWER_UP_DONE)) 720 ; 721 722 rk3066_dmc_memory_init(publ, sdram_params->base.dramtype); 723 rk3066_dmc_move_to_config_state(publ, pctl); 724 725 /* Use 32bit bus width for detection. */ 726 sdram_params->ch[channel].bw = 2; 727 rk3066_dmc_set_bandwidth_ratio(chan, channel, 728 sdram_params->ch[channel].bw, dram->grf); 729 /* 730 * set cs, using n=3 for detect 731 * CS0, n=1 732 * CS1, n=2 733 * CS0 & CS1, n = 3 734 */ 735 sdram_params->ch[channel].rank = 2; 736 clrsetbits_le32(&publ->pgcr, 0xF << 18, 737 (sdram_params->ch[channel].rank | 1) << 18); 738 739 /* DS=40ohm,ODT=155ohm */ 740 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | 741 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | 742 0x19 << PD_OUTPUT_SHIFT; 743 writel(zqcr, &publ->zq1cr[0]); 744 writel(zqcr, &publ->zq0cr[0]); 745 746 /* Detect the rank and bit-width with data-training. */ 747 writel(1, &chan->msch->ddrconf); 748 rk3066_dmc_sdram_rank_bw_detect(dram, channel, sdram_params); 749 750 if (sdram_params->base.dramtype == LPDDR3) { 751 u32 i; 752 753 writel(0, &pctl->mrrcfg0); 754 755 for (i = 0; i < 17; i++) 756 rk3066_dmc_send_command_op(pctl, 1, MRR_CMD, i, 0); 757 } 758 writel(4, &chan->msch->ddrconf); 759 rk3066_dmc_move_to_access_state(chan); 760 /* DDR3 and LPDDR3 are always 8 bank, no need to detect. */ 761 sdram_params->ch[channel].bk = 3; 762 /* Detect Col and Row number. */ 763 ret = rk3066_dmc_sdram_col_row_detect(dram, channel, sdram_params); 764 if (ret) 765 goto error; 766 } 767 /* Find NIU DDR configuration. */ 768 ret = rk3066_dmc_sdram_get_niu_config(sdram_params); 769 if (ret) 770 goto error; 771 772 rk3066_dmc_dram_all_config(dram, sdram_params); 773 debug("SDRAM init OK!\n"); 774 775 return 0; 776error: 777 debug("SDRAM init failed!\n"); 778 hang(); 779} 780 781static int rk3066_dmc_setup_sdram(struct udevice *dev) 782{ 783 struct rk3066_dmc_dram_info *priv = dev_get_priv(dev); 784 struct rk3066_dmc_sdram_params *params = dev_get_plat(dev); 785 786 return rk3066_dmc_sdram_init(priv, params); 787} 788 789static int rk3066_dmc_conv_of_plat(struct udevice *dev) 790{ 791#if CONFIG_IS_ENABLED(OF_PLATDATA) 792 struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev); 793 struct dtd_rockchip_rk3066_dmc *of_plat = &plat->of_plat; 794 int ret; 795 796 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, 797 sizeof(plat->pctl_timing)); 798 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, 799 sizeof(plat->phy_timing)); 800 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); 801 /* RK3066 supports dual-channel, set default channel num to 2. */ 802 plat->num_channels = 1; 803 ret = regmap_init_mem_plat(dev, of_plat->reg, sizeof(of_plat->reg[0]), 804 ARRAY_SIZE(of_plat->reg) / 2, &plat->map); 805 if (ret) 806 return ret; 807 808 return 0; 809#else 810 return -EINVAL; 811#endif 812} 813 814static int rk3066_dmc_probe(struct udevice *dev) 815{ 816 struct rk3066_dmc_dram_info *priv = dev_get_priv(dev); 817 818 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); 819 820 if (IS_ENABLED(CONFIG_TPL_BUILD)) { 821 struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev); 822 struct regmap *map; 823 struct udevice *dev_clk; 824 int ret; 825 826 ret = rk3066_dmc_conv_of_plat(dev); 827 if (ret) 828 return ret; 829 830 map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); 831 if (IS_ERR(map)) 832 return PTR_ERR(map); 833 priv->chan[0].msch = regmap_get_range(map, 0); 834 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 835 836 priv->chan[0].pctl = regmap_get_range(plat->map, 0); 837 priv->chan[0].publ = regmap_get_range(plat->map, 1); 838 839 ret = rockchip_get_clk(&dev_clk); 840 if (ret) 841 return ret; 842 843 priv->ddr_clk.id = CLK_DDR; 844 ret = clk_request(dev_clk, &priv->ddr_clk); 845 if (ret) 846 return ret; 847 848 priv->cru = rockchip_get_cru(); 849 if (IS_ERR(priv->cru)) 850 return PTR_ERR(priv->cru); 851 852 ret = rk3066_dmc_setup_sdram(dev); 853 if (ret) 854 return ret; 855 } else { 856 priv->info.base = CFG_SYS_SDRAM_BASE; 857 priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]); 858 } 859 860 return 0; 861} 862 863static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info) 864{ 865 struct rk3066_dmc_dram_info *priv = dev_get_priv(dev); 866 867 *info = priv->info; 868 869 return 0; 870} 871 872static struct ram_ops rk3066_dmc_ops = { 873 .get_info = rk3066_dmc_get_info, 874}; 875 876static const struct udevice_id rk3066_dmc_ids[] = { 877 { .compatible = "rockchip,rk3066-dmc" }, 878 { } 879}; 880 881U_BOOT_DRIVER(rockchip_rk3066_dmc) = { 882 .name = "rockchip_rk3066_dmc", 883 .id = UCLASS_RAM, 884 .ops = &rk3066_dmc_ops, 885 .probe = rk3066_dmc_probe, 886 .of_match = rk3066_dmc_ids, 887 .priv_auto = sizeof(struct rk3066_dmc_dram_info), 888#if IS_ENABLED(CONFIG_TPL_BUILD) 889 .plat_auto = sizeof(struct rk3066_dmc_sdram_params), 890#endif 891}; 892