Lines Matching refs:DDR3
165 /* Set to DDR3 mode */
252 * "16.6.2 Initialization (DDR3 Initialization Sequence)"
463 pr_err("%s: unimplemented DDR3 speed bin %d\n",
507 /* The DDR3 mode-register does only support even values for tWR > 8. */
516 pctl_timing->tdqs = 1; /* fixed for DDR3 */
525 pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
534 tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
568 /* DDR3 */
783 sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
860 /* DDR3 is always 8 bank */