Searched refs:CSR_WRITE_2 (Results 1 - 25 of 41) sorted by relevance

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/haiku/src/add-ons/kernel/drivers/network/ether/rtl8139/
H A Dglue.c25 CSR_WRITE_2(sc, RL_ISR, status);
31 CSR_WRITE_2(sc, RL_IMR, 0);
41 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
/haiku/src/add-ons/kernel/drivers/network/ether/3com/
H A Dglue.c49 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB);
50 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | (status & XL_INTRS));
60 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS);
/haiku/src/add-ons/kernel/drivers/network/ether/rtl81xx/
H A Dglue.c48 CSR_WRITE_2(sc, RL_ISR, status);
54 CSR_WRITE_2(sc, RL_IMR, 0);
64 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
/haiku/src/add-ons/kernel/drivers/network/ether/3com/dev/xl/
H A Dif_xl.c411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
576 CSR_WRITE_2(sc, XL_W0_EE_CMD,
579 CSR_WRITE_2(sc, XL_W0_EE_CMD,
648 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
689 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
711 CSR_WRITE_2(sc, XL_COMMAND,
720 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
741 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
826 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
828 CSR_WRITE_2(s
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/haiku/src/add-ons/kernel/drivers/network/wlan/aironetwifi/
H A Dglue.c42 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
/haiku/src/add-ons/kernel/drivers/network/ether/rdc/dev/vte/
H A Dif_vte.c180 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
204 CSR_WRITE_2(sc, VTE_MMWD, val);
205 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
261 CSR_WRITE_2(sc, VTE_MRICR, val);
269 CSR_WRITE_2(sc, VTE_MTICR, val);
1161 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
1257 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1358 CSR_WRITE_2(sc, VTE_MIER, 0);
1379 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1578 CSR_WRITE_2(s
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H A Dif_vtevar.h151 #define CSR_WRITE_2(_sc, reg, val) \ macro
/haiku/src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/
H A Dbwimac.c219 CSR_WRITE_2(sc, data_reg, v);
232 CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
236 CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
280 CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
351 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
368 CSR_WRITE_2(sc, 0x60e, 0);
369 CSR_WRITE_2(sc, 0x610, 0x8000);
370 CSR_WRITE_2(sc, 0x604, 0);
371 CSR_WRITE_2(sc, 0x606, 0x200);
395 CSR_WRITE_2(s
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H A Dbwirf.c203 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
204 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
222 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
253 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
257 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
356 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
582 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
584 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
586 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
788 CSR_WRITE_2(s
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H A Dbwiphy.c141 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
142 CSR_WRITE_2(sc, BWI_PHY_DATA, data);
150 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
443 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
453 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
490 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);
537 CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);
561 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
569 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
723 CSR_WRITE_2(s
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H A Dif_bwivar.h84 #define CSR_WRITE_2(sc, reg, val) \ macro
90 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
95 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
100 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
/haiku/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/
H A Dif_an.c341 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
342 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), 0xFFFF);
1206 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
1209 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), ~AN_INTRS(sc->mpi350));
1212 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_MIC);
1221 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_LINKSTAT);
1226 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_RX);
1231 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX_CPY);
1236 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX);
1241 CSR_WRITE_2(s
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/haiku/src/add-ons/kernel/drivers/network/ether/vt612x/dev/vge/
H A Dif_vgevar.h221 #define CSR_WRITE_2(sc, reg, val) \ macro
236 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
243 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/haiku/src/add-ons/kernel/drivers/network/ether/via_rhine/dev/vr/
H A Dif_vr.c276 CSR_WRITE_2(sc, VR_MIIDATA, data);
731 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
732 CSR_WRITE_2(sc, VR_IMR, 0);
734 CSR_WRITE_2(sc, VR_MII_IMR, 0);
1610 CSR_WRITE_2(sc, VR_ISR, status);
1674 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1705 CSR_WRITE_2(sc, VR_IMR, 0);
1706 CSR_WRITE_2(sc, VR_ISR, status);
1711 CSR_WRITE_2(sc, VR_ISR, status);
1737 CSR_WRITE_2(s
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H A Dif_vrreg.h754 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val) macro
763 #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
764 #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/haiku/src/add-ons/kernel/drivers/network/ether/rtl8139/dev/rl/
H A Dif_rl.c470 CSR_WRITE_2(sc, rl8139_reg, data);
1217 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1328 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1331 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1474 CSR_WRITE_2(sc, RL_ISR, status);
1513 CSR_WRITE_2(sc, RL_IMR, 0);
1515 CSR_WRITE_2(sc, RL_ISR, status);
1539 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1751 CSR_WRITE_2(sc, RL_IMR, 0);
1755 CSR_WRITE_2(s
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/haiku/src/add-ons/kernel/drivers/network/ether/rtl81xx/dev/re/
H A Dif_re.c613 CSR_WRITE_2(sc, re8139_reg, data);
823 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
840 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
852 CSR_WRITE_2(sc, RL_ISR, status);
2542 CSR_WRITE_2(sc, RL_ISR, status);
2571 CSR_WRITE_2(sc, RL_IMR, 0);
2592 CSR_WRITE_2(sc, RL_ISR, status);
2645 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2666 CSR_WRITE_2(sc, RL_IMR, 0);
2674 CSR_WRITE_2(s
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/haiku/src/add-ons/kernel/drivers/network/ether/marvell_yukon/dev/msk/
H A Dif_msk.c689 CSR_WRITE_2(sc_if->msk_softc,
754 CSR_WRITE_2(sc_if->msk_softc,
822 CSR_WRITE_2(sc_if->msk_softc,
1296 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1310 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1312 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1369 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
1373 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1378 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1379 CSR_WRITE_2(s
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/haiku/src/add-ons/kernel/drivers/network/ether/ipro100/dev/fxp/
H A Dif_fxpvar.h253 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val) macro
H A Dif_fxp.c1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1153 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1173 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1187 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1189 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1191 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1206 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1210 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1213 CSR_WRITE_2(s
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/haiku/src/add-ons/kernel/drivers/network/wlan/iprowifi2100/dev/ipw/
H A Dif_ipwreg.h339 #define CSR_WRITE_2(sc, reg, val) \ macro
367 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
/haiku/src/add-ons/kernel/drivers/network/wlan/iprowifi2200/dev/iwi/
H A Dif_iwireg.h589 #define CSR_WRITE_2(sc, reg, val) \ macro
609 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/haiku/src/add-ons/kernel/drivers/network/ether/atheros813x/dev/alc/
H A Dif_alcvar.h264 #define CSR_WRITE_2(_sc, reg, val) \ macro
/haiku/src/add-ons/kernel/drivers/network/ether/atheros81xx/dev/ale/
H A Dif_alevar.h233 #define CSR_WRITE_2(_sc, reg, val) \ macro
/haiku/src/add-ons/kernel/drivers/network/ether/attansic_l1/dev/age/
H A Dif_agevar.h241 #define CSR_WRITE_2(_sc, reg, val) \ macro

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