Searched refs:AR_RC (Results 1 - 17 of 17) sorted by relevance

/freebsd-11-stable/sys/dev/ath/ath_hal/ar5416/
H A Dar5416_power.c99 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);
H A Dar5416_interrupts.c237 OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
238 OS_REG_WRITE(ah, AR_RC, 0);
H A Dar5416_reset.c1320 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
1328 OS_REG_WRITE(ah, AR_RC, 0);
1383 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);
1385 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
1412 OS_REG_WRITE(ah, AR_RC, 0);
/freebsd-11-stable/tools/tools/ath/common/
H A Ddumpregs_5210.c64 DEFBASICfmt(AR_RC, "RC", AR_RC_BITS),
H A Ddumpregs_5211.c223 DEFBASICfmt(AR_RC, "RC", AR_RC_BITS),
H A Ddumpregs_5212.c252 DEFBASIC(AR_RC, "RC"),
H A Ddumpregs_5416.c259 DEFBASICfmt(AR_RC, "RC",
/freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_interrupts.c436 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF);
437 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), 0);
H A Dar9300_reset.c1681 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF);
1686 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF);
1690 /*OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_AHB);*/
1852 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), 0);
H A Dar9300.h730 u_int32_t AR_RC; member in struct:ath_hal_9300::__anon8060
H A Dar9300_attach.c4101 AR_HOSTIF_REG(ah, AR_RC) =
4216 AR_HOSTIF_REG(ah, AR_RC) =
/freebsd-11-stable/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h53 #define AR_RC 0x4000 /* Reset control */ macro
H A Dar5210_reset.c47 * The delay, in usecs, between writing AR_RC with a reset
592 OS_REG_WRITE(ah, AR_RC, resetMask);
598 rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
969 OS_REG_READ(ah, AR_RC));
/freebsd-11-stable/sys/dev/ath/ath_hal/ar5211/
H A Dar5211_reset.c757 OS_REG_WRITE(ah, AR_RC, resetMask);
764 rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
H A Dar5211reg.h222 #define AR_RC 0x4000 /* Warm reset control register */ macro
/freebsd-11-stable/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h231 #define AR_RC 0x4000 /* Warm reset control register */ macro
H A Dar5212_reset.c1273 OS_REG_WRITE(ah, AR_RC, resetMask);
1278 rt = ath_hal_wait(ah, AR_RC, mask, resetMask);

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