1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian#include "opt_ah.h" 18250003Sadrian 19250003Sadrian#include "ah.h" 20250003Sadrian#include "ah_internal.h" 21250003Sadrian#include "ah_devid.h" 22250003Sadrian 23250003Sadrian#include "ar9300/ar9300desc.h" 24250003Sadrian#include "ar9300/ar9300.h" 25250003Sadrian#include "ar9300/ar9300reg.h" 26250003Sadrian#include "ar9300/ar9300phy.h" 27250003Sadrian#include "ar9300/ar9300paprd.h" 28250003Sadrian 29250008Sadrian#include "ar9300/ar9300_stub.h" 30250008Sadrian#include "ar9300/ar9300_stub_funcs.h" 31250003Sadrian 32250008Sadrian 33250003Sadrian/* Add static register initialization vectors */ 34250003Sadrian#include "ar9300/ar9300_osprey22.ini" 35250003Sadrian#include "ar9300/ar9330_11.ini" 36250003Sadrian#include "ar9300/ar9330_12.ini" 37250003Sadrian#include "ar9300/ar9340.ini" 38250003Sadrian#include "ar9300/ar9485.ini" 39250003Sadrian#include "ar9300/ar9485_1_1.ini" 40250003Sadrian#include "ar9300/ar9300_jupiter10.ini" 41301421Sadrian/* TODO: convert the 2.0 code to use the new initvals from ath9k */ 42250003Sadrian#include "ar9300/ar9300_jupiter20.ini" 43301421Sadrian#include "ar9300/ar9462_2p0_initvals.h" 44291433Sadrian#include "ar9300/ar9462_2p1_initvals.h" 45250003Sadrian#include "ar9300/ar9580.ini" 46250003Sadrian#include "ar9300/ar955x.ini" 47291437Sadrian#include "ar9300/ar953x.ini" 48250003Sadrian#include "ar9300/ar9300_aphrodite10.ini" 49250003Sadrian 50250003Sadrian 51250008Sadrian/* Include various freebsd specific HAL methods */ 52250008Sadrian#include "ar9300/ar9300_freebsd.h" 53250008Sadrian 54250008Sadrian/* XXX duplicate in ar9300_radio.c ? */ 55250003Sadrianstatic HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, 56250008Sadrian struct ieee80211_channel *chan); 57250003Sadrian 58250003Sadrianstatic inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); 59250003Sadrianstatic inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); 60250003Sadrianstatic inline void ar9300_hw_detach(struct ath_hal *ah); 61250003Sadrianstatic int16_t ar9300_get_nf_adjust(struct ath_hal *ah, 62250003Sadrian const HAL_CHANNEL_INTERNAL *c); 63250008Sadrian#if 0 64250003Sadrianint ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 65250003Sadrian HAL_CAL_QUERY query); 66250008Sadrian#endif 67250008Sadrian 68250003Sadrian#if ATH_TRAFFIC_FAST_RECOVER 69250003Sadrianunsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); 70250003Sadrian#endif 71250003Sadrianstatic int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid); 72250003Sadrian 73250003Sadrian 74250003Sadrianstatic void 75250003Sadrianar9300_disable_pcie_phy(struct ath_hal *ah); 76250003Sadrian 77250003Sadrianstatic const HAL_PERCAL_DATA iq_cal_single_sample = 78250003Sadrian {IQ_MISMATCH_CAL, 79250003Sadrian MIN_CAL_SAMPLES, 80250003Sadrian PER_MAX_LOG_COUNT, 81250003Sadrian ar9300_iq_cal_collect, 82250003Sadrian ar9300_iq_calibration}; 83250003Sadrian 84250008Sadrian#if 0 85250003Sadrianstatic HAL_CALIBRATION_TIMER ar9300_cals[] = 86250003Sadrian { {IQ_MISMATCH_CAL, /* Cal type */ 87250003Sadrian 1200000, /* Cal interval */ 88250003Sadrian 0 /* Cal timestamp */ 89250003Sadrian }, 90250003Sadrian {TEMP_COMP_CAL, 91250003Sadrian 5000, 92250003Sadrian 0 93250003Sadrian }, 94250003Sadrian }; 95250008Sadrian#endif 96250008Sadrian 97250003Sadrian#if ATH_PCIE_ERROR_MONITOR 98250003Sadrian 99250003Sadrianint ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) 100250003Sadrian{ 101250003Sadrian u_int32_t val; 102250003Sadrian 103250003Sadrian /* Clear the counters */ 104250003Sadrian OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0); 105250003Sadrian OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0); 106250003Sadrian 107250003Sadrian /* Read the previous value */ 108250003Sadrian val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 109250003Sadrian 110250003Sadrian /* Set auto_stop */ 111250003Sadrian if (b_auto_stop) { 112250003Sadrian val |= 113250003Sadrian RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 114250003Sadrian BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 115250003Sadrian RPLY_NUM_RO_ERR_CTR_AUTO_STOP; 116250003Sadrian } else { 117250003Sadrian val &= ~( 118250003Sadrian RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 119250003Sadrian BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 120250003Sadrian RPLY_NUM_RO_ERR_CTR_AUTO_STOP); 121250003Sadrian } 122250003Sadrian OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 123250003Sadrian 124250003Sadrian /* 125250003Sadrian * Start to run. 126250003Sadrian * This has to be done separately from the above auto_stop flag setting, 127250003Sadrian * to avoid a HW race condition. 128250003Sadrian */ 129250003Sadrian val |= 130250003Sadrian RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | 131250003Sadrian RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN; 132250003Sadrian OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val); 133250003Sadrian 134250003Sadrian return 0; 135250003Sadrian} 136250003Sadrian 137250003Sadrianint ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters) 138250003Sadrian{ 139250003Sadrian u_int32_t val; 140250003Sadrian ar_pcie_error_moniter_counters *p_counters = 141250003Sadrian (ar_pcie_error_moniter_counters*) p_read_counters; 142250003Sadrian 143250003Sadrian val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0); 144250003Sadrian 145250003Sadrian p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); 146250003Sadrian p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); 147250003Sadrian p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); 148250003Sadrian 149250003Sadrian val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1); 150250003Sadrian 151250003Sadrian p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); 152250003Sadrian p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); 153250003Sadrian 154250003Sadrian return 0; 155250003Sadrian} 156250003Sadrian 157250003Sadrianint ar9300_stop_pcie_error_monitor(struct ath_hal *ah) 158250003Sadrian{ 159250003Sadrian u_int32_t val; 160250003Sadrian 161250003Sadrian /* Read the previous value */ 162250003Sadrian val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 163250003Sadrian 164250003Sadrian val &= ~( 165250003Sadrian RCVD_ERR_CTR_RUN | 166250003Sadrian BAD_TLP_ERR_CTR_RUN | 167250003Sadrian BAD_DLLP_ERR_CTR_RUN | 168250003Sadrian RPLY_TO_ERR_CTR_RUN | 169250003Sadrian RPLY_NUM_RO_ERR_CTR_RUN); 170250003Sadrian 171250003Sadrian /* Start to stop */ 172250003Sadrian OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 173250003Sadrian 174250003Sadrian return 0; 175250003Sadrian} 176250003Sadrian 177250003Sadrian#endif /* ATH_PCIE_ERROR_MONITOR */ 178250003Sadrian 179250008Sadrian#if 0 180250003Sadrian/* WIN32 does not support C99 */ 181250003Sadrianstatic const struct ath_hal_private ar9300hal = { 182250003Sadrian { 183250003Sadrian ar9300_get_rate_table, /* ah_get_rate_table */ 184250003Sadrian ar9300_detach, /* ah_detach */ 185250003Sadrian 186250003Sadrian /* Reset Functions */ 187250003Sadrian ar9300_reset, /* ah_reset */ 188250003Sadrian ar9300_phy_disable, /* ah_phy_disable */ 189250003Sadrian ar9300_disable, /* ah_disable */ 190250003Sadrian ar9300_config_pci_power_save, /* ah_config_pci_power_save */ 191250003Sadrian ar9300_set_pcu_config, /* ah_set_pcu_config */ 192250003Sadrian ar9300_calibration, /* ah_per_calibration */ 193250003Sadrian ar9300_reset_cal_valid, /* ah_reset_cal_valid */ 194250003Sadrian ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */ 195250003Sadrian 196250003Sadrian#if ATH_ANT_DIV_COMB 197250003Sadrian ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */ 198250003Sadrian#endif /* ATH_ANT_DIV_COMB */ 199250003Sadrian#ifdef ATH_SUPPORT_DFS 200250003Sadrian ar9300_radar_wait, /* ah_radar_wait */ 201250003Sadrian 202250003Sadrian /* New DFS functions */ 203250003Sadrian ar9300_check_dfs, /* ah_ar_check_dfs */ 204250003Sadrian ar9300_dfs_found, /* ah_ar_dfs_found */ 205250003Sadrian ar9300_enable_dfs, /* ah_ar_enable_dfs */ 206250003Sadrian ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */ 207250003Sadrian ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */ 208250003Sadrian ar9300_adjust_difs, /* ah_adjust_difs */ 209250003Sadrian ar9300_dfs_config_fft, /* ah_dfs_config_fft */ 210250003Sadrian ar9300_dfs_cac_war, /* ah_dfs_cac_war */ 211250003Sadrian ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */ 212250003Sadrian#endif 213250003Sadrian ar9300_get_extension_channel, /* ah_get_extension_channel */ 214250003Sadrian ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */ 215250003Sadrian 216250003Sadrian /* Transmit functions */ 217250003Sadrian ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */ 218250003Sadrian ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */ 219250003Sadrian ar9300_setup_tx_queue, /* ah_setup_tx_queue */ 220250003Sadrian ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */ 221250003Sadrian ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */ 222250003Sadrian ar9300_release_tx_queue, /* ah_release_tx_queue */ 223250003Sadrian ar9300_reset_tx_queue, /* ah_reset_tx_queue */ 224250003Sadrian ar9300_get_tx_dp, /* ah_get_tx_dp */ 225250003Sadrian ar9300_set_tx_dp, /* ah_set_tx_dp */ 226250003Sadrian ar9300_num_tx_pending, /* ah_num_tx_pending */ 227250003Sadrian ar9300_start_tx_dma, /* ah_start_tx_dma */ 228250003Sadrian ar9300_stop_tx_dma, /* ah_stop_tx_dma */ 229250003Sadrian ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */ 230250003Sadrian ar9300_abort_tx_dma, /* ah_abort_tx_dma */ 231250003Sadrian ar9300_fill_tx_desc, /* ah_fill_tx_desc */ 232250003Sadrian ar9300_set_desc_link, /* ah_set_desc_link */ 233250003Sadrian ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */ 234250003Sadrian ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */ 235250003Sadrian#ifdef ATH_SWRETRY 236250003Sadrian ar9300_clear_dest_mask, /* ah_clear_dest_mask */ 237250003Sadrian#endif 238250003Sadrian ar9300_proc_tx_desc, /* ah_proc_tx_desc */ 239250003Sadrian ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */ 240250003Sadrian ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */ 241250003Sadrian AH_NULL, /* ah_get_tx_intr_queue */ 242250003Sadrian ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */ 243250003Sadrian ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */ 244250003Sadrian ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */ 245250003Sadrian 246250003Sadrian /* RX Functions */ 247250003Sadrian ar9300_get_rx_dp, /* ah_get_rx_dp */ 248250003Sadrian ar9300_set_rx_dp, /* ah_set_rx_dp */ 249250003Sadrian ar9300_enable_receive, /* ah_enable_receive */ 250250003Sadrian ar9300_stop_dma_receive, /* ah_stop_dma_receive */ 251250003Sadrian ar9300_start_pcu_receive, /* ah_start_pcu_receive */ 252250003Sadrian ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */ 253250003Sadrian ar9300_set_multicast_filter, /* ah_set_multicast_filter */ 254250003Sadrian ar9300_get_rx_filter, /* ah_get_rx_filter */ 255250003Sadrian ar9300_set_rx_filter, /* ah_set_rx_filter */ 256250003Sadrian ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */ 257250003Sadrian ar9300_set_rx_abort, /* ah_set_rx_abort */ 258250003Sadrian AH_NULL, /* ah_setup_rx_desc */ 259250003Sadrian ar9300_proc_rx_desc, /* ah_proc_rx_desc */ 260250003Sadrian ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */ 261250003Sadrian ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */ 262250003Sadrian ar9300_ani_ar_poll, /* ah_rx_monitor */ 263250003Sadrian ar9300_process_mib_intr, /* ah_proc_mib_event */ 264250003Sadrian 265250003Sadrian /* Misc Functions */ 266250003Sadrian ar9300_get_capability, /* ah_get_capability */ 267250003Sadrian ar9300_set_capability, /* ah_set_capability */ 268250003Sadrian ar9300_get_diag_state, /* ah_get_diag_state */ 269250003Sadrian ar9300_get_mac_address, /* ah_get_mac_address */ 270250003Sadrian ar9300_set_mac_address, /* ah_set_mac_address */ 271250003Sadrian ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */ 272250003Sadrian ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */ 273250003Sadrian ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */ 274250003Sadrian ar9300_set_led_state, /* ah_set_led_state */ 275250003Sadrian ar9300_set_power_led_state, /* ah_setpowerledstate */ 276250003Sadrian ar9300_set_network_led_state, /* ah_setnetworkledstate */ 277250003Sadrian ar9300_write_associd, /* ah_write_associd */ 278250003Sadrian ar9300_force_tsf_sync, /* ah_force_tsf_sync */ 279250003Sadrian ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */ 280250003Sadrian ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */ 281250003Sadrian ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */ 282250003Sadrian ar9300_gpio_get, /* ah_gpio_get */ 283250003Sadrian ar9300_gpio_set, /* ah_gpio_set */ 284250003Sadrian ar9300_gpio_get_intr, /* ah_gpio_get_intr */ 285250003Sadrian ar9300_gpio_set_intr, /* ah_gpio_set_intr */ 286250003Sadrian ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */ 287250003Sadrian ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */ 288250003Sadrian ar9300_gpio_get_mask, /* ah_gpio_get_mask */ 289250003Sadrian ar9300_gpio_set_mask, /* ah_gpio_set_mask */ 290250003Sadrian ar9300_get_tsf32, /* ah_get_tsf32 */ 291250003Sadrian ar9300_get_tsf64, /* ah_get_tsf64 */ 292250003Sadrian ar9300_get_tsf2_32, /* ah_get_tsf2_32 */ 293250003Sadrian ar9300_reset_tsf, /* ah_reset_tsf */ 294250003Sadrian ar9300_detect_card_present, /* ah_detect_card_present */ 295250003Sadrian ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */ 296250003Sadrian ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */ 297250003Sadrian ar9300_get_rfgain, /* ah_get_rf_gain */ 298250003Sadrian ar9300_get_def_antenna, /* ah_get_def_antenna */ 299250003Sadrian ar9300_set_def_antenna, /* ah_set_def_antenna */ 300250003Sadrian ar9300_set_slot_time, /* ah_set_slot_time */ 301250003Sadrian ar9300_set_ack_timeout, /* ah_set_ack_timeout */ 302250003Sadrian ar9300_get_ack_timeout, /* ah_get_ack_timeout */ 303250003Sadrian ar9300_set_coverage_class, /* ah_set_coverage_class */ 304250003Sadrian ar9300_set_quiet, /* ah_set_quiet */ 305250003Sadrian ar9300_set_antenna_switch, /* ah_set_antenna_switch */ 306250003Sadrian ar9300_get_desc_info, /* ah_get_desc_info */ 307250003Sadrian ar9300_select_ant_config, /* ah_select_ant_config */ 308250003Sadrian ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */ 309278741Sadrian ar9300_ant_swcom_sel, /* ah_ant_swcom_sel */ 310250003Sadrian ar9300_enable_tpc, /* ah_enable_tpc */ 311250003Sadrian AH_NULL, /* ah_olpc_temp_compensation */ 312250003Sadrian#if ATH_SUPPORT_CRDC 313250003Sadrian ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/ 314250003Sadrian#endif 315250003Sadrian ar9300_disable_phy_restart, /* ah_disable_phy_restart */ 316250003Sadrian ar9300_enable_keysearch_always, 317250003Sadrian ar9300_interference_is_present, /* ah_interference_is_present */ 318250003Sadrian ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */ 319250003Sadrian ar9300_get_tpc_tables, /* ah_get_tpc_tables */ 320250003Sadrian /* Key Cache Functions */ 321250003Sadrian ar9300_get_key_cache_size, /* ah_get_key_cache_size */ 322250003Sadrian ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */ 323250003Sadrian ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */ 324250003Sadrian ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */ 325250003Sadrian ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */ 326250003Sadrian ar9300_print_keycache, /* ah_print_key_cache */ 327278741Sadrian#if ATH_SUPPORT_KEYPLUMB_WAR 328278741Sadrian ar9300_check_key_cache_entry, /* ah_check_key_cache_entry */ 329278741Sadrian#endif 330250003Sadrian /* Power Management Functions */ 331250003Sadrian ar9300_set_power_mode, /* ah_set_power_mode */ 332250003Sadrian ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */ 333250003Sadrian#if ATH_WOW 334250003Sadrian ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */ 335250003Sadrian ar9300_wow_enable, /* ah_wow_enable */ 336250003Sadrian ar9300_wow_wake_up, /* ah_wow_wake_up */ 337250003Sadrian#if ATH_WOW_OFFLOAD 338250003Sadrian ar9300_wowoffload_prep, /* ah_wow_offload_prep */ 339250003Sadrian ar9300_wowoffload_post, /* ah_wow_offload_post */ 340250003Sadrian ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */ 341250003Sadrian ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */ 342250003Sadrian ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */ 343250003Sadrian ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */ 344250003Sadrian ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */ 345250003Sadrian ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */ 346250003Sadrian#endif /* ATH_WOW_OFFLOAD */ 347250003Sadrian#endif 348250003Sadrian 349250003Sadrian /* Get Channel Noise */ 350250003Sadrian ath_hal_get_chan_noise, /* ah_get_chan_noise */ 351250003Sadrian ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */ 352278741Sadrian ar9300_get_nf_from_reg, /* ah_get_nf_from_reg */ 353278741Sadrian ar9300_get_rx_nf_offset, /* ah_get_rx_nf_offset */ 354250003Sadrian 355250003Sadrian /* Beacon Functions */ 356250003Sadrian ar9300_beacon_init, /* ah_beacon_init */ 357250003Sadrian ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */ 358250003Sadrian 359250003Sadrian /* Interrupt Functions */ 360250003Sadrian ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */ 361250003Sadrian ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */ 362250003Sadrian ar9300_get_interrupts, /* ah_get_interrupts */ 363250003Sadrian ar9300_set_interrupts, /* ah_set_interrupts */ 364250003Sadrian ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */ 365250003Sadrian ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */ 366250003Sadrian ar9300ForceVCS, 367250003Sadrian ar9300SetDfs3StreamFix, 368250003Sadrian ar9300Get3StreamSignature, 369250003Sadrian 370250003Sadrian /* 11n specific functions (NOT applicable to ar9300) */ 371250003Sadrian ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */ 372250003Sadrian /* Update rxchain */ 373250003Sadrian ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/ 374250003Sadrian /*Updating locationing register */ 375250003Sadrian ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/ 376250003Sadrian /* Start PAPRD functions */ 377250003Sadrian ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */ 378250003Sadrian ar9300_paprd_init_table, /* ah_paprd_init_table */ 379250003Sadrian ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */ 380250003Sadrian ar9300_paprd_create_curve, /* ah_paprd_create_curve */ 381250003Sadrian ar9300_paprd_is_done, /* ah_paprd_is_done */ 382250003Sadrian ar9300_enable_paprd, /* ah_PAPRDEnable */ 383250003Sadrian ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */ 384250003Sadrian ar9300_is_tx_done, /* ah_is_tx_done */ 385250003Sadrian ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/ 386250003Sadrian ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */ 387250003Sadrian /* End PAPRD functions */ 388250003Sadrian ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */ 389250003Sadrian ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */ 390250003Sadrian ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */ 391250003Sadrian ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */ 392250003Sadrian ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */ 393250003Sadrian ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */ 394250003Sadrian ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */ 395250003Sadrian ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */ 396250003Sadrian ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */ 397250003Sadrian ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */ 398250003Sadrian ar9300_set_smart_antenna, /* ah_setSmartAntenna */ 399250003Sadrian ar9300_detect_bb_hang, /* ah_detect_bb_hang */ 400250003Sadrian ar9300_detect_mac_hang, /* ah_detect_mac_hang */ 401250003Sadrian ar9300_set_immunity, /* ah_immunity */ 402250003Sadrian ar9300_get_hw_hangs, /* ah_get_hang_types */ 403250003Sadrian ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */ 404250003Sadrian ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */ 405250003Sadrian ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */ 406250003Sadrian ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */ 407250003Sadrian ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */ 408250003Sadrian ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */ 409250003Sadrian ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */ 410250003Sadrian ar9300_dma_reg_dump, /* ah_dma_reg_dump */ 411250003Sadrian 412250003Sadrian /* force_ppm specific functions */ 413250003Sadrian ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */ 414250003Sadrian ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */ 415250003Sadrian ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */ 416250003Sadrian ar9300_ppm_force, /* ah_ppm_force */ 417250003Sadrian ar9300_ppm_un_force, /* ah_ppm_un_force */ 418250003Sadrian ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */ 419250003Sadrian 420250003Sadrian ar9300_get_spur_info, /* ah_get_spur_info */ 421250003Sadrian ar9300_set_spur_info, /* ah_get_spur_info */ 422250003Sadrian 423250003Sadrian ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */ 424250003Sadrian 425250003Sadrian ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */ 426250003Sadrian ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */ 427250003Sadrian 428250003Sadrian /* radio measurement specific functions */ 429250003Sadrian ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */ 430250003Sadrian ar9300_get_vow_stats, /* ah_get_vow_stats */ 431250003Sadrian ar9300_clear_mib_counters, /* ah_clear_mib_counters */ 432250003Sadrian#if ATH_GEN_RANDOMNESS 433250003Sadrian ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */ 434250003Sadrian#endif 435250003Sadrian#ifdef ATH_BT_COEX 436250003Sadrian /* Bluetooth Coexistence functions */ 437250003Sadrian ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */ 438250003Sadrian ar9300_bt_coex_config, /* ah_bt_coex_config */ 439250003Sadrian ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */ 440250003Sadrian ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */ 441250003Sadrian ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */ 442250003Sadrian ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */ 443250003Sadrian ar9300_bt_coex_disable, /* ah_bt_coex_disable */ 444250003Sadrian ar9300_bt_coex_enable, /* ah_bt_coex_enable */ 445250003Sadrian ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/ 446250003Sadrian ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/ 447250003Sadrian#endif 448250003Sadrian /* Generic Timer functions */ 449250003Sadrian ar9300_alloc_generic_timer, /* ah_gentimer_alloc */ 450250003Sadrian ar9300_free_generic_timer, /* ah_gentimer_free */ 451250003Sadrian ar9300_start_generic_timer, /* ah_gentimer_start */ 452250003Sadrian ar9300_stop_generic_timer, /* ah_gentimer_stop */ 453250003Sadrian ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */ 454250003Sadrian 455250003Sadrian ar9300_set_dcs_mode, /* ah_set_dcs_mode */ 456250003Sadrian ar9300_get_dcs_mode, /* ah_get_dcs_mode */ 457250003Sadrian 458250003Sadrian#if ATH_ANT_DIV_COMB 459250003Sadrian ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */ 460250003Sadrian ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */ 461250003Sadrian#endif 462250003Sadrian 463250003Sadrian ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */ 464250003Sadrian ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */ 465250003Sadrian ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */ 466250003Sadrian 467250003Sadrian#if ATH_PCIE_ERROR_MONITOR 468250003Sadrian ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */ 469250003Sadrian ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/ 470250003Sadrian ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/ 471250003Sadrian#endif /* ATH_PCIE_ERROR_MONITOR */ 472250003Sadrian 473250003Sadrian#if ATH_SUPPORT_SPECTRAL 474250003Sadrian /* Spectral scan */ 475250003Sadrian ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */ 476250003Sadrian ar9300_get_spectral_params, /* ah_ar_get_spectral_config */ 477250003Sadrian ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */ 478250003Sadrian ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */ 479250003Sadrian ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */ 480250003Sadrian ar9300_is_spectral_active, /* ah_ar_is_spectral_active */ 481250003Sadrian ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */ 482250003Sadrian ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */ 483250003Sadrian#endif /* ATH_SUPPORT_SPECTRAL */ 484250003Sadrian 485250003Sadrian 486250003Sadrian ar9300_promisc_mode, /* ah_promisc_mode */ 487250003Sadrian ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */ 488250003Sadrian ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */ 489250003Sadrian ar9300_set_proxy_sta, /* ah_set_proxy_sta */ 490250003Sadrian ar9300_get_cal_intervals, /* ah_get_cal_intervals */ 491250003Sadrian#if ATH_TRAFFIC_FAST_RECOVER 492250003Sadrian ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */ 493250003Sadrian#endif 494250003Sadrian#ifdef ATH_SUPPORT_HTC 495250003Sadrian AH_NULL, 496250003Sadrian#endif 497250003Sadrian 498250003Sadrian#ifdef ATH_TX99_DIAG 499250003Sadrian /* Tx99 functions */ 500250003Sadrian#ifdef ATH_SUPPORT_HTC 501250003Sadrian AH_NULL, 502250003Sadrian AH_NULL, 503250003Sadrian AH_NULL, 504250003Sadrian AH_NULL, 505250003Sadrian AH_NULL, 506250003Sadrian AH_NULL, 507250003Sadrian AH_NULL, 508250003Sadrian#else 509250003Sadrian AH_NULL, 510250003Sadrian AH_NULL, 511278741Sadrian ar9300_tx99_channel_pwr_update, /* ah_tx99channelpwrupdate */ 512278741Sadrian ar9300_tx99_start, /* ah_tx99start */ 513278741Sadrian ar9300_tx99_stop, /* ah_tx99stop */ 514278741Sadrian ar9300_tx99_chainmsk_setup, /* ah_tx99_chainmsk_setup */ 515278741Sadrian ar9300_tx99_set_single_carrier, /* ah_tx99_set_single_carrier */ 516250003Sadrian#endif 517250003Sadrian#endif 518250003Sadrian ar9300_chk_rssi_update_tx_pwr, 519250003Sadrian ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */ 520250003Sadrian ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */ 521250003Sadrian#if ATH_SUPPORT_MCI 522250003Sadrian /* MCI Coexistence Functions */ 523250003Sadrian ar9300_mci_setup, /* ah_mci_setup */ 524250003Sadrian ar9300_mci_send_message, /* ah_mci_send_message */ 525250003Sadrian ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */ 526250003Sadrian ar9300_mci_state, /* ah_mci_state */ 527250003Sadrian ar9300_mci_detach, /* ah_mci_detach */ 528250003Sadrian#endif 529250003Sadrian ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */ 530250003Sadrian ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */ 531250003Sadrian ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/ 532250003Sadrian ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */ 533250003Sadrian ar9300_mat_enable, /* ah_mat_enable */ 534250003Sadrian ar9300_dump_keycache, /* ah_dump_keycache */ 535250003Sadrian ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */ 536250003Sadrian ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */ 537278741Sadrian ar9300_set_ctl_pwr, /* ah_set_ctl_pwr */ 538278741Sadrian ar9300_set_txchainmaskopt, /* ah_set_txchainmaskopt */ 539250003Sadrian }, 540250003Sadrian 541250003Sadrian ar9300_get_channel_edges, /* ah_get_channel_edges */ 542250003Sadrian ar9300_get_wireless_modes, /* ah_get_wireless_modes */ 543250003Sadrian ar9300_eeprom_read_word, /* ah_eeprom_read */ 544250003Sadrian AH_NULL, 545250003Sadrian ar9300_eeprom_dump_support, /* ah_eeprom_dump */ 546250003Sadrian ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */ 547250003Sadrian 548250003Sadrian ar9300_get_nf_adjust, /* ah_get_nf_adjust */ 549250003Sadrian /* rest is zero'd by compiler */ 550250003Sadrian}; 551250008Sadrian#endif 552250003Sadrian 553250003Sadrian/* 554250003Sadrian * Read MAC version/revision information from Chip registers and initialize 555250003Sadrian * local data structures. 556250003Sadrian */ 557250003Sadrianvoid 558250003Sadrianar9300_read_revisions(struct ath_hal *ah) 559250003Sadrian{ 560250003Sadrian u_int32_t val; 561250003Sadrian 562250003Sadrian /* XXX verify if this is the correct way to read revision on Osprey */ 563250003Sadrian /* new SREV format for Sowl and later */ 564250003Sadrian val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 565250003Sadrian 566250003Sadrian if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { 567250003Sadrian /* XXX: AR_SREV register in Wasp reads 0 */ 568250003Sadrian AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; 569250008Sadrian } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { 570250003Sadrian /* XXX: AR_SREV register in Scorpion reads 0 */ 571250003Sadrian AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; 572291437Sadrian } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA953X) { 573291437Sadrian /* XXX: AR_SREV register in HoneyBEE reads 0 */ 574291437Sadrian AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_HONEYBEE; 575250003Sadrian } else { 576250003Sadrian /* 577250003Sadrian * Include 6-bit Chip Type (masked to 0) 578250003Sadrian * to differentiate from pre-Sowl versions 579250003Sadrian */ 580250003Sadrian AH_PRIVATE(ah)->ah_macVersion = 581250003Sadrian (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 582250003Sadrian } 583250003Sadrian 584250003Sadrian 585250003Sadrian 586250003Sadrian 587250003Sadrian 588250003Sadrian#ifdef AH_SUPPORT_HORNET 589250003Sadrian /* 590250003Sadrian * EV74984, due to Hornet 1.1 didn't update WMAC revision, 591250003Sadrian * so that have to read SoC's revision ID instead 592250003Sadrian */ 593250003Sadrian if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) { 594250003Sadrian#define AR_SOC_RST_REVISION_ID 0xB8060090 595250003Sadrian#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 596250003Sadrian if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) 597250003Sadrian == AR_SREV_REVISION_HORNET_11) 598250003Sadrian { 599250003Sadrian AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11; 600250003Sadrian } else { 601250003Sadrian AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 602250003Sadrian } 603250003Sadrian#undef REG_READ 604250003Sadrian#undef AR_SOC_RST_REVISION_ID 605250003Sadrian } else 606250003Sadrian#endif 607250003Sadrian if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP) 608250003Sadrian { 609250003Sadrian#define AR_SOC_RST_REVISION_ID 0xB8060090 610250003Sadrian#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 611250003Sadrian 612250003Sadrian AH_PRIVATE(ah)->ah_macRev = 613250003Sadrian REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; 614250003Sadrian#undef REG_READ 615250003Sadrian#undef AR_SOC_RST_REVISION_ID 616250003Sadrian } 617250003Sadrian else 618250003Sadrian AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 619250003Sadrian 620250003Sadrian if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 621250008Sadrian AH_PRIVATE(ah)->ah_ispcie = AH_TRUE; 622250003Sadrian } 623250003Sadrian else { 624250008Sadrian AH_PRIVATE(ah)->ah_ispcie = 625250003Sadrian (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 626250003Sadrian } 627250003Sadrian 628250003Sadrian} 629250003Sadrian 630250003Sadrian/* 631250003Sadrian * Attach for an AR9300 part. 632250003Sadrian */ 633250003Sadrianstruct ath_hal * 634250008Sadrianar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, 635272292Sadrian HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, 636272292Sadrian HAL_STATUS *status) 637250003Sadrian{ 638250003Sadrian struct ath_hal_9300 *ahp; 639250003Sadrian struct ath_hal *ah; 640250003Sadrian struct ath_hal_private *ahpriv; 641250003Sadrian HAL_STATUS ecode; 642250003Sadrian 643250008Sadrian HAL_NO_INTERSPERSED_READS; 644250003Sadrian 645250003Sadrian /* NB: memory is returned zero'd */ 646272292Sadrian ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, ah_config, status); 647250003Sadrian if (ahp == AH_NULL) { 648250003Sadrian return AH_NULL; 649250003Sadrian } 650250008Sadrian ah = &ahp->ah_priv.h; 651250003Sadrian ar9300_init_offsets(ah, devid); 652250003Sadrian ahpriv = AH_PRIVATE(ah); 653250008Sadrian// AH_PRIVATE(ah)->ah_bustype = bustype; 654250003Sadrian 655250008Sadrian /* FreeBSD: to make OTP work for now, provide this.. */ 656250008Sadrian AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE); 657252381Sadrian if (AH9300(ah)->ah_cal_mem == NULL) { 658252381Sadrian ath_hal_printf(ah, "%s: caldata malloc failed!\n", __func__); 659252381Sadrian ecode = HAL_EIO; 660252381Sadrian goto bad; 661252381Sadrian } 662250003Sadrian 663252238Sadrian /* 664252238Sadrian * If eepromdata is not NULL, copy it it into ah_cal_mem. 665252238Sadrian */ 666252238Sadrian if (eepromdata != NULL) 667252238Sadrian OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE); 668252238Sadrian 669250008Sadrian /* XXX FreeBSD: enable RX mitigation */ 670250008Sadrian ah->ah_config.ath_hal_intr_mitigation_rx = 1; 671250008Sadrian 672250003Sadrian /* interrupt mitigation */ 673250003Sadrian#ifdef AR5416_INT_MITIGATION 674250008Sadrian if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) { 675250003Sadrian ahp->ah_intr_mitigation_rx = AH_TRUE; 676250003Sadrian } 677250003Sadrian#else 678250003Sadrian /* Enable Rx mitigation (default) */ 679250003Sadrian ahp->ah_intr_mitigation_rx = AH_TRUE; 680250008Sadrian ah->ah_config.ath_hal_intr_mitigation_rx = 1; 681250003Sadrian 682250003Sadrian#endif 683250003Sadrian#ifdef HOST_OFFLOAD 684250003Sadrian /* Reset default Rx mitigation values for Hornet */ 685250003Sadrian if (AR_SREV_HORNET(ah)) { 686250003Sadrian ahp->ah_intr_mitigation_rx = AH_FALSE; 687250003Sadrian#ifdef AR5416_INT_MITIGATION 688250008Sadrian ah->ah_config.ath_hal_intr_mitigation_rx = 0; 689250003Sadrian#endif 690250003Sadrian } 691250003Sadrian#endif 692250003Sadrian 693250008Sadrian if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) { 694250003Sadrian ahp->ah_intr_mitigation_tx = AH_TRUE; 695250003Sadrian } 696250003Sadrian 697250003Sadrian /* 698250003Sadrian * Read back AR_WA into a permanent copy and set bits 14 and 17. 699250003Sadrian * We need to do this to avoid RMW of this register. 700250003Sadrian * Do this before calling ar9300_set_reset_reg. 701250003Sadrian * If not, the AR_WA register which was inited via EEPROM 702250003Sadrian * will get wiped out. 703250003Sadrian */ 704250003Sadrian ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); 705250003Sadrian /* Set Bits 14 and 17 in the AR_WA register. */ 706250003Sadrian ahp->ah_wa_reg_val |= 707250003Sadrian AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE; 708250003Sadrian 709250003Sadrian if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */ 710250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__); 711250003Sadrian ecode = HAL_EIO; 712250003Sadrian goto bad; 713250003Sadrian } 714250003Sadrian 715250003Sadrian if (AR_SREV_JUPITER(ah) 716250003Sadrian#if ATH_WOW_OFFLOAD 717250003Sadrian && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14) 718250003Sadrian#endif 719250003Sadrian ) 720250003Sadrian { 721250003Sadrian /* Jupiter doesn't need bit 14 to be set. */ 722250003Sadrian ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE; 723250003Sadrian OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 724250003Sadrian } 725250003Sadrian 726250003Sadrian#if ATH_SUPPORT_MCI 727250003Sadrian if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 728301012Sadrian#if 1 729301012Sadrian ah->ah_btCoexSetWeights = ar9300_mci_bt_coex_set_weights; 730301012Sadrian ah->ah_btCoexDisable = ar9300_mci_bt_coex_disable; 731301012Sadrian ah->ah_btCoexEnable = ar9300_mci_bt_coex_enable; 732250008Sadrian#endif 733250003Sadrian ahp->ah_mci_ready = AH_FALSE; 734250003Sadrian ahp->ah_mci_bt_state = MCI_BT_SLEEP; 735250003Sadrian ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; 736250003Sadrian ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN; 737250003Sadrian ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT; 738250003Sadrian ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT; 739250003Sadrian ahp->ah_mci_coex_bt_version_known = AH_FALSE; 740250003Sadrian ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */ 741250003Sadrian /* will be updated before boot up sequence */ 742250003Sadrian ahp->ah_mci_coex_is_2g = AH_TRUE; 743250003Sadrian ahp->ah_mci_coex_wlan_channels_update = AH_FALSE; 744250003Sadrian ahp->ah_mci_coex_wlan_channels[0] = 0x00000000; 745250003Sadrian ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff; 746250003Sadrian ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff; 747250003Sadrian ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff; 748250003Sadrian ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */ 749250003Sadrian ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */ 750250003Sadrian ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */ 751250003Sadrian ahp->ah_mci_need_flush_btinfo = AH_FALSE; 752250003Sadrian ahp->ah_mci_wlan_cal_seq = 0; 753250003Sadrian ahp->ah_mci_wlan_cal_done = 0; 754250003Sadrian } 755250003Sadrian#endif /* ATH_SUPPORT_MCI */ 756250003Sadrian 757250003Sadrian#if ATH_WOW_OFFLOAD 758250003Sadrian ahp->ah_mcast_filter_l32_set = 0; 759250003Sadrian ahp->ah_mcast_filter_u32_set = 0; 760250003Sadrian#endif 761250003Sadrian 762250003Sadrian if (AR_SREV_HORNET(ah)) { 763250003Sadrian#ifdef AH_SUPPORT_HORNET 764250003Sadrian if (!AR_SREV_HORNET_11(ah)) { 765250003Sadrian /* 766250003Sadrian * Do not check bootstrap register, which cannot be trusted 767250003Sadrian * due to s26 switch issue on CUS164/AP121. 768250003Sadrian */ 769250003Sadrian ahp->clk_25mhz = 1; 770250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 771250003Sadrian } else { 772250003Sadrian /* check bootstrap clock setting */ 773250003Sadrian#define AR_SOC_SEL_25M_40M 0xB80600AC 774250003Sadrian#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); 775250003Sadrian#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 776250003Sadrian if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { 777250003Sadrian ahp->clk_25mhz = 0; 778250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 779250003Sadrian "Bootstrap clock 40MHz\n"); 780250003Sadrian } else { 781250003Sadrian ahp->clk_25mhz = 1; 782250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 783250003Sadrian "Bootstrap clock 25MHz\n"); 784250003Sadrian } 785250003Sadrian#undef REG_READ 786250003Sadrian#undef REG_WRITE 787250003Sadrian#undef AR_SOC_SEL_25M_40M 788250003Sadrian } 789250003Sadrian#endif /* AH_SUPPORT_HORNET */ 790250003Sadrian } 791250003Sadrian 792250003Sadrian if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 793250003Sadrian /* check bootstrap clock setting */ 794250003Sadrian#define AR9340_SOC_SEL_25M_40M 0xB80600B0 795250003Sadrian#define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ 796250003Sadrian#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 797250003Sadrian if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) { 798250003Sadrian ahp->clk_25mhz = 0; 799250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); 800250003Sadrian } else { 801250003Sadrian ahp->clk_25mhz = 1; 802250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 803250003Sadrian } 804250003Sadrian#undef REG_READ 805250003Sadrian#undef AR9340_SOC_SEL_25M_40M 806250003Sadrian#undef AR9340_REF_CLK_40 807250003Sadrian } 808291437Sadrian 809291437Sadrian if (AR_SREV_HONEYBEE(ah)) { 810291437Sadrian ahp->clk_25mhz = 1; 811291437Sadrian } 812291437Sadrian 813250003Sadrian ar9300_init_pll(ah, AH_NULL); 814250003Sadrian 815250003Sadrian if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 816250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__); 817250003Sadrian ecode = HAL_EIO; 818250003Sadrian goto bad; 819250003Sadrian } 820250003Sadrian 821250003Sadrian /* No serialization of Register Accesses needed. */ 822250008Sadrian ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF; 823250008Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n", 824250008Sadrian __func__, ah->ah_config.ah_serialise_reg_war); 825250003Sadrian 826250003Sadrian /* 827250003Sadrian * Add mac revision check when needed. 828250003Sadrian * - Osprey 1.0 and 2.0 no longer supported. 829250003Sadrian */ 830250003Sadrian if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) && 831250003Sadrian (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) || 832250003Sadrian (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY && 833250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_WASP && 834250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET && 835250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON && 836250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION && 837291437Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_HONEYBEE && 838250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER && 839250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) { 840250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 841250003Sadrian "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 842250003Sadrian __func__, 843250003Sadrian ahpriv->ah_macVersion, 844250003Sadrian ahpriv->ah_macRev); 845250003Sadrian ecode = HAL_ENOTSUPP; 846250003Sadrian goto bad; 847250003Sadrian } 848250003Sadrian 849250008Sadrian AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 850250003Sadrian 851250003Sadrian /* Setup supported calibrations */ 852250003Sadrian ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; 853250003Sadrian ahp->ah_supp_cals = IQ_MISMATCH_CAL; 854250003Sadrian 855250003Sadrian /* Enable ANI */ 856250003Sadrian ahp->ah_ani_function = HAL_ANI_ALL; 857250003Sadrian 858250003Sadrian /* Enable RIFS */ 859250003Sadrian ahp->ah_rifs_enabled = AH_TRUE; 860250003Sadrian 861278741Sadrian /* by default, stop RX also in abort txdma, due to 862278741Sadrian "Unable to stop TxDMA" msg observed */ 863278741Sadrian ahp->ah_abort_txdma_norx = AH_TRUE; 864278741Sadrian 865278741Sadrian /* do not use optional tx chainmask by default */ 866278741Sadrian ahp->ah_tx_chainmaskopt = 0; 867278741Sadrian 868278741Sadrian ahp->ah_skip_rx_iq_cal = AH_FALSE; 869278741Sadrian ahp->ah_rx_cal_complete = AH_FALSE; 870278741Sadrian ahp->ah_rx_cal_chan = 0; 871278741Sadrian ahp->ah_rx_cal_chan_flag = 0; 872278741Sadrian 873250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 874250003Sadrian "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 875250003Sadrian ahpriv->ah_macVersion, 876250003Sadrian ahpriv->ah_macRev); 877250003Sadrian 878250003Sadrian if (AR_SREV_HORNET_12(ah)) { 879250003Sadrian /* mac */ 880250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 881250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 882250003Sadrian ar9331_hornet1_2_mac_core, 883250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2); 884250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 885250003Sadrian ar9331_hornet1_2_mac_postamble, 886250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5); 887250003Sadrian 888250003Sadrian /* bb */ 889250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 890250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 891250003Sadrian ar9331_hornet1_2_baseband_core, 892250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2); 893250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 894250003Sadrian ar9331_hornet1_2_baseband_postamble, 895250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5); 896250003Sadrian 897250003Sadrian /* radio */ 898250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 899250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 900250003Sadrian ar9331_hornet1_2_radio_core, 901250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2); 902250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 903250003Sadrian 904250003Sadrian /* soc */ 905250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 906250003Sadrian ar9331_hornet1_2_soc_preamble, 907250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2); 908250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 909250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 910250003Sadrian ar9331_hornet1_2_soc_postamble, 911250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2); 912250003Sadrian 913250003Sadrian /* rx/tx gain */ 914250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 915250003Sadrian ar9331_common_rx_gain_hornet1_2, 916250003Sadrian ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 917250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 918250003Sadrian ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 919250003Sadrian ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 920250003Sadrian 921250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 922250003Sadrian 923250003Sadrian /* Japan 2484Mhz CCK settings */ 924250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 925250003Sadrian ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484, 926250003Sadrian ARRAY_LENGTH( 927250003Sadrian ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2); 928250003Sadrian 929250003Sadrian#if 0 /* ATH_WOW */ 930250003Sadrian /* SerDes values during WOW sleep */ 931250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 932250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 933250003Sadrian#endif 934250003Sadrian 935250003Sadrian /* additional clock settings */ 936250003Sadrian if (AH9300(ah)->clk_25mhz) { 937250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 938250003Sadrian ar9331_hornet1_2_xtal_25M, 939250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2); 940250003Sadrian } else { 941250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 942250003Sadrian ar9331_hornet1_2_xtal_40M, 943250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2); 944250003Sadrian } 945250003Sadrian 946250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 947250003Sadrian /* mac */ 948250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 949250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 950250003Sadrian ar9331_hornet1_1_mac_core, 951250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2); 952250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 953250003Sadrian ar9331_hornet1_1_mac_postamble, 954250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5); 955250003Sadrian 956250003Sadrian /* bb */ 957250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 958250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 959250003Sadrian ar9331_hornet1_1_baseband_core, 960250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2); 961250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 962250003Sadrian ar9331_hornet1_1_baseband_postamble, 963250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5); 964250003Sadrian 965250003Sadrian /* radio */ 966250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 967250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 968250003Sadrian ar9331_hornet1_1_radio_core, 969250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2); 970250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 971250003Sadrian 972250003Sadrian /* soc */ 973250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 974250003Sadrian ar9331_hornet1_1_soc_preamble, 975250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2); 976250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 977250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 978250003Sadrian ar9331_hornet1_1_soc_postamble, 979250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2); 980250003Sadrian 981250003Sadrian /* rx/tx gain */ 982250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 983250003Sadrian ar9331_common_rx_gain_hornet1_1, 984250003Sadrian ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 985250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 986250003Sadrian ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 987250003Sadrian ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 988250003Sadrian 989250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 990250003Sadrian 991250003Sadrian /* Japan 2484Mhz CCK settings */ 992250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 993250003Sadrian ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484, 994250003Sadrian ARRAY_LENGTH( 995250003Sadrian ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2); 996250003Sadrian 997250003Sadrian#if 0 /* ATH_WOW */ 998250003Sadrian /* SerDes values during WOW sleep */ 999250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1000250003Sadrian N(ar9300_pcie_phy_awow), 2); 1001250003Sadrian#endif 1002250003Sadrian 1003250003Sadrian /* additional clock settings */ 1004250003Sadrian if (AH9300(ah)->clk_25mhz) { 1005250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1006250003Sadrian ar9331_hornet1_1_xtal_25M, 1007250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2); 1008250003Sadrian } else { 1009250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1010250003Sadrian ar9331_hornet1_1_xtal_40M, 1011250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2); 1012250003Sadrian } 1013250003Sadrian 1014250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 1015250003Sadrian /* mac */ 1016250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1017250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1018250003Sadrian ar9485_poseidon1_1_mac_core, 1019250003Sadrian ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2); 1020250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1021250003Sadrian ar9485_poseidon1_1_mac_postamble, 1022250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5); 1023250003Sadrian 1024250003Sadrian /* bb */ 1025250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1026250003Sadrian ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2); 1027250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1028250003Sadrian ar9485_poseidon1_1_baseband_core, 1029250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2); 1030250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1031250003Sadrian ar9485_poseidon1_1_baseband_postamble, 1032250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5); 1033250003Sadrian 1034250003Sadrian /* radio */ 1035250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1036250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1037250003Sadrian ar9485_poseidon1_1_radio_core, 1038250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2); 1039250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1040250003Sadrian ar9485_poseidon1_1_radio_postamble, 1041250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2); 1042250003Sadrian 1043250003Sadrian /* soc */ 1044250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1045250003Sadrian ar9485_poseidon1_1_soc_preamble, 1046250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2); 1047250003Sadrian 1048250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1049250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1050250003Sadrian 1051250003Sadrian /* rx/tx gain */ 1052250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1053250003Sadrian ar9485_common_wo_xlna_rx_gain_poseidon1_1, 1054250003Sadrian ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 1055250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1056250003Sadrian ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 1057250003Sadrian ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 1058250003Sadrian 1059250003Sadrian /* Japan 2484Mhz CCK settings */ 1060250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1061250003Sadrian ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484, 1062250003Sadrian ARRAY_LENGTH( 1063250003Sadrian ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); 1064250003Sadrian 1065250003Sadrian /* Load PCIE SERDES settings from INI */ 1066250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1067250003Sadrian /* Pci-e Clock Request = 1 */ 1068250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save 1069250003Sadrian & AR_PCIE_PLL_PWRSAVE_CONTROL) 1070250003Sadrian { 1071250003Sadrian /* Sleep Setting */ 1072250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1073250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1074250003Sadrian { 1075250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1076250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1077250003Sadrian ARRAY_LENGTH( 1078250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1079250003Sadrian 2); 1080250003Sadrian } else { 1081250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1082250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1083250003Sadrian ARRAY_LENGTH( 1084250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1085250003Sadrian 2); 1086250003Sadrian } 1087250003Sadrian /* Awake Setting */ 1088250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1089250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1090250003Sadrian { 1091250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1092250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1093250003Sadrian ARRAY_LENGTH( 1094250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1095250003Sadrian 2); 1096250003Sadrian } else { 1097250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1098250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1099250003Sadrian ARRAY_LENGTH( 1100250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1101250003Sadrian 2); 1102250003Sadrian } 1103250003Sadrian 1104250003Sadrian } else { 1105250003Sadrian /*Use driver default setting*/ 1106250003Sadrian /* Sleep Setting */ 1107250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1108250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1109250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1110250003Sadrian 2); 1111250003Sadrian /* Awake Setting */ 1112250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1113250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1114250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1115250003Sadrian 2); 1116250003Sadrian } 1117250003Sadrian } else { 1118250003Sadrian /* Pci-e Clock Request = 0 */ 1119250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save 1120250003Sadrian & AR_PCIE_PLL_PWRSAVE_CONTROL) 1121250003Sadrian { 1122250003Sadrian /* Sleep Setting */ 1123250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1124250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1125250003Sadrian { 1126250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1127250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1128250003Sadrian ARRAY_LENGTH( 1129250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1130250003Sadrian 2); 1131250003Sadrian } else { 1132250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1133250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1134250003Sadrian ARRAY_LENGTH( 1135250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1136250003Sadrian 2); 1137250003Sadrian } 1138250003Sadrian /* Awake Setting */ 1139250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1140250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1141250003Sadrian { 1142250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1143250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1144250003Sadrian ARRAY_LENGTH( 1145250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1146250003Sadrian 2); 1147250003Sadrian } else { 1148250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1149250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1150250003Sadrian ARRAY_LENGTH( 1151250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1152250003Sadrian 2); 1153250003Sadrian } 1154250003Sadrian 1155250003Sadrian } else { 1156250003Sadrian /*Use driver default setting*/ 1157250003Sadrian /* Sleep Setting */ 1158250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1159250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1160250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1161250003Sadrian 2); 1162250003Sadrian /* Awake Setting */ 1163250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1164250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1165250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1166250003Sadrian 2); 1167250003Sadrian } 1168250003Sadrian } 1169250003Sadrian /* pcie ps setting will honor registry setting, default is 0 */ 1170250008Sadrian //ah->ah_config.ath_hal_pciePowerSaveEnable = 0; 1171250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 1172250003Sadrian /* mac */ 1173250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1174250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1175250003Sadrian ar9485_poseidon1_0_mac_core, 1176250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2); 1177250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1178250003Sadrian ar9485_poseidon1_0_mac_postamble, 1179250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5); 1180250003Sadrian 1181250003Sadrian /* bb */ 1182250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1183250003Sadrian ar9485_poseidon1_0, 1184250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0), 2); 1185250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1186250003Sadrian ar9485_poseidon1_0_baseband_core, 1187250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2); 1188250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1189250003Sadrian ar9485_poseidon1_0_baseband_postamble, 1190250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5); 1191250003Sadrian 1192250003Sadrian /* radio */ 1193250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1194250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1195250003Sadrian ar9485_poseidon1_0_radio_core, 1196250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2); 1197250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1198250003Sadrian ar9485_poseidon1_0_radio_postamble, 1199250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2); 1200250003Sadrian 1201250003Sadrian /* soc */ 1202250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1203250003Sadrian ar9485_poseidon1_0_soc_preamble, 1204250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2); 1205250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1206250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1207250003Sadrian 1208250003Sadrian /* rx/tx gain */ 1209250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1210250003Sadrian ar9485Common_wo_xlna_rx_gain_poseidon1_0, 1211250003Sadrian ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 1212250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1213250003Sadrian ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 1214250003Sadrian ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 1215250003Sadrian 1216250003Sadrian /* Japan 2484Mhz CCK settings */ 1217250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1218250003Sadrian ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484, 1219250003Sadrian ARRAY_LENGTH( 1220250003Sadrian ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); 1221250003Sadrian 1222250003Sadrian /* Load PCIE SERDES settings from INI */ 1223250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1224250003Sadrian /* Pci-e Clock Request = 1 */ 1225250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save 1226250003Sadrian & AR_PCIE_PLL_PWRSAVE_CONTROL) 1227250003Sadrian { 1228250003Sadrian /* Sleep Setting */ 1229250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1230250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1231250003Sadrian { 1232250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1233250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1234250003Sadrian ARRAY_LENGTH( 1235250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1236250003Sadrian 2); 1237250003Sadrian } else { 1238250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1239250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1240250003Sadrian ARRAY_LENGTH( 1241250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1242250003Sadrian 2); 1243250003Sadrian } 1244250003Sadrian /* Awake Setting */ 1245250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1246250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1247250003Sadrian { 1248250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1249250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1250250003Sadrian ARRAY_LENGTH( 1251250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1252250003Sadrian 2); 1253250003Sadrian } else { 1254250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1255250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1256250003Sadrian ARRAY_LENGTH( 1257250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1258250003Sadrian 2); 1259250003Sadrian } 1260250003Sadrian 1261250003Sadrian } else { 1262250003Sadrian /*Use driver default setting*/ 1263250003Sadrian /* Sleep Setting */ 1264250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1265250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1266250003Sadrian ARRAY_LENGTH( 1267250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1268250003Sadrian 2); 1269250003Sadrian /* Awake Setting */ 1270250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1271250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1272250003Sadrian ARRAY_LENGTH( 1273250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1274250003Sadrian 2); 1275250003Sadrian } 1276250003Sadrian } else { 1277250003Sadrian /* Pci-e Clock Request = 0 */ 1278250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save 1279250003Sadrian & AR_PCIE_PLL_PWRSAVE_CONTROL) 1280250003Sadrian { 1281250003Sadrian /* Sleep Setting */ 1282250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1283250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1284250003Sadrian { 1285250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1286250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1287250003Sadrian ARRAY_LENGTH( 1288250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1289250003Sadrian 2); 1290250003Sadrian } else { 1291250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1292250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1293250003Sadrian ARRAY_LENGTH( 1294250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1295250003Sadrian 2); 1296250003Sadrian } 1297250003Sadrian /* Awake Setting */ 1298250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1299250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1300250003Sadrian { 1301250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1302250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1303250003Sadrian ARRAY_LENGTH( 1304250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1305250003Sadrian 2); 1306250003Sadrian } else { 1307250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1308250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1309250003Sadrian ARRAY_LENGTH( 1310250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1311250003Sadrian 2); 1312250003Sadrian } 1313250003Sadrian 1314250003Sadrian } else { 1315250003Sadrian /*Use driver default setting*/ 1316250003Sadrian /* Sleep Setting */ 1317250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1318250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1319250003Sadrian ARRAY_LENGTH( 1320250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1321250003Sadrian 2); 1322250003Sadrian /* Awake Setting */ 1323250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1324250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1325250003Sadrian ARRAY_LENGTH( 1326250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1327250003Sadrian 2); 1328250003Sadrian } 1329250003Sadrian } 1330250003Sadrian /* pcie ps setting will honor registry setting, default is 0 */ 1331250008Sadrian /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/ 1332250003Sadrian 1333250003Sadrian#if 0 /* ATH_WOW */ 1334250003Sadrian /* SerDes values during WOW sleep */ 1335250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1336250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1337250003Sadrian#endif 1338250003Sadrian 1339250003Sadrian } else if (AR_SREV_WASP(ah)) { 1340250003Sadrian /* mac */ 1341250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1342250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1343250003Sadrian ar9340_wasp_1p0_mac_core, 1344250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2); 1345250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1346250003Sadrian ar9340_wasp_1p0_mac_postamble, 1347250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5); 1348250003Sadrian 1349250003Sadrian /* bb */ 1350250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1351250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1352250003Sadrian ar9340_wasp_1p0_baseband_core, 1353250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2); 1354250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1355250003Sadrian ar9340_wasp_1p0_baseband_postamble, 1356250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5); 1357250003Sadrian 1358250003Sadrian /* radio */ 1359250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1360250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1361250003Sadrian ar9340_wasp_1p0_radio_core, 1362250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2); 1363250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1364250003Sadrian ar9340_wasp_1p0_radio_postamble, 1365250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5); 1366250003Sadrian 1367250003Sadrian /* soc */ 1368250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1369250003Sadrian ar9340_wasp_1p0_soc_preamble, 1370250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2); 1371250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1372250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1373250003Sadrian ar9340_wasp_1p0_soc_postamble, 1374250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5); 1375250003Sadrian 1376250003Sadrian /* rx/tx gain */ 1377250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1378250003Sadrian ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 1379250003Sadrian ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 1380250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1381250003Sadrian ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 1382250003Sadrian ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 1383250003Sadrian 1384250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1385250003Sadrian 1386250003Sadrian /* Fast clock modal settings */ 1387250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1388250003Sadrian ar9340Modes_fast_clock_wasp_1p0, 1389250003Sadrian ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3); 1390250003Sadrian 1391291437Sadrian /* XXX TODO: need to add this for freebsd; it's missing from the current .ini files */ 1392291437Sadrian#if 0 1393291437Sadrian /* Japan 2484Mhz CCK settings */ 1394291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1395291437Sadrian ar9340_wasp_1p0_baseband_core_txfir_coeff_japan_2484, 1396291437Sadrian ARRAY_LENGTH( 1397291437Sadrian ar9340_wasp_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1398291437Sadrian#endif 1399291437Sadrian 1400250003Sadrian /* Additional setttings for 40Mhz */ 1401250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, 1402250003Sadrian ar9340_wasp_1p0_radio_core_40M, 1403250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2); 1404250003Sadrian 1405250003Sadrian /* DFS */ 1406250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1407250003Sadrian ar9340_wasp_1p0_baseband_postamble_dfs_channel, 1408250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3); 1409250003Sadrian } else if (AR_SREV_SCORPION(ah)) { 1410250003Sadrian /* mac */ 1411250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1412250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1413250003Sadrian ar955x_scorpion_1p0_mac_core, 1414250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2); 1415250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1416250003Sadrian ar955x_scorpion_1p0_mac_postamble, 1417250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5); 1418250003Sadrian 1419250003Sadrian /* bb */ 1420250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1421250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1422250003Sadrian ar955x_scorpion_1p0_baseband_core, 1423250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2); 1424250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1425250003Sadrian ar955x_scorpion_1p0_baseband_postamble, 1426250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5); 1427250003Sadrian 1428250003Sadrian /* radio */ 1429250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1430250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1431250003Sadrian ar955x_scorpion_1p0_radio_core, 1432250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2); 1433250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1434250003Sadrian ar955x_scorpion_1p0_radio_postamble, 1435250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5); 1436250003Sadrian 1437250003Sadrian /* soc */ 1438250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1439250003Sadrian ar955x_scorpion_1p0_soc_preamble, 1440250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2); 1441250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1442250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1443250003Sadrian ar955x_scorpion_1p0_soc_postamble, 1444250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5); 1445250003Sadrian 1446250003Sadrian /* rx/tx gain */ 1447250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1448250003Sadrian ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 1449250003Sadrian ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 1450250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1451250003Sadrian ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 1452250003Sadrian ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 1453250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1454250003Sadrian ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 1455250003Sadrian ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5); 1456250003Sadrian 1457250003Sadrian /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1458250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1459250003Sadrian 1460250003Sadrian /* Fast clock modal settings */ 1461250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1462250003Sadrian ar955xModes_fast_clock_scorpion_1p0, 1463250003Sadrian ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3); 1464250003Sadrian 1465250003Sadrian /* Additional setttings for 40Mhz */ 1466250003Sadrian //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1467250003Sadrian // ar955x_scorpion_1p0_radio_core_40M, 1468250003Sadrian // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2); 1469291437Sadrian } else if (AR_SREV_HONEYBEE(ah)) { 1470291437Sadrian /* mac */ 1471291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1472291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1473291437Sadrian qca953x_honeybee_1p0_mac_core, 1474291437Sadrian ARRAY_LENGTH(qca953x_honeybee_1p0_mac_core), 2); 1475291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1476291437Sadrian qca953x_honeybee_1p0_mac_postamble, 1477291437Sadrian ARRAY_LENGTH(qca953x_honeybee_1p0_mac_postamble), 5); 1478291437Sadrian 1479291437Sadrian /* bb */ 1480291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1481291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1482291437Sadrian qca953x_honeybee_1p0_baseband_core, 1483291437Sadrian ARRAY_LENGTH(qca953x_honeybee_1p0_baseband_core), 2); 1484291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1485291437Sadrian qca953x_honeybee_1p0_baseband_postamble, 1486291437Sadrian ARRAY_LENGTH(qca953x_honeybee_1p0_baseband_postamble), 5); 1487291437Sadrian 1488291437Sadrian /* radio */ 1489291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1490291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1491291437Sadrian qca953x_honeybee_1p0_radio_core, 1492291437Sadrian ARRAY_LENGTH(qca953x_honeybee_1p0_radio_core), 2); 1493291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1494291437Sadrian qca953x_honeybee_1p0_radio_postamble, 1495291437Sadrian ARRAY_LENGTH(qca953x_honeybee_1p0_radio_postamble), 5); 1496291437Sadrian 1497291437Sadrian /* soc */ 1498291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1499291437Sadrian qca953x_honeybee_1p0_soc_preamble, 1500291437Sadrian ARRAY_LENGTH(qca953x_honeybee_1p0_soc_preamble), 2); 1501291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1502291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1503291437Sadrian qca953x_honeybee_1p0_soc_postamble, 1504291437Sadrian ARRAY_LENGTH(qca953x_honeybee_1p0_soc_postamble), 5); 1505291437Sadrian 1506291437Sadrian /* rx/tx gain */ 1507291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1508291437Sadrian qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0, 1509291437Sadrian ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0), 2); 1510291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1511291437Sadrian qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0, 1512291437Sadrian ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0), 5); 1513291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1514291437Sadrian qca953xModes_no_xpa_tx_gain_table_honeybee_1p0, 1515291437Sadrian ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p0), 2); 1516291437Sadrian 1517291437Sadrian /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1518291437Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1519291437Sadrian 1520291437Sadrian /* Fast clock modal settings */ 1521291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1522291437Sadrian qca953xModes_fast_clock_honeybee_1p0, 1523291437Sadrian ARRAY_LENGTH(qca953xModes_fast_clock_honeybee_1p0), 3); 1524291437Sadrian 1525291437Sadrian /* Additional setttings for 40Mhz */ 1526291437Sadrian //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1527291437Sadrian // qca953x_honeybee_1p0_radio_core_40M, 1528291437Sadrian // ARRAY_LENGTH(qca953x_honeybee_1p0_radio_core_40M), 2); 1529291437Sadrian 1530250003Sadrian } else if (AR_SREV_JUPITER_10(ah)) { 1531250003Sadrian /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1532250003Sadrian 1533250003Sadrian /* mac */ 1534250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1535250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1536250003Sadrian ar9300_jupiter_1p0_mac_core, 1537250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2); 1538250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1539250003Sadrian ar9300_jupiter_1p0_mac_postamble, 1540250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5); 1541250003Sadrian 1542250003Sadrian /* bb */ 1543250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1544250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1545250003Sadrian ar9300_jupiter_1p0_baseband_core, 1546250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2); 1547250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1548250003Sadrian ar9300_jupiter_1p0_baseband_postamble, 1549250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5); 1550250003Sadrian 1551250003Sadrian /* radio */ 1552250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1553250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1554250003Sadrian ar9300_jupiter_1p0_radio_core, 1555250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2); 1556250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1557250003Sadrian ar9300_jupiter_1p0_radio_postamble, 1558250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5); 1559250003Sadrian 1560250003Sadrian /* soc */ 1561250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1562250003Sadrian ar9300_jupiter_1p0_soc_preamble, 1563250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2); 1564250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1565250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1566250003Sadrian ar9300_jupiter_1p0_soc_postamble, 1567250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5); 1568250003Sadrian 1569250003Sadrian /* rx/tx gain */ 1570250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1571250003Sadrian ar9300_common_rx_gain_table_jupiter_1p0, 1572250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 1573250003Sadrian 1574250003Sadrian /* Load PCIE SERDES settings from INI */ 1575250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1576250003Sadrian /* Pci-e Clock Request = 1 */ 1577250003Sadrian /* 1578250003Sadrian * PLL ON + clkreq enable is not a valid combination, 1579250003Sadrian * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1580250003Sadrian */ 1581250003Sadrian { 1582250003Sadrian /*Use driver default setting*/ 1583250003Sadrian /* Awake -> Sleep Setting */ 1584250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1585250003Sadrian ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1586250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1587250003Sadrian 2); 1588250003Sadrian /* Sleep -> Awake Setting */ 1589250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1590250003Sadrian ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1591250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1592250003Sadrian 2); 1593250003Sadrian } 1594250003Sadrian } 1595250003Sadrian else { 1596250003Sadrian /* 1597250003Sadrian * Since Jupiter 1.0 and 2.0 share the same device id and will be 1598250003Sadrian * installed with same INF, but Jupiter 1.0 has issue with PLL OFF. 1599250003Sadrian * 1600250003Sadrian * Force Jupiter 1.0 to use ON/ON setting. 1601250003Sadrian */ 1602250008Sadrian ah->ah_config.ath_hal_pll_pwr_save = 0; 1603250003Sadrian /* Pci-e Clock Request = 0 */ 1604250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1605250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 1606250003Sadrian { 1607250003Sadrian /* Awake -> Sleep Setting */ 1608250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1609250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1610250003Sadrian { 1611250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1612250003Sadrian ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1613250003Sadrian ARRAY_LENGTH( 1614250003Sadrian ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1615250003Sadrian 2); 1616250003Sadrian } 1617250003Sadrian else { 1618250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1619250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1620250003Sadrian ARRAY_LENGTH( 1621250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1622250003Sadrian 2); 1623250003Sadrian } 1624250003Sadrian /* Sleep -> Awake Setting */ 1625250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1626250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1627250003Sadrian { 1628250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1629250003Sadrian ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1630250003Sadrian ARRAY_LENGTH( 1631250003Sadrian ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1632250003Sadrian 2); 1633250003Sadrian } 1634250003Sadrian else { 1635250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1636250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1637250003Sadrian ARRAY_LENGTH( 1638250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1639250003Sadrian 2); 1640250003Sadrian } 1641250003Sadrian 1642250003Sadrian } 1643250003Sadrian else { 1644250003Sadrian /*Use driver default setting*/ 1645250003Sadrian /* Awake -> Sleep Setting */ 1646250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1647250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1648250003Sadrian ARRAY_LENGTH( 1649250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1650250003Sadrian 2); 1651250003Sadrian /* Sleep -> Awake Setting */ 1652250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1653250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1654250003Sadrian ARRAY_LENGTH( 1655250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1656250003Sadrian 2); 1657250003Sadrian } 1658250003Sadrian } 1659250003Sadrian /* 1660250003Sadrian * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1661250003Sadrian * 0 for merlin 1662250003Sadrian */ 1663250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1664250003Sadrian 1665250003Sadrian#if 0 // ATH_WOW 1666250003Sadrian /* SerDes values during WOW sleep */ 1667250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1668250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1669250003Sadrian#endif 1670250003Sadrian 1671250003Sadrian /* Fast clock modal settings */ 1672250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1673250003Sadrian ar9300_modes_fast_clock_jupiter_1p0, 1674250003Sadrian ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3); 1675250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1676250003Sadrian ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484, 1677250003Sadrian ARRAY_LENGTH( 1678250003Sadrian ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1679250003Sadrian 1680250003Sadrian } 1681301421Sadrian else if (AR_SREV_JUPITER_20_OR_LATER(ah)) { 1682250003Sadrian /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1683250003Sadrian 1684291433Sadrian /* FreeBSD: just override the registers for jupiter 2.1 */ 1685301421Sadrian /* XXX TODO: refactor this stuff out; reinit all the 2.1 registers */ 1686291433Sadrian 1687250003Sadrian /* mac */ 1688250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1689291433Sadrian 1690291433Sadrian if (AR_SREV_JUPITER_21(ah)) { 1691291433Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1692291433Sadrian ar9462_2p1_mac_core, 1693291433Sadrian ARRAY_LENGTH(ar9462_2p1_mac_core), 2); 1694291433Sadrian } else { 1695291433Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1696291433Sadrian ar9300_jupiter_2p0_mac_core, 1697291433Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); 1698291433Sadrian } 1699291433Sadrian 1700250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1701250003Sadrian ar9300_jupiter_2p0_mac_postamble, 1702250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5); 1703250003Sadrian 1704250003Sadrian /* bb */ 1705250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1706250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1707250003Sadrian ar9300_jupiter_2p0_baseband_core, 1708250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2); 1709250003Sadrian 1710291433Sadrian if (AR_SREV_JUPITER_21(ah)) { 1711291433Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1712291433Sadrian ar9462_2p1_baseband_postamble, 1713291433Sadrian ARRAY_LENGTH(ar9462_2p1_baseband_postamble), 5); 1714291433Sadrian } else { 1715291433Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1716291433Sadrian ar9300_jupiter_2p0_baseband_postamble, 1717291433Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); 1718291433Sadrian } 1719291433Sadrian 1720250003Sadrian /* radio */ 1721250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1722250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1723250003Sadrian ar9300_jupiter_2p0_radio_core, 1724250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2); 1725250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1726250003Sadrian ar9300_jupiter_2p0_radio_postamble, 1727250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5); 1728250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant, 1729250003Sadrian ar9300_jupiter_2p0_radio_postamble_sys2ant, 1730250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5); 1731250003Sadrian 1732250003Sadrian /* soc */ 1733291433Sadrian if (AR_SREV_JUPITER_21(ah)) { 1734291433Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1735291433Sadrian ar9462_2p1_soc_preamble, 1736291433Sadrian ARRAY_LENGTH(ar9462_2p1_soc_preamble), 2); 1737291433Sadrian } else { 1738291433Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1739291433Sadrian ar9300_jupiter_2p0_soc_preamble, 1740291433Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); 1741291433Sadrian } 1742250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1743250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1744250003Sadrian ar9300_jupiter_2p0_soc_postamble, 1745250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5); 1746250003Sadrian 1747250003Sadrian /* rx/tx gain */ 1748250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1749250003Sadrian ar9300Common_rx_gain_table_jupiter_2p0, 1750250003Sadrian ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 1751250003Sadrian 1752250003Sadrian /* BTCOEX */ 1753250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR, 1754250003Sadrian ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table, 1755250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2); 1756250003Sadrian 1757250003Sadrian /* Load PCIE SERDES settings from INI */ 1758250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1759250003Sadrian /* Pci-e Clock Request = 1 */ 1760250003Sadrian /* 1761250003Sadrian * PLL ON + clkreq enable is not a valid combination, 1762250003Sadrian * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1763250003Sadrian */ 1764250003Sadrian { 1765250003Sadrian /*Use driver default setting*/ 1766250003Sadrian /* Awake -> Sleep Setting */ 1767250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1768250003Sadrian ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1769250003Sadrian ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1770250003Sadrian 2); 1771250003Sadrian /* Sleep -> Awake Setting */ 1772250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1773250003Sadrian ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1774250003Sadrian ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1775250003Sadrian 2); 1776250003Sadrian } 1777250003Sadrian } 1778250003Sadrian else { 1779250003Sadrian /* Pci-e Clock Request = 0 */ 1780250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1781250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 1782250003Sadrian { 1783250003Sadrian /* Awake -> Sleep Setting */ 1784250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1785250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1786250003Sadrian { 1787250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1788250003Sadrian ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1789250003Sadrian ARRAY_LENGTH( 1790250003Sadrian ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1791250003Sadrian 2); 1792250003Sadrian } 1793250003Sadrian else { 1794250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1795250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1796250003Sadrian ARRAY_LENGTH( 1797250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1798250003Sadrian 2); 1799250003Sadrian } 1800250003Sadrian /* Sleep -> Awake Setting */ 1801250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1802250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1803250003Sadrian { 1804250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1805250003Sadrian ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1806250003Sadrian ARRAY_LENGTH( 1807250003Sadrian ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1808250003Sadrian 2); 1809250003Sadrian } 1810250003Sadrian else { 1811250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1812250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1813250003Sadrian ARRAY_LENGTH( 1814250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1815250003Sadrian 2); 1816250003Sadrian } 1817250003Sadrian 1818250003Sadrian } 1819250003Sadrian else { 1820250003Sadrian /*Use driver default setting*/ 1821250003Sadrian /* Awake -> Sleep Setting */ 1822250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1823250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1824250003Sadrian ARRAY_LENGTH( 1825250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1826250003Sadrian 2); 1827250003Sadrian /* Sleep -> Awake Setting */ 1828250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1829250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1830250003Sadrian ARRAY_LENGTH( 1831250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1832250003Sadrian 2); 1833250003Sadrian } 1834250003Sadrian } 1835250003Sadrian 1836250003Sadrian /* 1837250003Sadrian * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1838250003Sadrian * 0 for merlin 1839250003Sadrian */ 1840250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1841250003Sadrian 1842250003Sadrian#if 0 // ATH_WOW 1843250003Sadrian /* SerDes values during WOW sleep */ 1844250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1845250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1846250003Sadrian#endif 1847250003Sadrian 1848250003Sadrian /* Fast clock modal settings */ 1849250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1850250003Sadrian ar9300Modes_fast_clock_jupiter_2p0, 1851250003Sadrian ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3); 1852250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1853250003Sadrian ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484, 1854250003Sadrian ARRAY_LENGTH( 1855250003Sadrian ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2); 1856250003Sadrian 1857250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 1858250003Sadrian /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */ 1859250003Sadrian 1860250003Sadrian /* mac */ 1861250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1862250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1863250003Sadrian ar956X_aphrodite_1p0_mac_core, 1864250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2); 1865250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1866250003Sadrian ar956X_aphrodite_1p0_mac_postamble, 1867250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5); 1868250003Sadrian 1869250003Sadrian /* bb */ 1870250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1871250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1872250003Sadrian ar956X_aphrodite_1p0_baseband_core, 1873250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2); 1874250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1875250003Sadrian ar956X_aphrodite_1p0_baseband_postamble, 1876250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5); 1877250003Sadrian 1878250003Sadrian//mark jupiter have but aphrodite don't have 1879250003Sadrian// /* radio */ 1880250003Sadrian// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1881250003Sadrian// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1882250003Sadrian// ar9300_aphrodite_1p0_radio_core, 1883250003Sadrian// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2); 1884250003Sadrian// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1885250003Sadrian// ar9300_aphrodite_1p0_radio_postamble, 1886250003Sadrian// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5); 1887250003Sadrian 1888250003Sadrian /* soc */ 1889250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1890250003Sadrian ar956X_aphrodite_1p0_soc_preamble, 1891250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2); 1892250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1893250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1894250003Sadrian ar956X_aphrodite_1p0_soc_postamble, 1895250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5); 1896250003Sadrian 1897250003Sadrian /* rx/tx gain */ 1898250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1899250003Sadrian ar956XCommon_rx_gain_table_aphrodite_1p0, 1900250003Sadrian ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2); 1901250003Sadrian //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1902250003Sadrian // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0, 1903250003Sadrian // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0), 1904250003Sadrian // 5); 1905250003Sadrian 1906250003Sadrian 1907250003Sadrian /* 1908250003Sadrian * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1909250003Sadrian * 0 for merlin 1910250003Sadrian */ 1911250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1912250003Sadrian 1913250003Sadrian#if 0 // ATH_WOW 1914250003Sadrian /* SerDes values during WOW sleep */ 1915250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1916250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1917250003Sadrian#endif 1918250003Sadrian /* Fast clock modal settings */ 1919250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1920250003Sadrian ar956XModes_fast_clock_aphrodite_1p0, 1921250003Sadrian ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3); 1922250003Sadrian 1923250003Sadrian } else if (AR_SREV_AR9580(ah)) { 1924250003Sadrian /* 1925250003Sadrian * AR9580/Peacock - 1926250003Sadrian * new INI format (pre, core, post arrays per subsystem) 1927250003Sadrian */ 1928250003Sadrian 1929250003Sadrian /* mac */ 1930250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1931250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1932250003Sadrian ar9300_ar9580_1p0_mac_core, 1933250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2); 1934250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1935250003Sadrian ar9300_ar9580_1p0_mac_postamble, 1936250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5); 1937250003Sadrian 1938250003Sadrian /* bb */ 1939250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1940250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1941250003Sadrian ar9300_ar9580_1p0_baseband_core, 1942250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2); 1943250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1944250003Sadrian ar9300_ar9580_1p0_baseband_postamble, 1945250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5); 1946250003Sadrian 1947250003Sadrian /* radio */ 1948250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1949250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1950250003Sadrian ar9300_ar9580_1p0_radio_core, 1951250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2); 1952250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1953250003Sadrian ar9300_ar9580_1p0_radio_postamble, 1954250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5); 1955250003Sadrian 1956250003Sadrian /* soc */ 1957250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1958250003Sadrian ar9300_ar9580_1p0_soc_preamble, 1959250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2); 1960250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1961250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1962250003Sadrian ar9300_ar9580_1p0_soc_postamble, 1963250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5); 1964250003Sadrian 1965250003Sadrian /* rx/tx gain */ 1966250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1967250003Sadrian ar9300_common_rx_gain_table_ar9580_1p0, 1968250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 1969250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1970250003Sadrian ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 1971250003Sadrian ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); 1972250003Sadrian 1973250003Sadrian /* DFS */ 1974250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1975250003Sadrian ar9300_ar9580_1p0_baseband_postamble_dfs_channel, 1976250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3); 1977250003Sadrian 1978250003Sadrian 1979250003Sadrian /* Load PCIE SERDES settings from INI */ 1980250003Sadrian 1981250003Sadrian /*D3 Setting */ 1982250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1983250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1984250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 1985250003Sadrian { //registry control 1986250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1987250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1988250003Sadrian { //bit1, in to D3 1989250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1990250003Sadrian ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1991250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1992250003Sadrian 2); 1993250003Sadrian } else { 1994250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1995250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1996250003Sadrian ARRAY_LENGTH( 1997250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1998250003Sadrian 2); 1999250003Sadrian } 2000250003Sadrian } else {//no registry control, default is pll on 2001250003Sadrian INIT_INI_ARRAY( 2002250003Sadrian &ahp->ah_ini_pcie_serdes, 2003250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2004250003Sadrian ARRAY_LENGTH( 2005250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2006250003Sadrian 2); 2007250003Sadrian } 2008250003Sadrian } else { 2009250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2010250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2011250003Sadrian { //registry control 2012250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2013250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 2014250003Sadrian { //bit1, in to D3 2015250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2016250003Sadrian ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 2017250003Sadrian ARRAY_LENGTH( 2018250003Sadrian ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 2019250003Sadrian 2); 2020250003Sadrian } else { 2021250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2022250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2023250003Sadrian ARRAY_LENGTH( 2024250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2025250003Sadrian 2); 2026250003Sadrian } 2027250003Sadrian } else {//no registry control, default is pll on 2028250003Sadrian INIT_INI_ARRAY( 2029250003Sadrian &ahp->ah_ini_pcie_serdes, 2030250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2031250003Sadrian ARRAY_LENGTH( 2032250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2033250003Sadrian 2); 2034250003Sadrian } 2035250003Sadrian } 2036250003Sadrian 2037250003Sadrian /*D0 Setting */ 2038250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 2039250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2040250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2041250003Sadrian { //registry control 2042250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2043250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 2044250003Sadrian { //bit2, out of D3 2045250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2046250003Sadrian ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 2047250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 2048250003Sadrian 2); 2049250003Sadrian 2050250003Sadrian } else { 2051250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2052250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2053250003Sadrian ARRAY_LENGTH( 2054250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2055250003Sadrian 2); 2056250003Sadrian } 2057250003Sadrian } else { //no registry control, default is pll on 2058250003Sadrian INIT_INI_ARRAY( 2059250003Sadrian &ahp->ah_ini_pcie_serdes_low_power, 2060250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2061250003Sadrian ARRAY_LENGTH( 2062250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2063250003Sadrian 2); 2064250003Sadrian } 2065250003Sadrian } else { 2066250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2067250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2068250003Sadrian {//registry control 2069250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2070250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 2071250003Sadrian {//bit2, out of D3 2072250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2073250003Sadrian ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 2074250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 2075250003Sadrian 2); 2076250003Sadrian } else { 2077250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2078250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2079250003Sadrian ARRAY_LENGTH( 2080250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2081250003Sadrian 2); 2082250003Sadrian } 2083250003Sadrian } else { //no registry control, default is pll on 2084250003Sadrian INIT_INI_ARRAY( 2085250003Sadrian &ahp->ah_ini_pcie_serdes_low_power, 2086250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2087250003Sadrian ARRAY_LENGTH( 2088250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2089250003Sadrian 2); 2090250003Sadrian } 2091250003Sadrian } 2092250003Sadrian 2093250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2094250003Sadrian 2095250003Sadrian#if 0 /* ATH_WOW */ 2096250003Sadrian /* SerDes values during WOW sleep */ 2097250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2098250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2099250003Sadrian#endif 2100250003Sadrian 2101250003Sadrian /* Fast clock modal settings */ 2102250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2103250003Sadrian ar9300Modes_fast_clock_ar9580_1p0, 2104250003Sadrian ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3); 2105250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2106250003Sadrian ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484, 2107250003Sadrian ARRAY_LENGTH( 2108250003Sadrian ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2); 2109250003Sadrian 2110250003Sadrian } else { 2111250003Sadrian /* 2112250003Sadrian * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem) 2113250003Sadrian */ 2114250003Sadrian 2115250003Sadrian /* mac */ 2116250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 2117250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 2118250003Sadrian ar9300_osprey_2p2_mac_core, 2119250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2); 2120250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 2121250003Sadrian ar9300_osprey_2p2_mac_postamble, 2122250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5); 2123250003Sadrian 2124250003Sadrian /* bb */ 2125250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 2126250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 2127250003Sadrian ar9300_osprey_2p2_baseband_core, 2128250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2); 2129250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 2130250003Sadrian ar9300_osprey_2p2_baseband_postamble, 2131250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5); 2132250003Sadrian 2133250003Sadrian /* radio */ 2134250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 2135250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 2136250003Sadrian ar9300_osprey_2p2_radio_core, 2137250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2); 2138250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 2139250003Sadrian ar9300_osprey_2p2_radio_postamble, 2140250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5); 2141250003Sadrian 2142250003Sadrian /* soc */ 2143250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 2144250003Sadrian ar9300_osprey_2p2_soc_preamble, 2145250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2); 2146250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 2147250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 2148250003Sadrian ar9300_osprey_2p2_soc_postamble, 2149250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5); 2150250003Sadrian 2151250003Sadrian /* rx/tx gain */ 2152250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 2153250003Sadrian ar9300_common_rx_gain_table_osprey_2p2, 2154250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 2155250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 2156250003Sadrian ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 2157250003Sadrian ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); 2158250003Sadrian 2159250003Sadrian /* DFS */ 2160250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_dfs, 2161250003Sadrian ar9300_osprey_2p2_baseband_postamble_dfs_channel, 2162250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3); 2163250003Sadrian 2164250003Sadrian /* Load PCIE SERDES settings from INI */ 2165250003Sadrian 2166250003Sadrian /*D3 Setting */ 2167250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 2168250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2169250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2170250003Sadrian { //registry control 2171250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2172250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 2173250003Sadrian { //bit1, in to D3 2174250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2175250003Sadrian ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2176250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2177250003Sadrian 2); 2178250003Sadrian } else { 2179250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2180250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2181250003Sadrian ARRAY_LENGTH( 2182250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2183250003Sadrian 2); 2184250003Sadrian } 2185250003Sadrian } else {//no registry control, default is pll on 2186250003Sadrian#ifndef ATH_BUS_PM 2187250003Sadrian INIT_INI_ARRAY( 2188250003Sadrian &ahp->ah_ini_pcie_serdes, 2189250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2190250003Sadrian ARRAY_LENGTH( 2191250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2192250003Sadrian 2); 2193250003Sadrian#else 2194250003Sadrian //no registry control, default is pll off 2195250003Sadrian INIT_INI_ARRAY( 2196250003Sadrian &ahp->ah_ini_pcie_serdes, 2197250003Sadrian ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2198250003Sadrian ARRAY_LENGTH( 2199250003Sadrian ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2200250003Sadrian 2); 2201250003Sadrian#endif 2202250003Sadrian 2203250003Sadrian } 2204250003Sadrian } else { 2205250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2206250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2207250003Sadrian { //registry control 2208250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2209250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 2210250003Sadrian { //bit1, in to D3 2211250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2212250003Sadrian ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2213250003Sadrian ARRAY_LENGTH( 2214250003Sadrian ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2215250003Sadrian 2); 2216250003Sadrian } else { 2217250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2218250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2219250003Sadrian ARRAY_LENGTH( 2220250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2221250003Sadrian 2); 2222250003Sadrian } 2223250003Sadrian } else { 2224250003Sadrian#ifndef ATH_BUS_PM 2225250003Sadrian //no registry control, default is pll on 2226250003Sadrian INIT_INI_ARRAY( 2227250003Sadrian &ahp->ah_ini_pcie_serdes, 2228250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2229250003Sadrian ARRAY_LENGTH( 2230250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2231250003Sadrian 2); 2232250003Sadrian#else 2233250003Sadrian //no registry control, default is pll off 2234250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2235250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); 2236250003Sadrian#endif 2237250003Sadrian } 2238250003Sadrian } 2239250003Sadrian 2240250003Sadrian /*D0 Setting */ 2241250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 2242250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2243250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2244250003Sadrian { //registry control 2245250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2246250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 2247250003Sadrian { //bit2, out of D3 2248250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2249250003Sadrian ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2250250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2251250003Sadrian 2); 2252250003Sadrian 2253250003Sadrian } else { 2254250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2255250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2256250003Sadrian ARRAY_LENGTH( 2257250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2258250003Sadrian 2); 2259250003Sadrian } 2260250003Sadrian } else { //no registry control, default is pll on 2261250003Sadrian INIT_INI_ARRAY( 2262250003Sadrian &ahp->ah_ini_pcie_serdes_low_power, 2263250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2264250003Sadrian ARRAY_LENGTH( 2265250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2266250003Sadrian 2); 2267250003Sadrian } 2268250003Sadrian } else { 2269250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2270250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2271250003Sadrian {//registry control 2272250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2273250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 2274250003Sadrian {//bit2, out of D3 2275250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2276250003Sadrian ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2277250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2278250003Sadrian 2); 2279250003Sadrian } else { 2280250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2281250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2282250003Sadrian ARRAY_LENGTH( 2283250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2284250003Sadrian 2); 2285250003Sadrian } 2286250003Sadrian } else { //no registry control, default is pll on 2287250003Sadrian INIT_INI_ARRAY( 2288250003Sadrian &ahp->ah_ini_pcie_serdes_low_power, 2289250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2290250003Sadrian ARRAY_LENGTH( 2291250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2292250003Sadrian 2); 2293250003Sadrian } 2294250003Sadrian } 2295250003Sadrian 2296250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2297250003Sadrian 2298250003Sadrian#ifdef ATH_BUS_PM 2299250003Sadrian /*Use HAL to config PCI powersave by writing into the SerDes Registers */ 2300250008Sadrian ah->ah_config.ath_hal_pcie_ser_des_write = 1; 2301250003Sadrian#endif 2302250003Sadrian 2303250003Sadrian#if 0 /* ATH_WOW */ 2304250003Sadrian /* SerDes values during WOW sleep */ 2305250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2306250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2307250003Sadrian#endif 2308250003Sadrian 2309250003Sadrian /* Fast clock modal settings */ 2310250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2311250003Sadrian ar9300Modes_fast_clock_osprey_2p2, 2312250003Sadrian ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3); 2313250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2314250003Sadrian ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484, 2315250003Sadrian ARRAY_LENGTH( 2316250003Sadrian ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2); 2317250003Sadrian 2318250003Sadrian } 2319250003Sadrian 2320250003Sadrian if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) 2321250003Sadrian { 2322250003Sadrian#define AR_SOC_RST_OTP_INTF 0xB80600B4 2323250003Sadrian#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2324250003Sadrian 2325250003Sadrian ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF); 2326250003Sadrian if (AR_SREV_SCORPION(ah)) { 2327250003Sadrian ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12; 2328250003Sadrian } 2329250003Sadrian ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode); 2330250003Sadrian#undef REG_READ 2331250003Sadrian#undef AR_SOC_RST_OTP_INTF 2332250003Sadrian } else { 2333250003Sadrian ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP); 2334250003Sadrian } 2335250003Sadrian 2336250003Sadrian 2337250008Sadrian if (ahpriv->ah_ispcie) { 2338250003Sadrian ar9300_config_pci_power_save(ah, 0, 0); 2339250003Sadrian } else { 2340250003Sadrian ar9300_disable_pcie_phy(ah); 2341250003Sadrian } 2342250008Sadrian ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__); 2343250003Sadrian ecode = ar9300_hw_attach(ah); 2344250003Sadrian if (ecode != HAL_OK) { 2345250003Sadrian goto bad; 2346250003Sadrian } 2347250003Sadrian 2348250003Sadrian /* set gain table pointers according to values read from the eeprom */ 2349250003Sadrian ar9300_tx_gain_table_apply(ah); 2350250003Sadrian ar9300_rx_gain_table_apply(ah); 2351250003Sadrian 2352250003Sadrian /* 2353250003Sadrian ** 2354250003Sadrian ** Got everything we need now to setup the capabilities. 2355250003Sadrian */ 2356250003Sadrian 2357250003Sadrian if (!ar9300_fill_capability_info(ah)) { 2358250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 2359250003Sadrian "%s:failed ar9300_fill_capability_info\n", __func__); 2360250003Sadrian ecode = HAL_EEREAD; 2361250003Sadrian goto bad; 2362250003Sadrian } 2363250003Sadrian ecode = ar9300_init_mac_addr(ah); 2364250003Sadrian if (ecode != HAL_OK) { 2365250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 2366250003Sadrian "%s: failed initializing mac address\n", __func__); 2367250003Sadrian goto bad; 2368250003Sadrian } 2369250003Sadrian 2370250003Sadrian /* 2371250003Sadrian * Initialize receive buffer size to MAC default 2372250003Sadrian */ 2373250003Sadrian ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT; 2374250003Sadrian 2375250003Sadrian#if ATH_WOW 2376250003Sadrian#if 0 2377250003Sadrian /* 2378250003Sadrian * Needs to be removed once we stop using XB92 XXX 2379250003Sadrian * FIXME: Check with latest boards too - SriniK 2380250003Sadrian */ 2381250003Sadrian ar9300_wow_set_gpio_reset_low(ah); 2382250003Sadrian#endif 2383250003Sadrian 2384250003Sadrian /* 2385250003Sadrian * Clear the Wow Status. 2386250003Sadrian */ 2387250003Sadrian OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), 2388250003Sadrian OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | 2389250003Sadrian AR_PMCTRL_WOW_PME_CLR); 2390250003Sadrian OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, 2391250003Sadrian AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); 2392250003Sadrian#endif 2393250003Sadrian 2394250003Sadrian /* 2395250003Sadrian * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n 2396250003Sadrian * with aggregation enabled or disabled. 2397250003Sadrian */ 2398250008Sadrian ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 2399250003Sadrian 2400250003Sadrian if (AR_SREV_HORNET(ah)) { 2401250008Sadrian ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ; 2402250008Sadrian ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2403250008Sadrian ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2404250008Sadrian ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2405250008Sadrian ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2406250008Sadrian ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2407250008Sadrian ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2408250003Sadrian } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2409250008Sadrian ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ; 2410250008Sadrian ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2411250008Sadrian ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ; 2412250008Sadrian ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ; 2413250008Sadrian ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2414250008Sadrian ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ; 2415250008Sadrian ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2416250003Sadrian } else { 2417250008Sadrian ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ; 2418250008Sadrian ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2419250008Sadrian ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2420250003Sadrian if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 2421250008Sadrian ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ; 2422250003Sadrian } else { 2423250008Sadrian ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2424250003Sadrian } 2425250008Sadrian ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2426250008Sadrian ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2427250008Sadrian ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2428250003Sadrian } 2429250003Sadrian 2430250003Sadrian 2431250003Sadrian 2432250003Sadrian 2433250003Sadrian /* init BB Panic Watchdog timeout */ 2434250003Sadrian if (AR_SREV_HORNET(ah)) { 2435250008Sadrian ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET; 2436250003Sadrian } else { 2437250008Sadrian ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO; 2438250003Sadrian } 2439250003Sadrian 2440250003Sadrian 2441250003Sadrian /* 2442250003Sadrian * Determine whether tx IQ calibration HW should be enabled, 2443250003Sadrian * and whether tx IQ calibration should be performed during 2444250003Sadrian * AGC calibration, or separately. 2445250003Sadrian */ 2446250003Sadrian if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2447250003Sadrian /* 2448250003Sadrian * Register not initialized yet. This flag will be re-initialized 2449250003Sadrian * after INI loading following each reset. 2450250003Sadrian */ 2451250003Sadrian ahp->tx_iq_cal_enable = 1; 2452250003Sadrian /* if tx IQ cal is enabled, do it together with AGC cal */ 2453250003Sadrian ahp->tx_iq_cal_during_agc_cal = 1; 2454250003Sadrian } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) { 2455250003Sadrian ahp->tx_iq_cal_enable = 1; 2456250003Sadrian ahp->tx_iq_cal_during_agc_cal = 1; 2457250003Sadrian } else { 2458250003Sadrian /* osprey, hornet, wasp */ 2459250003Sadrian ahp->tx_iq_cal_enable = 1; 2460250003Sadrian ahp->tx_iq_cal_during_agc_cal = 0; 2461250003Sadrian } 2462250003Sadrian return ah; 2463250003Sadrian 2464250003Sadrianbad: 2465250003Sadrian if (ahp) { 2466250003Sadrian ar9300_detach((struct ath_hal *) ahp); 2467250003Sadrian } 2468250003Sadrian if (status) { 2469250003Sadrian *status = ecode; 2470250003Sadrian } 2471250003Sadrian return AH_NULL; 2472250003Sadrian} 2473250003Sadrian 2474250003Sadrianvoid 2475250003Sadrianar9300_detach(struct ath_hal *ah) 2476250003Sadrian{ 2477250003Sadrian HALASSERT(ah != AH_NULL); 2478250008Sadrian HALASSERT(ah->ah_magic == AR9300_MAGIC); 2479250003Sadrian 2480250003Sadrian /* Make sure that chip is awake before writing to it */ 2481250003Sadrian if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 2482250003Sadrian HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 2483250003Sadrian "%s: failed to wake up chip\n", 2484250003Sadrian __func__); 2485250003Sadrian } 2486250003Sadrian 2487250003Sadrian ar9300_hw_detach(ah); 2488250003Sadrian ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 2489250003Sadrian 2490250008Sadrian// ath_hal_hdprintf_deregister(ah); 2491250008Sadrian 2492250008Sadrian if (AH9300(ah)->ah_cal_mem) 2493250008Sadrian ath_hal_free(AH9300(ah)->ah_cal_mem); 2494250008Sadrian AH9300(ah)->ah_cal_mem = AH_NULL; 2495250008Sadrian 2496250008Sadrian ath_hal_free(ah); 2497250003Sadrian} 2498250003Sadrian 2499250003Sadrianstruct ath_hal_9300 * 2500250008Sadrianar9300_new_state(u_int16_t devid, HAL_SOFTC sc, 2501250008Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, 2502272292Sadrian uint16_t *eepromdata, 2503272292Sadrian HAL_OPS_CONFIG *ah_config, 2504272292Sadrian HAL_STATUS *status) 2505250003Sadrian{ 2506250003Sadrian static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] = 2507250003Sadrian { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2508250003Sadrian struct ath_hal_9300 *ahp; 2509250003Sadrian struct ath_hal *ah; 2510250003Sadrian 2511250003Sadrian /* NB: memory is returned zero'd */ 2512250008Sadrian ahp = ath_hal_malloc(sizeof(struct ath_hal_9300)); 2513250003Sadrian if (ahp == AH_NULL) { 2514250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2515250003Sadrian "%s: cannot allocate memory for state block\n", 2516250003Sadrian __func__); 2517250003Sadrian *status = HAL_ENOMEM; 2518250003Sadrian return AH_NULL; 2519250003Sadrian } 2520250003Sadrian 2521250008Sadrian ah = &ahp->ah_priv.h; 2522250003Sadrian /* set initial values */ 2523250003Sadrian 2524250008Sadrian /* stub everything first */ 2525250008Sadrian ar9300_set_stub_functions(ah); 2526250008Sadrian 2527250008Sadrian /* setup the FreeBSD HAL methods */ 2528250008Sadrian ar9300_attach_freebsd_ops(ah); 2529250008Sadrian 2530250008Sadrian /* These are private to this particular file, so .. */ 2531250008Sadrian ah->ah_disablePCIE = ar9300_disable_pcie_phy; 2532250008Sadrian AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust; 2533250008Sadrian AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits; 2534250008Sadrian 2535250008Sadrian#if 0 2536250003Sadrian /* Attach Osprey structure as default hal structure */ 2537250003Sadrian OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv)); 2538250008Sadrian#endif 2539250003Sadrian 2540250008Sadrian#if 0 2541250003Sadrian AH_PRIVATE(ah)->amem_handle = amem_handle; 2542250003Sadrian AH_PRIVATE(ah)->ah_osdev = osdev; 2543250008Sadrian#endif 2544250008Sadrian ah->ah_sc = sc; 2545250008Sadrian ah->ah_st = st; 2546250008Sadrian ah->ah_sh = sh; 2547250008Sadrian ah->ah_magic = AR9300_MAGIC; 2548250003Sadrian AH_PRIVATE(ah)->ah_devid = devid; 2549250003Sadrian 2550250003Sadrian AH_PRIVATE(ah)->ah_flags = 0; 2551250003Sadrian 2552250003Sadrian /* 2553250003Sadrian ** Initialize factory defaults in the private space 2554250003Sadrian */ 2555250008Sadrian// ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm); 2556272292Sadrian ar9300_config_defaults_freebsd(ah, ah_config); 2557250003Sadrian 2558250008Sadrian /* XXX FreeBSD: cal is always in EEPROM */ 2559250008Sadrian#if 0 2560250003Sadrian if (!hal_conf_parm->calInFlash) { 2561250003Sadrian AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2562250003Sadrian } 2563250008Sadrian#endif 2564250008Sadrian AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2565250003Sadrian 2566250003Sadrian#if 0 2567250003Sadrian if (ar9300_eep_data_in_flash(ah)) { 2568250003Sadrian ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read; 2569250003Sadrian ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL; 2570250003Sadrian } else { 2571250003Sadrian ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word; 2572250003Sadrian } 2573250003Sadrian#endif 2574250003Sadrian 2575250008Sadrian /* XXX FreeBSD - for now, just supports EEPROM reading */ 2576250008Sadrian ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word; 2577250003Sadrian 2578250008Sadrian AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 2579250008Sadrian AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 2580250008Sadrian 2581250003Sadrian ahp->ah_atim_window = 0; /* [0..1000] */ 2582272292Sadrian 2583250003Sadrian ahp->ah_diversity_control = 2584250008Sadrian ah->ah_config.ath_hal_diversity_control; 2585250003Sadrian ahp->ah_antenna_switch_swap = 2586250008Sadrian ah->ah_config.ath_hal_antenna_switch_swap; 2587250003Sadrian 2588250003Sadrian /* 2589250003Sadrian * Enable MIC handling. 2590250003Sadrian */ 2591250003Sadrian ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 2592250003Sadrian ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */ 2593250003Sadrian ahp->ah_slot_time = (u_int) -1; 2594250003Sadrian ahp->ah_ack_timeout = (u_int) -1; 2595250003Sadrian OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN); 2596250003Sadrian 2597250003Sadrian /* 2598250003Sadrian * 11g-specific stuff 2599250003Sadrian */ 2600250003Sadrian ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */ 2601250003Sadrian 2602250003Sadrian /* SM power mode: Attach time, disable any setting */ 2603250003Sadrian ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT; 2604250003Sadrian 2605250003Sadrian return ahp; 2606250003Sadrian} 2607250003Sadrian 2608250003SadrianHAL_BOOL 2609250003Sadrianar9300_chip_test(struct ath_hal *ah) 2610250003Sadrian{ 2611250003Sadrian /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/ 2612250003Sadrian u_int32_t reg_addr[2] = { AR_STA_ID0 }; 2613250003Sadrian u_int32_t reg_hold[2]; 2614250003Sadrian u_int32_t pattern_data[4] = 2615250003Sadrian { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 2616250003Sadrian int i, j; 2617250003Sadrian 2618250003Sadrian /* Test PHY & MAC registers */ 2619250003Sadrian for (i = 0; i < 1; i++) { 2620250003Sadrian u_int32_t addr = reg_addr[i]; 2621250003Sadrian u_int32_t wr_data, rd_data; 2622250003Sadrian 2623250003Sadrian reg_hold[i] = OS_REG_READ(ah, addr); 2624250003Sadrian for (j = 0; j < 0x100; j++) { 2625250003Sadrian wr_data = (j << 16) | j; 2626250003Sadrian OS_REG_WRITE(ah, addr, wr_data); 2627250003Sadrian rd_data = OS_REG_READ(ah, addr); 2628250003Sadrian if (rd_data != wr_data) { 2629250008Sadrian HALDEBUG(ah, HAL_DEBUG_REGIO, 2630250003Sadrian "%s: address test failed addr: " 2631250003Sadrian "0x%08x - wr:0x%08x != rd:0x%08x\n", 2632250003Sadrian __func__, addr, wr_data, rd_data); 2633250003Sadrian return AH_FALSE; 2634250003Sadrian } 2635250003Sadrian } 2636250003Sadrian for (j = 0; j < 4; j++) { 2637250003Sadrian wr_data = pattern_data[j]; 2638250003Sadrian OS_REG_WRITE(ah, addr, wr_data); 2639250003Sadrian rd_data = OS_REG_READ(ah, addr); 2640250003Sadrian if (wr_data != rd_data) { 2641250008Sadrian HALDEBUG(ah, HAL_DEBUG_REGIO, 2642250003Sadrian "%s: address test failed addr: " 2643250003Sadrian "0x%08x - wr:0x%08x != rd:0x%08x\n", 2644250003Sadrian __func__, addr, wr_data, rd_data); 2645250003Sadrian return AH_FALSE; 2646250003Sadrian } 2647250003Sadrian } 2648250003Sadrian OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]); 2649250003Sadrian } 2650250003Sadrian OS_DELAY(100); 2651250003Sadrian return AH_TRUE; 2652250003Sadrian} 2653250003Sadrian 2654250003Sadrian/* 2655250003Sadrian * Store the channel edges for the requested operational mode 2656250003Sadrian */ 2657250003SadrianHAL_BOOL 2658250003Sadrianar9300_get_channel_edges(struct ath_hal *ah, 2659250003Sadrian u_int16_t flags, u_int16_t *low, u_int16_t *high) 2660250003Sadrian{ 2661250003Sadrian struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2662250003Sadrian HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2663250003Sadrian 2664250008Sadrian if (flags & IEEE80211_CHAN_5GHZ) { 2665250008Sadrian *low = p_cap->halLow5GhzChan; 2666250008Sadrian *high = p_cap->halHigh5GhzChan; 2667250003Sadrian return AH_TRUE; 2668250003Sadrian } 2669250008Sadrian if ((flags & IEEE80211_CHAN_2GHZ)) { 2670250008Sadrian *low = p_cap->halLow2GhzChan; 2671250008Sadrian *high = p_cap->halHigh2GhzChan; 2672250003Sadrian 2673250003Sadrian return AH_TRUE; 2674250003Sadrian } 2675250003Sadrian return AH_FALSE; 2676250003Sadrian} 2677250003Sadrian 2678250003SadrianHAL_BOOL 2679250003Sadrianar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn) 2680250003Sadrian{ 2681250008Sadrian AH_PRIVATE(ah)->ah_currentRD = regdmn; 2682250003Sadrian return AH_TRUE; 2683250003Sadrian} 2684250003Sadrian 2685250003Sadrian/* 2686250003Sadrian * Fill all software cached or static hardware state information. 2687250003Sadrian * Return failure if capabilities are to come from EEPROM and 2688250003Sadrian * cannot be read. 2689250003Sadrian */ 2690250003SadrianHAL_BOOL 2691250003Sadrianar9300_fill_capability_info(struct ath_hal *ah) 2692250003Sadrian{ 2693250003Sadrian#define AR_KEYTABLE_SIZE 128 2694250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2695250003Sadrian struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2696250003Sadrian HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2697250003Sadrian u_int16_t cap_field = 0, eeval; 2698250003Sadrian 2699250003Sadrian ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE); 2700250003Sadrian eeval = ar9300_eeprom_get(ahp, EEP_REG_0); 2701250003Sadrian 2702250003Sadrian /* XXX record serial number */ 2703250008Sadrian AH_PRIVATE(ah)->ah_currentRD = eeval; 2704250003Sadrian 2705250008Sadrian /* Always enable fast clock; leave it up to EEPROM and channel */ 2706250008Sadrian p_cap->halSupportsFastClock5GHz = AH_TRUE; 2707250008Sadrian 2708250008Sadrian p_cap->halIntrMitigation = AH_TRUE; 2709250003Sadrian eeval = ar9300_eeprom_get(ahp, EEP_REG_1); 2710250008Sadrian AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT; 2711250003Sadrian 2712250003Sadrian /* Read the capability EEPROM location */ 2713250003Sadrian cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP); 2714250003Sadrian 2715250003Sadrian /* Construct wireless mode from EEPROM */ 2716250008Sadrian p_cap->halWirelessModes = 0; 2717250003Sadrian eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE); 2718250003Sadrian 2719250008Sadrian /* 2720250008Sadrian * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1, 2721250008Sadrian * or we won't have 11n support. 2722250008Sadrian */ 2723250008Sadrian ah->ah_config.ath_hal_ht_enable = 1; 2724250008Sadrian 2725250003Sadrian if (eeval & AR9300_OPFLAGS_11A) { 2726250008Sadrian p_cap->halWirelessModes |= HAL_MODE_11A | 2727250008Sadrian ((!ah->ah_config.ath_hal_ht_enable || 2728250003Sadrian (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 : 2729250003Sadrian (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 : 2730250003Sadrian (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)))); 2731250003Sadrian } 2732250003Sadrian if (eeval & AR9300_OPFLAGS_11G) { 2733250008Sadrian p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G | 2734250008Sadrian ((!ah->ah_config.ath_hal_ht_enable || 2735250003Sadrian (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 : 2736250003Sadrian (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 : 2737250003Sadrian (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS)))); 2738250003Sadrian } 2739250003Sadrian 2740250003Sadrian /* Get chainamsks from eeprom */ 2741250008Sadrian p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK); 2742250008Sadrian p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK); 2743250003Sadrian 2744250003Sadrian 2745250008Sadrian 2746250008Sadrian#define owl_get_ntxchains(_txchainmask) \ 2747250008Sadrian (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 2748250008Sadrian 2749250008Sadrian /* FreeBSD: Update number of TX/RX streams */ 2750250008Sadrian p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask); 2751250008Sadrian p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask); 2752250008Sadrian 2753250008Sadrian 2754250003Sadrian /* 2755250003Sadrian * This being a newer chip supports TKIP non-splitmic mode. 2756250003Sadrian * 2757250003Sadrian */ 2758250003Sadrian ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2759250008Sadrian p_cap->halTkipMicTxRxKeySupport = AH_TRUE; 2760250003Sadrian 2761250008Sadrian p_cap->halLow2GhzChan = 2312; 2762250008Sadrian p_cap->halHigh2GhzChan = 2732; 2763250003Sadrian 2764250008Sadrian p_cap->halLow5GhzChan = 4920; 2765250008Sadrian p_cap->halHigh5GhzChan = 6100; 2766250003Sadrian 2767250008Sadrian p_cap->halCipherCkipSupport = AH_FALSE; 2768250008Sadrian p_cap->halCipherTkipSupport = AH_TRUE; 2769250008Sadrian p_cap->halCipherAesCcmSupport = AH_TRUE; 2770250003Sadrian 2771250008Sadrian p_cap->halMicCkipSupport = AH_FALSE; 2772250008Sadrian p_cap->halMicTkipSupport = AH_TRUE; 2773250008Sadrian p_cap->halMicAesCcmSupport = AH_TRUE; 2774250003Sadrian 2775250008Sadrian p_cap->halChanSpreadSupport = AH_TRUE; 2776250008Sadrian p_cap->halSleepAfterBeaconBroken = AH_TRUE; 2777250003Sadrian 2778250008Sadrian p_cap->halBurstSupport = AH_TRUE; 2779250008Sadrian p_cap->halChapTuningSupport = AH_TRUE; 2780250008Sadrian p_cap->halTurboPrimeSupport = AH_TRUE; 2781289099Sadrian p_cap->halFastFramesSupport = AH_TRUE; 2782250003Sadrian 2783250008Sadrian p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G; 2784250003Sadrian 2785250008Sadrian// p_cap->hal_xr_support = AH_FALSE; 2786250003Sadrian 2787250008Sadrian p_cap->halHTSupport = 2788250008Sadrian ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE; 2789250003Sadrian 2790250008Sadrian p_cap->halGTTSupport = AH_TRUE; 2791250008Sadrian p_cap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 2792250008Sadrian p_cap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 2793250008Sadrian p_cap->halHTSGI20Support = AH_TRUE; 2794250008Sadrian p_cap->halVEOLSupport = AH_TRUE; 2795250008Sadrian p_cap->halBssIdMaskSupport = AH_TRUE; 2796250003Sadrian /* Bug 26802, fixed in later revs? */ 2797250008Sadrian p_cap->halMcastKeySrchSupport = AH_TRUE; 2798250008Sadrian p_cap->halTsfAddSupport = AH_TRUE; 2799250003Sadrian 2800250003Sadrian if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) { 2801250008Sadrian p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU); 2802250003Sadrian } else { 2803250008Sadrian p_cap->halTotalQueues = HAL_NUM_TX_QUEUES; 2804250003Sadrian } 2805250003Sadrian 2806250003Sadrian if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) { 2807250008Sadrian p_cap->halKeyCacheSize = 2808250003Sadrian 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES); 2809250003Sadrian } else { 2810250008Sadrian p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE; 2811250003Sadrian } 2812250008Sadrian p_cap->halFastCCSupport = AH_TRUE; 2813250008Sadrian// p_cap->hal_num_mr_retries = 4; 2814250008Sadrian// ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD; 2815250003Sadrian 2816250008Sadrian p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM; 2817250003Sadrian 2818250003Sadrian#if 0 2819250003Sadrian /* XXX Verify support in Osprey */ 2820250003Sadrian if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2821250008Sadrian p_cap->halWowSupport = AH_TRUE; 2822250003Sadrian p_cap->hal_wow_match_pattern_exact = AH_TRUE; 2823250003Sadrian if (AR_SREV_MERLIN(ah)) { 2824250003Sadrian p_cap->hal_wow_pattern_match_dword = AH_TRUE; 2825250003Sadrian } 2826250003Sadrian } else { 2827250008Sadrian p_cap->halWowSupport = AH_FALSE; 2828250003Sadrian p_cap->hal_wow_match_pattern_exact = AH_FALSE; 2829250003Sadrian } 2830250003Sadrian#endif 2831250008Sadrian p_cap->halWowSupport = AH_TRUE; 2832250008Sadrian p_cap->halWowMatchPatternExact = AH_TRUE; 2833250003Sadrian if (AR_SREV_POSEIDON(ah)) { 2834250008Sadrian p_cap->halWowMatchPatternExact = AH_TRUE; 2835250003Sadrian } 2836250003Sadrian 2837250008Sadrian p_cap->halCSTSupport = AH_TRUE; 2838250003Sadrian 2839250008Sadrian p_cap->halRifsRxSupport = AH_TRUE; 2840250008Sadrian p_cap->halRifsTxSupport = AH_TRUE; 2841250003Sadrian 2842250008Sadrian#define IEEE80211_AMPDU_LIMIT_MAX (65536) 2843250008Sadrian p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX; 2844250008Sadrian#undef IEEE80211_AMPDU_LIMIT_MAX 2845250003Sadrian 2846250008Sadrian p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support; 2847250003Sadrian 2848250008Sadrian p_cap->halForcePpmSupport = AH_TRUE; 2849250008Sadrian p_cap->halHwBeaconProcSupport = AH_TRUE; 2850250003Sadrian 2851250003Sadrian /* ar9300 - has the HW UAPSD trigger support, 2852250003Sadrian * but it has the following limitations 2853250003Sadrian * The power state change from the following 2854250003Sadrian * frames are not put in High priority queue. 2855250003Sadrian * i) Mgmt frames 2856250003Sadrian * ii) NoN QoS frames 2857250003Sadrian * iii) QoS frames form the access categories for which 2858250003Sadrian * UAPSD is not enabled. 2859250003Sadrian * so we can not enable this feature currently. 2860250003Sadrian * could be enabled, if these limitations are fixed 2861250003Sadrian * in later versions of ar9300 chips 2862250003Sadrian */ 2863250008Sadrian p_cap->halHasUapsdSupport = AH_FALSE; 2864250003Sadrian 2865250003Sadrian /* Number of buffers that can be help in a single TxD */ 2866250008Sadrian p_cap->halNumTxMaps = 4; 2867250003Sadrian 2868250008Sadrian p_cap->halTxDescLen = sizeof(struct ar9300_txc); 2869250008Sadrian p_cap->halTxStatusLen = sizeof(struct ar9300_txs); 2870250008Sadrian p_cap->halRxStatusLen = sizeof(struct ar9300_rxs); 2871250003Sadrian 2872250008Sadrian p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH; 2873250008Sadrian p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH; 2874250003Sadrian 2875250003Sadrian /* Enable extension channel DFS support */ 2876250008Sadrian p_cap->halUseCombinedRadarRssi = AH_TRUE; 2877250008Sadrian p_cap->halExtChanDfsSupport = AH_TRUE; 2878250003Sadrian#if ATH_SUPPORT_SPECTRAL 2879250008Sadrian p_cap->halSpectralScanSupport = AH_TRUE; 2880250003Sadrian#endif 2881250003Sadrian 2882250003Sadrian ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT); 2883250003Sadrian if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) { 2884250003Sadrian ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 2885250003Sadrian ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY); 2886250003Sadrian 2887250003Sadrian ath_hal_enable_rfkill(ah, AH_TRUE); 2888250008Sadrian p_cap->halRfSilentSupport = AH_TRUE; 2889250003Sadrian } 2890250003Sadrian 2891250003Sadrian /* XXX */ 2892250008Sadrian p_cap->halWpsPushButtonSupport = AH_FALSE; 2893250003Sadrian 2894250003Sadrian#ifdef ATH_BT_COEX 2895250008Sadrian p_cap->halBtCoexSupport = AH_TRUE; 2896250008Sadrian p_cap->halBtCoexApsmWar = AH_FALSE; 2897250003Sadrian#endif 2898250003Sadrian 2899250008Sadrian p_cap->halGenTimerSupport = AH_TRUE; 2900250003Sadrian ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1); 2901250003Sadrian ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1; 2902250003Sadrian /* 2903250003Sadrian * According to Kyungwan, generic timer 0 and 8 are special 2904250003Sadrian * timers. Remove timer 8 from the available gen timer list. 2905250003Sadrian * Jupiter testing shows timer won't trigger with timer 8. 2906250003Sadrian */ 2907250003Sadrian ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED); 2908250003Sadrian 2909250003Sadrian if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2910250003Sadrian#if ATH_SUPPORT_MCI 2911250008Sadrian if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI) 2912250003Sadrian { 2913250008Sadrian p_cap->halMciSupport = AH_FALSE; 2914250003Sadrian } 2915250003Sadrian else 2916250003Sadrian#endif 2917250003Sadrian { 2918250008Sadrian p_cap->halMciSupport = (ahp->ah_enterprise_mode & 2919250008Sadrian AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE; 2920250003Sadrian } 2921250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2922250003Sadrian "%s: (MCI) MCI support = %d\n", 2923250008Sadrian __func__, p_cap->halMciSupport); 2924250003Sadrian } 2925250003Sadrian else { 2926250008Sadrian p_cap->halMciSupport = AH_FALSE; 2927250003Sadrian } 2928250003Sadrian 2929301421Sadrian /* XXX TODO: jupiter 2.1? */ 2930250003Sadrian if (AR_SREV_JUPITER_20(ah)) { 2931250008Sadrian p_cap->halRadioRetentionSupport = AH_TRUE; 2932250003Sadrian } else { 2933250008Sadrian p_cap->halRadioRetentionSupport = AH_FALSE; 2934250003Sadrian } 2935250003Sadrian 2936250008Sadrian p_cap->halAutoSleepSupport = AH_TRUE; 2937250003Sadrian 2938250008Sadrian p_cap->halMbssidAggrSupport = AH_TRUE; 2939250008Sadrian// p_cap->hal_proxy_sta_support = AH_TRUE; 2940250003Sadrian 2941250008Sadrian /* XXX Mark it true after it is verfied as fixed */ 2942250008Sadrian p_cap->hal4kbSplitTransSupport = AH_FALSE; 2943250003Sadrian 2944250003Sadrian /* Read regulatory domain flag */ 2945250008Sadrian if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2946250003Sadrian /* 2947250003Sadrian * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND. 2948250003Sadrian */ 2949250008Sadrian p_cap->halRegCap = 2950250003Sadrian AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2951250003Sadrian AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2952250003Sadrian AR_EEPROM_EEREGCAP_EN_KK_U2 | 2953250003Sadrian AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2954250003Sadrian } else { 2955250008Sadrian p_cap->halRegCap = 2956250003Sadrian AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2957250003Sadrian } 2958250003Sadrian 2959250003Sadrian /* For AR9300 and above, midband channels are always supported */ 2960250008Sadrian p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2961250003Sadrian 2962250008Sadrian p_cap->halNumAntCfg5GHz = 2963250003Sadrian ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); 2964250008Sadrian p_cap->halNumAntCfg2GHz = 2965250003Sadrian ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); 2966250003Sadrian 2967250003Sadrian /* STBC supported */ 2968250008Sadrian p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */ 2969250003Sadrian if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2970250008Sadrian p_cap->halTxStbcSupport = 0; 2971250003Sadrian } else { 2972250008Sadrian p_cap->halTxStbcSupport = 1; 2973250003Sadrian } 2974250003Sadrian 2975250008Sadrian p_cap->halEnhancedDmaSupport = AH_TRUE; 2976250008Sadrian p_cap->halEnhancedDfsSupport = AH_TRUE; 2977250003Sadrian 2978250003Sadrian /* 2979250003Sadrian * EV61133 (missing interrupts due to AR_ISR_RAC). 2980250003Sadrian * Fixed in Osprey 2.0. 2981250003Sadrian */ 2982250008Sadrian p_cap->halIsrRacSupport = AH_TRUE; 2983250003Sadrian 2984250008Sadrian /* XXX FreeBSD won't support TKIP and WEP aggregation */ 2985250008Sadrian#if 0 2986250003Sadrian p_cap->hal_wep_tkip_aggr_support = AH_TRUE; 2987250003Sadrian p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */ 2988250003Sadrian p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */ 2989250003Sadrian p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */ 2990250008Sadrian#endif 2991250008Sadrian 2992250008Sadrian /* 2993250008Sadrian * XXX FreeBSD won't need these; but eventually add them 2994250008Sadrian * and add the WARs - AGGR extra delim WAR is useful to know 2995250008Sadrian * about. 2996250008Sadrian */ 2997250008Sadrian#if 0 2998250003Sadrian p_cap->hal_cfend_fix_support = AH_FALSE; 2999250003Sadrian p_cap->hal_aggr_extra_delim_war = AH_FALSE; 3000250008Sadrian#endif 3001250008Sadrian p_cap->halHasLongRxDescTsf = AH_TRUE; 3002250008Sadrian// p_cap->hal_rx_desc_timestamp_bits = 32; 3003250008Sadrian p_cap->halRxTxAbortSupport = AH_TRUE; 3004250003Sadrian p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL; 3005250003Sadrian p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC; 3006250003Sadrian 3007250003Sadrian /* Transmit Beamforming supported, fill capabilities */ 3008250008Sadrian p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED); 3009250008Sadrian p_cap->halChanHalfRate = 3010250003Sadrian !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE); 3011250008Sadrian p_cap->halChanQuarterRate = 3012250003Sadrian !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE); 3013250003Sadrian 3014250003Sadrian if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 3015250003Sadrian /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */ 3016250008Sadrian p_cap->hal49GhzSupport = 1; 3017250003Sadrian } else { 3018250008Sadrian p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE); 3019250003Sadrian } 3020250003Sadrian 3021250003Sadrian if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) { 3022250003Sadrian /* LDPC supported */ 3023250003Sadrian /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */ 3024250008Sadrian p_cap->halLDPCSupport = AH_FALSE; 3025250003Sadrian /* PCI_E LCR offset */ 3026250003Sadrian if (AR_SREV_POSEIDON(ah)) { 3027250003Sadrian p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/ 3028250003Sadrian } 3029250003Sadrian /*WAR method for APSM L0s with Poseidon 1.0*/ 3030250003Sadrian if (AR_SREV_POSEIDON_10(ah)) { 3031250003Sadrian p_cap->hal_pcie_lcr_extsync_en = AH_TRUE; 3032250003Sadrian } 3033250003Sadrian } else { 3034250008Sadrian p_cap->halLDPCSupport = AH_TRUE; 3035250003Sadrian } 3036250003Sadrian 3037250008Sadrian /* XXX is this a flag, or a chainmask number? */ 3038250008Sadrian p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE); 3039250003Sadrian#if ATH_ANT_DIV_COMB 3040301012Sadrian if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 3041250003Sadrian if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) { 3042250003Sadrian u_int8_t ant_div_control1 = 3043250003Sadrian ar9300_eeprom_get(ahp, EEP_ANTDIV_control); 3044250003Sadrian /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1, 3045250003Sadrian * we enable the diversity-combining algorithm. 3046250003Sadrian */ 3047250003Sadrian if ((ant_div_control1 >> 0x6) == 0x3) { 3048250008Sadrian p_cap->halAntDivCombSupport = AH_TRUE; 3049250003Sadrian } 3050250008Sadrian p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport; 3051250003Sadrian } 3052250003Sadrian } 3053250003Sadrian#endif /* ATH_ANT_DIV_COMB */ 3054250003Sadrian 3055251676Sadrian /* 3056251676Sadrian * FreeBSD: enable LNA mixing if the chip is Hornet or Poseidon. 3057251676Sadrian */ 3058251676Sadrian if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3059251676Sadrian p_cap->halRxUsingLnaMixing = AH_TRUE; 3060251676Sadrian } 3061250003Sadrian 3062265034Sadrian /* 3063265034Sadrian * AR5416 and later NICs support MYBEACON filtering. 3064265034Sadrian */ 3065265034Sadrian p_cap->halRxDoMyBeacon = AH_TRUE; 3066251676Sadrian 3067250003Sadrian#if ATH_WOW_OFFLOAD 3068250003Sadrian if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 3069250003Sadrian p_cap->hal_wow_gtk_offload_support = AH_TRUE; 3070250003Sadrian p_cap->hal_wow_arp_offload_support = AH_TRUE; 3071250003Sadrian p_cap->hal_wow_ns_offload_support = AH_TRUE; 3072250003Sadrian p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE; 3073250003Sadrian p_cap->hal_wow_acer_magic_support = AH_TRUE; 3074250003Sadrian p_cap->hal_wow_acer_swka_support = AH_TRUE; 3075250003Sadrian } else { 3076250003Sadrian p_cap->hal_wow_gtk_offload_support = AH_FALSE; 3077250003Sadrian p_cap->hal_wow_arp_offload_support = AH_FALSE; 3078250003Sadrian p_cap->hal_wow_ns_offload_support = AH_FALSE; 3079250003Sadrian p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE; 3080250003Sadrian p_cap->hal_wow_acer_magic_support = AH_FALSE; 3081250003Sadrian p_cap->hal_wow_acer_swka_support = AH_FALSE; 3082250003Sadrian } 3083250003Sadrian#endif /* ATH_WOW_OFFLOAD */ 3084250003Sadrian 3085250003Sadrian 3086250003Sadrian return AH_TRUE; 3087250003Sadrian#undef AR_KEYTABLE_SIZE 3088250003Sadrian} 3089250003Sadrian 3090250008Sadrian#if 0 3091250003Sadrianstatic HAL_BOOL 3092250003Sadrianar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, 3093250003Sadrian u_int32_t nchans) 3094250003Sadrian{ 3095250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3096250003Sadrian 3097250003Sadrian return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans); 3098250003Sadrian} 3099250008Sadrian#endif 3100250008Sadrian/* XXX FreeBSD */ 3101250003Sadrian 3102250008Sadrianstatic HAL_BOOL 3103250008Sadrianar9300_get_chip_power_limits(struct ath_hal *ah, 3104250008Sadrian struct ieee80211_channel *chan) 3105250008Sadrian{ 3106250008Sadrian 3107250008Sadrian chan->ic_maxpower = AR9300_MAX_RATE_POWER; 3108250008Sadrian chan->ic_minpower = 0; 3109250008Sadrian 3110250008Sadrian return AH_TRUE; 3111250008Sadrian} 3112250008Sadrian 3113250003Sadrian/* 3114250003Sadrian * Disable PLL when in L0s as well as receiver clock when in L1. 3115250003Sadrian * This power saving option must be enabled through the Serdes. 3116250003Sadrian * 3117250003Sadrian * Programming the Serdes must go through the same 288 bit serial shift 3118250003Sadrian * register as the other analog registers. Hence the 9 writes. 3119250003Sadrian * 3120250003Sadrian * XXX Clean up the magic numbers. 3121250003Sadrian */ 3122250003Sadrianvoid 3123250003Sadrianar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off) 3124250003Sadrian{ 3125250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3126250003Sadrian int i; 3127250003Sadrian 3128250008Sadrian if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) { 3129250003Sadrian return; 3130250003Sadrian } 3131250003Sadrian 3132250003Sadrian /* 3133250003Sadrian * Increase L1 Entry Latency. Some WB222 boards don't have 3134250003Sadrian * this change in eeprom/OTP. 3135250003Sadrian */ 3136250003Sadrian if (AR_SREV_JUPITER(ah)) { 3137250008Sadrian u_int32_t val = ah->ah_config.ath_hal_war70c; 3138250003Sadrian if ((val & 0xff000000) == 0x17000000) { 3139250003Sadrian val &= 0x00ffffff; 3140250003Sadrian val |= 0x27000000; 3141250003Sadrian OS_REG_WRITE(ah, 0x570c, val); 3142250003Sadrian } 3143250003Sadrian } 3144250003Sadrian 3145250003Sadrian /* Do not touch SERDES registers */ 3146250008Sadrian if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) { 3147250003Sadrian return; 3148250003Sadrian } 3149250003Sadrian 3150250003Sadrian /* Nothing to do on restore for 11N */ 3151250003Sadrian if (!restore) { 3152250003Sadrian /* set bit 19 to allow forcing of pcie core into L1 state */ 3153250003Sadrian OS_REG_SET_BIT(ah, 3154250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); 3155250003Sadrian 3156250003Sadrian /* 3157250003Sadrian * Set PCIE workaround config only if requested, else use the reset 3158250003Sadrian * value of this register. 3159250003Sadrian */ 3160250008Sadrian if (ah->ah_config.ath_hal_pcie_waen) { 3161250003Sadrian OS_REG_WRITE(ah, 3162250003Sadrian AR_HOSTIF_REG(ah, AR_WA), 3163250008Sadrian ah->ah_config.ath_hal_pcie_waen); 3164250003Sadrian } else { 3165250003Sadrian /* Set Bits 17 and 14 in the AR_WA register. */ 3166250003Sadrian OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 3167250003Sadrian } 3168250003Sadrian } 3169250003Sadrian 3170250003Sadrian /* Configure PCIE after Ini init. SERDES values now come from ini file */ 3171250008Sadrian if (ah->ah_config.ath_hal_pcie_ser_des_write) { 3172250003Sadrian if (power_off) { 3173250003Sadrian for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) { 3174250003Sadrian OS_REG_WRITE(ah, 3175250003Sadrian INI_RA(&ahp->ah_ini_pcie_serdes, i, 0), 3176250003Sadrian INI_RA(&ahp->ah_ini_pcie_serdes, i, 1)); 3177250003Sadrian } 3178250003Sadrian } else { 3179250003Sadrian for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) { 3180250003Sadrian OS_REG_WRITE(ah, 3181250003Sadrian INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0), 3182250003Sadrian INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1)); 3183250003Sadrian } 3184250003Sadrian } 3185250003Sadrian } 3186250003Sadrian 3187250003Sadrian} 3188250003Sadrian 3189250003Sadrian/* 3190250003Sadrian * Recipe from charles to turn off PCIe PHY in PCI mode for power savings 3191250003Sadrian */ 3192250003Sadrianvoid 3193250003Sadrianar9300_disable_pcie_phy(struct ath_hal *ah) 3194250003Sadrian{ 3195250003Sadrian /* Osprey does not support PCI mode */ 3196250003Sadrian} 3197250003Sadrian 3198250003Sadrianstatic inline HAL_STATUS 3199250003Sadrianar9300_init_mac_addr(struct ath_hal *ah) 3200250003Sadrian{ 3201250003Sadrian u_int32_t sum; 3202250003Sadrian int i; 3203250003Sadrian u_int16_t eeval; 3204250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3205250003Sadrian u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 3206250003Sadrian 3207250003Sadrian sum = 0; 3208250003Sadrian for (i = 0; i < 3; i++) { 3209250003Sadrian eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]); 3210250003Sadrian sum += eeval; 3211250003Sadrian ahp->ah_macaddr[2*i] = eeval >> 8; 3212250003Sadrian ahp->ah_macaddr[2*i + 1] = eeval & 0xff; 3213250003Sadrian } 3214250003Sadrian if (sum == 0 || sum == 0xffff*3) { 3215250003Sadrian HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n", 3216250003Sadrian __func__, ath_hal_ether_sprintf(ahp->ah_macaddr)); 3217250003Sadrian return HAL_EEBADMAC; 3218250003Sadrian } 3219250003Sadrian 3220250003Sadrian return HAL_OK; 3221250003Sadrian} 3222250003Sadrian 3223250003Sadrian/* 3224250003Sadrian * Code for the "real" chip i.e. non-emulation. Review and revisit 3225250003Sadrian * when actual hardware is at hand. 3226250003Sadrian */ 3227250003Sadrianstatic inline HAL_STATUS 3228250003Sadrianar9300_hw_attach(struct ath_hal *ah) 3229250003Sadrian{ 3230250003Sadrian HAL_STATUS ecode; 3231250003Sadrian 3232250003Sadrian if (!ar9300_chip_test(ah)) { 3233250008Sadrian HALDEBUG(ah, HAL_DEBUG_REGIO, 3234250003Sadrian "%s: hardware self-test failed\n", __func__); 3235250003Sadrian return HAL_ESELFTEST; 3236250003Sadrian } 3237250003Sadrian 3238250008Sadrian ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__); 3239250003Sadrian ecode = ar9300_eeprom_attach(ah); 3240250008Sadrian ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode); 3241250003Sadrian if (ecode != HAL_OK) { 3242250003Sadrian return ecode; 3243250003Sadrian } 3244250003Sadrian if (!ar9300_rf_attach(ah, &ecode)) { 3245250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n", 3246250003Sadrian __func__, ecode); 3247250003Sadrian } 3248250003Sadrian 3249250003Sadrian if (ecode != HAL_OK) { 3250250003Sadrian return ecode; 3251250003Sadrian } 3252250003Sadrian ar9300_ani_attach(ah); 3253250003Sadrian 3254250003Sadrian return HAL_OK; 3255250003Sadrian} 3256250003Sadrian 3257250003Sadrianstatic inline void 3258250003Sadrianar9300_hw_detach(struct ath_hal *ah) 3259250003Sadrian{ 3260250003Sadrian /* XXX EEPROM allocated state */ 3261250003Sadrian ar9300_ani_detach(ah); 3262250003Sadrian} 3263250003Sadrian 3264250003Sadrianstatic int16_t 3265250003Sadrianar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 3266250003Sadrian{ 3267250003Sadrian return 0; 3268250003Sadrian} 3269250003Sadrian 3270250003Sadrianvoid 3271250003Sadrianar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable) 3272250003Sadrian{ 3273250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3274250003Sadrian u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0], 3275250003Sadrian m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1], 3276250003Sadrian m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2], 3277250003Sadrian m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3], 3278250003Sadrian m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4], 3279250003Sadrian m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5]; 3280250003Sadrian 3281250003Sadrian if (ahp->ah_immunity_on == enable) { 3282250003Sadrian return; 3283250003Sadrian } 3284250003Sadrian 3285250003Sadrian ahp->ah_immunity_on = enable; 3286250003Sadrian 3287250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3288250003Sadrian AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); 3289250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3290250003Sadrian AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); 3291250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3292250003Sadrian AR_PHY_SFCORR_M1_THRESH, m1_thresh); 3293250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3294250003Sadrian AR_PHY_SFCORR_M2_THRESH, m2_thresh); 3295250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3296250003Sadrian AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr); 3297250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3298250003Sadrian AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); 3299250003Sadrian 3300250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3301250003Sadrian AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low); 3302250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3303250003Sadrian AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low); 3304250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3305250003Sadrian AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh); 3306250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3307250003Sadrian AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh); 3308250003Sadrian 3309250003Sadrian if (!enable) { 3310250003Sadrian OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 3311250003Sadrian AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3312250003Sadrian } else { 3313250003Sadrian OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 3314250003Sadrian AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3315250003Sadrian } 3316250003Sadrian} 3317250003Sadrian 3318250008Sadrian/* XXX FreeBSD: I'm not sure how to implement this.. */ 3319250008Sadrian#if 0 3320250003Sadrianint 3321250003Sadrianar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 3322250003Sadrian HAL_CAL_QUERY query) 3323250003Sadrian{ 3324250003Sadrian#define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \ 3325250003Sadrian ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0) 3326250003Sadrian#define AR9300_IS_RX_IQCAL_DISABLED(_ah) \ 3327250003Sadrian (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \ 3328250003Sadrian AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE)) 3329250003Sadrian/* Avoid comilation warnings. Variables are not used when EMULATION. */ 3330250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3331250003Sadrian u_int8_t rxchainmask = ahp->ah_rx_chainmask, i; 3332250003Sadrian int rx_iqcal_invalid = 0, num_chains = 0; 3333250003Sadrian static const u_int32_t offset_array[3] = { 3334250003Sadrian AR_PHY_RX_IQCAL_CORR_B0, 3335250003Sadrian AR_PHY_RX_IQCAL_CORR_B1, 3336250003Sadrian AR_PHY_RX_IQCAL_CORR_B2}; 3337250003Sadrian 3338250003Sadrian *timerp = ar9300_cals; 3339250003Sadrian 3340250003Sadrian switch (query) { 3341250003Sadrian case HAL_QUERY_CALS: 3342250003Sadrian return AR9300_NUM_CAL_TYPES; 3343250003Sadrian case HAL_QUERY_RERUN_CALS: 3344250003Sadrian for (i = 0; i < AR9300_MAX_CHAINS; i++) { 3345250003Sadrian if (rxchainmask & (1 << i)) { 3346250003Sadrian num_chains++; 3347250003Sadrian } 3348250003Sadrian } 3349250003Sadrian for (i = 0; i < num_chains; i++) { 3350250003Sadrian if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 3351250003Sadrian HALASSERT(num_chains == 0x1); 3352250003Sadrian } 3353250003Sadrian if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) { 3354250003Sadrian rx_iqcal_invalid = 1; 3355250003Sadrian } 3356250003Sadrian } 3357250003Sadrian if (AR9300_IS_RX_IQCAL_DISABLED(ah)) { 3358250003Sadrian rx_iqcal_invalid = 1; 3359250003Sadrian } 3360250003Sadrian 3361250003Sadrian return rx_iqcal_invalid; 3362250003Sadrian default: 3363250003Sadrian HALASSERT(0); 3364250003Sadrian } 3365250003Sadrian return 0; 3366250003Sadrian} 3367250008Sadrian#endif 3368250003Sadrian 3369250003Sadrian#if ATH_TRAFFIC_FAST_RECOVER 3370250003Sadrian#define PLL3 0x16188 3371250003Sadrian#define PLL3_DO_MEAS_MASK 0x40000000 3372250003Sadrian#define PLL4 0x1618c 3373250003Sadrian#define PLL4_MEAS_DONE 0x8 3374250003Sadrian#define SQSUM_DVC_MASK 0x007ffff8 3375250003Sadrianunsigned long 3376250003Sadrianar9300_get_pll3_sqsum_dvc(struct ath_hal *ah) 3377250003Sadrian{ 3378250003Sadrian if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 3379250003Sadrian OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); 3380250003Sadrian OS_DELAY(100); 3381250003Sadrian OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); 3382250003Sadrian 3383250003Sadrian while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 3384250003Sadrian OS_DELAY(100); 3385250003Sadrian } 3386250003Sadrian 3387250003Sadrian return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); 3388250003Sadrian } else { 3389250003Sadrian HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 3390250003Sadrian "%s: unable to get pll3_sqsum_dvc\n", 3391250003Sadrian __func__); 3392250003Sadrian return 0; 3393250003Sadrian } 3394250003Sadrian} 3395250003Sadrian#endif 3396250003Sadrian 3397250003Sadrian 3398250003Sadrian#define RX_GAIN_TABLE_LENGTH 128 3399250003Sadrian// this will be called if rfGainCAP is enabled and rfGainCAP setting is changed, 3400250003Sadrian// or rxGainTable setting is changed 3401250003SadrianHAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz) 3402250003Sadrian{ 3403250003Sadrian int i, done = 0, i_rx_gain = 32; 3404250003Sadrian u_int32_t rf_gain_cap; 3405250003Sadrian u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped; 3406250003Sadrian static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2]; 3407250003Sadrian ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; 3408250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3409250003Sadrian 3410250003Sadrian if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) ) 3411250003Sadrian return AH_FALSE; 3412250003Sadrian 3413250003Sadrian if (is_2GHz) 3414250003Sadrian { 3415250003Sadrian rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap; 3416250003Sadrian } 3417250003Sadrian else 3418250003Sadrian { 3419250003Sadrian rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap; 3420250003Sadrian } 3421250003Sadrian 3422250003Sadrian if (rf_gain_cap == 0) 3423250003Sadrian return AH_FALSE; 3424250003Sadrian 3425250003Sadrian for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++) 3426250003Sadrian { 3427250003Sadrian if (AR_SREV_AR9580(ah)) 3428250003Sadrian { 3429250003Sadrian // BB_rx_ocgain2 3430250003Sadrian i_rx_gain = 128 + 32; 3431250003Sadrian switch (ar9300_rx_gain_index_get(ah)) 3432250003Sadrian { 3433250003Sadrian case 0: 3434250003Sadrian rx_gain_table[i][0] = 3435250003Sadrian ar9300_common_rx_gain_table_ar9580_1p0[i][0]; 3436250003Sadrian rx_gain_table[i][1] = 3437250003Sadrian ar9300_common_rx_gain_table_ar9580_1p0[i][1]; 3438250003Sadrian break; 3439250003Sadrian case 1: 3440250003Sadrian rx_gain_table[i][0] = 3441250003Sadrian ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0]; 3442250003Sadrian rx_gain_table[i][1] = 3443250003Sadrian ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1]; 3444250003Sadrian break; 3445250003Sadrian } 3446250003Sadrian } 3447250003Sadrian else if (AR_SREV_OSPREY_22(ah)) 3448250003Sadrian { 3449250003Sadrian i_rx_gain = 128 + 32; 3450250003Sadrian switch (ar9300_rx_gain_index_get(ah)) 3451250003Sadrian { 3452250003Sadrian case 0: 3453250003Sadrian rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0]; 3454250003Sadrian rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1]; 3455250003Sadrian break; 3456250003Sadrian case 1: 3457250003Sadrian rx_gain_table[i][0] = 3458250003Sadrian ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0]; 3459250003Sadrian rx_gain_table[i][1] = 3460250003Sadrian ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1]; 3461250003Sadrian break; 3462250003Sadrian } 3463250003Sadrian } 3464250003Sadrian else 3465250003Sadrian { 3466250003Sadrian return AH_FALSE; 3467250003Sadrian } 3468250003Sadrian } 3469250003Sadrian 3470250003Sadrian while (1) 3471250003Sadrian { 3472250003Sadrian rx_gain_value = rx_gain_table[i_rx_gain][1]; 3473250003Sadrian rx_gain_value_caped = rx_gain_value; 3474250003Sadrian a_Byte = rx_gain_value & (0x000000FF); 3475250003Sadrian if (a_Byte>rf_gain_cap) 3476250003Sadrian { 3477250003Sadrian rx_gain_value_caped = (rx_gain_value_caped & 3478250003Sadrian (0xFFFFFF00)) + rf_gain_cap; 3479250003Sadrian } 3480250003Sadrian a_Byte = rx_gain_value & (0x0000FF00); 3481250003Sadrian if ( a_Byte > ( rf_gain_cap << 8 ) ) 3482250003Sadrian { 3483250003Sadrian rx_gain_value_caped = (rx_gain_value_caped & 3484250003Sadrian (0xFFFF00FF)) + (rf_gain_cap<<8); 3485250003Sadrian } 3486250003Sadrian a_Byte = rx_gain_value & (0x00FF0000); 3487250003Sadrian if ( a_Byte > ( rf_gain_cap << 16 ) ) 3488250003Sadrian { 3489250003Sadrian rx_gain_value_caped = (rx_gain_value_caped & 3490250003Sadrian (0xFF00FFFF)) + (rf_gain_cap<<16); 3491250003Sadrian } 3492250003Sadrian a_Byte = rx_gain_value & (0xFF000000); 3493250003Sadrian if ( a_Byte > ( rf_gain_cap << 24 ) ) 3494250003Sadrian { 3495250003Sadrian rx_gain_value_caped = (rx_gain_value_caped & 3496250003Sadrian (0x00FFFFFF)) + (rf_gain_cap<<24); 3497250003Sadrian } 3498250003Sadrian else 3499250003Sadrian { 3500250003Sadrian done = 1; 3501250003Sadrian } 3502250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 3503250003Sadrian "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n", 3504250003Sadrian __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped); 3505250003Sadrian if (rx_gain_value_caped != rx_gain_value) 3506250003Sadrian { 3507250003Sadrian rx_gain_table[i_rx_gain][1] = rx_gain_value_caped; 3508250003Sadrian } 3509250003Sadrian if (done == 1) 3510250003Sadrian break; 3511250003Sadrian i_rx_gain ++; 3512250003Sadrian } 3513250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2); 3514250003Sadrian return AH_TRUE; 3515250003Sadrian} 3516250003Sadrian 3517250003Sadrian 3518250003Sadrianvoid ar9300_rx_gain_table_apply(struct ath_hal *ah) 3519250003Sadrian{ 3520250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3521250008Sadrian//struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 3522250003Sadrian u_int32_t xlan_gpio_cfg; 3523250003Sadrian u_int8_t i; 3524250003Sadrian 3525250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah)) 3526250003Sadrian { 3527250003Sadrian // this will be called if rxGainTable setting is changed 3528250003Sadrian if (ar9300_rf_gain_cap_apply(ah, 1)) 3529250003Sadrian return; 3530250003Sadrian } 3531250003Sadrian 3532250003Sadrian switch (ar9300_rx_gain_index_get(ah)) 3533250003Sadrian { 3534250003Sadrian case 2: 3535250003Sadrian if (AR_SREV_JUPITER_10(ah)) { 3536250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3537250003Sadrian ar9300_common_mixed_rx_gain_table_jupiter_1p0, 3538250003Sadrian ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2); 3539250003Sadrian break; 3540301421Sadrian } 3541250003Sadrian else if (AR_SREV_JUPITER_20(ah)) { 3542250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3543250003Sadrian ar9300Common_mixed_rx_gain_table_jupiter_2p0, 3544250003Sadrian ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2); 3545301423Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_core, 3546301423Sadrian ar9462_2p0_baseband_core_mix_rxgain, 3547301423Sadrian ARRAY_LENGTH(ar9462_2p0_baseband_core_mix_rxgain), 2); 3548301423Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_postamble, 3549301423Sadrian ar9462_2p0_baseband_postamble_mix_rxgain, 3550301423Sadrian ARRAY_LENGTH(ar9462_2p0_baseband_postamble_mix_rxgain), 2); 3551301423Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna, 3552301423Sadrian ar9462_2p0_baseband_postamble_5g_xlna, 3553301423Sadrian ARRAY_LENGTH(ar9462_2p0_baseband_postamble_5g_xlna), 2); 3554250003Sadrian break; 3555250003Sadrian } 3556301421Sadrian else if (AR_SREV_JUPITER_21(ah)) { 3557301421Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3558301421Sadrian ar9462_2p1_common_mixed_rx_gain, 3559301421Sadrian ARRAY_LENGTH(ar9462_2p1_common_mixed_rx_gain), 2); 3560301423Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_core, 3561301423Sadrian ar9462_2p1_baseband_core_mix_rxgain, 3562301423Sadrian ARRAY_LENGTH(ar9462_2p1_baseband_core_mix_rxgain), 2); 3563301423Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_postamble, 3564301423Sadrian ar9462_2p1_baseband_postamble_mix_rxgain, 3565301423Sadrian ARRAY_LENGTH(ar9462_2p1_baseband_postamble_mix_rxgain), 2); 3566301423Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna, 3567301423Sadrian ar9462_2p1_baseband_postamble_5g_xlna, 3568301423Sadrian ARRAY_LENGTH(ar9462_2p1_baseband_postamble_5g_xlna), 2); 3569301423Sadrian 3570301421Sadrian break; 3571301421Sadrian } 3572301423Sadrian case 3: 3573301423Sadrian if (AR_SREV_JUPITER_21(ah)) { 3574301423Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3575301423Sadrian ar9462_2p1_common_5g_xlna_only_rxgain, 3576301423Sadrian ARRAY_LENGTH(ar9462_2p1_common_5g_xlna_only_rxgain), 2); 3577301423Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna, 3578301423Sadrian ar9462_2p1_baseband_postamble_5g_xlna, 3579301423Sadrian ARRAY_LENGTH(ar9462_2p1_baseband_postamble_5g_xlna), 2); 3580301423Sadrian } else if (AR_SREV_JUPITER_20(ah)) { 3581301423Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3582301423Sadrian ar9462_2p0_common_5g_xlna_only_rxgain, 3583301423Sadrian ARRAY_LENGTH(ar9462_2p0_common_5g_xlna_only_rxgain), 2); 3584301423Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna, 3585301423Sadrian ar9462_2p0_baseband_postamble_5g_xlna, 3586301423Sadrian ARRAY_LENGTH(ar9462_2p0_baseband_postamble_5g_xlna), 2); 3587301423Sadrian } 3588301423Sadrian break; 3589250003Sadrian case 0: 3590250003Sadrian default: 3591250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3592250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3593250003Sadrian ar9331_common_rx_gain_hornet1_2, 3594250003Sadrian ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 3595250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3596250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3597250003Sadrian ar9331_common_rx_gain_hornet1_1, 3598250003Sadrian ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 3599250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3600250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3601250003Sadrian ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3602250003Sadrian ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3603250008Sadrian /* XXX FreeBSD: this needs to be revisited!! */ 3604250008Sadrian xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio; 3605250003Sadrian if (xlan_gpio_cfg) { 3606250003Sadrian for (i = 0; i < 32; i++) { 3607250003Sadrian if (xlan_gpio_cfg & (1 << i)) { 3608250008Sadrian /* 3609250008Sadrian * XXX FreeBSD: definitely make sure this 3610250008Sadrian * results in the correct value being written 3611250008Sadrian * to the hardware, or weird crap is very likely 3612250008Sadrian * to occur! 3613250008Sadrian */ 3614250008Sadrian ath_hal_gpioCfgOutput(ah, i, 3615250008Sadrian HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED); 3616250003Sadrian } 3617250003Sadrian } 3618250008Sadrian } 3619250003Sadrian 3620250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3621250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3622250003Sadrian ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3623250003Sadrian ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3624250003Sadrian } else if (AR_SREV_JUPITER_10(ah)) { 3625250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3626250003Sadrian ar9300_common_rx_gain_table_jupiter_1p0, 3627250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 3628250003Sadrian } else if (AR_SREV_JUPITER_20(ah)) { 3629250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3630250003Sadrian ar9300Common_rx_gain_table_jupiter_2p0, 3631250003Sadrian ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 3632301421Sadrian } else if (AR_SREV_JUPITER_21(ah)) { 3633301421Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3634301421Sadrian ar9462_2p1_common_rx_gain, 3635301421Sadrian ARRAY_LENGTH(ar9462_2p1_common_rx_gain), 2); 3636250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3637250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3638250003Sadrian ar9300_common_rx_gain_table_ar9580_1p0, 3639250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 3640250003Sadrian } else if (AR_SREV_WASP(ah)) { 3641250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3642250003Sadrian ar9340Common_rx_gain_table_wasp_1p0, 3643250003Sadrian ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2); 3644250003Sadrian } else if (AR_SREV_SCORPION(ah)) { 3645250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3646250003Sadrian ar955xCommon_rx_gain_table_scorpion_1p0, 3647250003Sadrian ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2); 3648250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3649250003Sadrian ar955xCommon_rx_gain_bounds_scorpion_1p0, 3650250003Sadrian ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5); 3651291437Sadrian } else if (AR_SREV_HONEYBEE(ah)) { 3652291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3653291437Sadrian qca953xCommon_rx_gain_table_honeybee_1p0, 3654291437Sadrian ARRAY_LENGTH(qca953xCommon_rx_gain_table_honeybee_1p0), 2); 3655291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3656291437Sadrian qca953xCommon_rx_gain_bounds_honeybee_1p0, 3657291437Sadrian ARRAY_LENGTH(qca953xCommon_rx_gain_bounds_honeybee_1p0), 5); 3658250003Sadrian } else { 3659250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3660250003Sadrian ar9300_common_rx_gain_table_osprey_2p2, 3661250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 3662250003Sadrian } 3663250003Sadrian break; 3664250003Sadrian case 1: 3665250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3666250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3667250003Sadrian ar9331_common_wo_xlna_rx_gain_hornet1_2, 3668250003Sadrian ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2); 3669250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3670250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3671250003Sadrian ar9331_common_wo_xlna_rx_gain_hornet1_1, 3672250003Sadrian ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2); 3673250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3674250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3675250003Sadrian ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3676250003Sadrian ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3677250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3678250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3679250003Sadrian ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3680250003Sadrian ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3681250003Sadrian } else if (AR_SREV_JUPITER_10(ah)) { 3682250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3683250003Sadrian ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0, 3684250003Sadrian ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0), 3685250003Sadrian 2); 3686250003Sadrian } else if (AR_SREV_JUPITER_20(ah)) { 3687250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3688250003Sadrian ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0, 3689250003Sadrian ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0), 3690250003Sadrian 2); 3691301421Sadrian } else if (AR_SREV_JUPITER_21(ah)) { 3692301421Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3693301421Sadrian ar9462_2p1_common_wo_xlna_rx_gain, 3694301421Sadrian ARRAY_LENGTH(ar9462_2p1_common_wo_xlna_rx_gain), 3695301421Sadrian 2); 3696250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 3697250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3698250003Sadrian ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0, 3699250003Sadrian ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0), 3700250003Sadrian 2); 3701250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3702250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3703250003Sadrian ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0, 3704250003Sadrian ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2); 3705250003Sadrian } else if (AR_SREV_WASP(ah)) { 3706250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3707250003Sadrian ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 3708250003Sadrian ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 3709250003Sadrian } else if (AR_SREV_SCORPION(ah)) { 3710250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3711250003Sadrian ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 3712250003Sadrian ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 3713250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3714250003Sadrian ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 3715250003Sadrian ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 3716291437Sadrian } else if (AR_SREV_HONEYBEE(ah)) { 3717291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3718291437Sadrian qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0, 3719291437Sadrian ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0), 2); 3720291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3721291437Sadrian qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0, 3722291437Sadrian ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0), 5); 3723250003Sadrian } else { 3724250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3725250003Sadrian ar9300Common_wo_xlna_rx_gain_table_osprey_2p2, 3726250003Sadrian ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2); 3727250003Sadrian } 3728250003Sadrian break; 3729250003Sadrian } 3730250003Sadrian} 3731250003Sadrian 3732250003Sadrianvoid ar9300_tx_gain_table_apply(struct ath_hal *ah) 3733250003Sadrian{ 3734250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3735250003Sadrian 3736250003Sadrian switch (ar9300_tx_gain_index_get(ah)) 3737250003Sadrian { 3738250003Sadrian case 0: 3739250003Sadrian default: 3740250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3741250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3742250003Sadrian ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 3743250003Sadrian ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 3744250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3745250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3746250003Sadrian ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 3747250003Sadrian ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 3748250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3749250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3750250003Sadrian ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 3751250003Sadrian ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 3752250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3753250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3754250003Sadrian ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 3755250003Sadrian ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 3756250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3757250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3758250003Sadrian ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 3759250003Sadrian ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 3760250003Sadrian 5); 3761250003Sadrian } else if (AR_SREV_WASP(ah)) { 3762250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3763250003Sadrian ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0, 3764250003Sadrian ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0), 3765250003Sadrian 5); 3766250003Sadrian } else if (AR_SREV_SCORPION(ah)) { 3767250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3768250003Sadrian ar955xModes_xpa_tx_gain_table_scorpion_1p0, 3769250003Sadrian ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0), 3770250003Sadrian 9); 3771250003Sadrian } else if (AR_SREV_JUPITER_10(ah)) { 3772250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3773250003Sadrian ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0, 3774250003Sadrian ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0), 3775250003Sadrian 5); 3776301421Sadrian } else if (AR_SREV_JUPITER_20(ah)) { 3777250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3778250003Sadrian ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0, 3779250003Sadrian ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0), 3780250003Sadrian 5); 3781301421Sadrian } else if (AR_SREV_JUPITER_21(ah)) { 3782301421Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3783301421Sadrian ar9462_2p1_modes_low_ob_db_tx_gain, 3784301421Sadrian ARRAY_LENGTH(ar9462_2p1_modes_low_ob_db_tx_gain), 3785301421Sadrian 5); 3786291437Sadrian } else if (AR_SREV_HONEYBEE(ah)) { 3787291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3788291437Sadrian qca953xModes_xpa_tx_gain_table_honeybee_1p0, 3789291437Sadrian ARRAY_LENGTH(qca953xModes_xpa_tx_gain_table_honeybee_1p0), 3790291437Sadrian 2); 3791250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 3792250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3793250003Sadrian ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3794250003Sadrian ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 3795250003Sadrian 5); 3796250003Sadrian } else { 3797250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3798250003Sadrian ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 3799250003Sadrian ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 3800250003Sadrian 5); 3801250003Sadrian } 3802250003Sadrian break; 3803250003Sadrian case 1: 3804250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3805250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3806250003Sadrian ar9331_modes_high_ob_db_tx_gain_hornet1_2, 3807250003Sadrian ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5); 3808250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3809250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3810250003Sadrian ar9331_modes_high_ob_db_tx_gain_hornet1_1, 3811250003Sadrian ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5); 3812250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3813250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3814250003Sadrian ar9485_modes_high_ob_db_tx_gain_poseidon1_1, 3815250003Sadrian ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5); 3816250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3817250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3818250003Sadrian ar9485Modes_high_ob_db_tx_gain_poseidon1_0, 3819250003Sadrian ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5); 3820250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3821250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3822250003Sadrian ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0, 3823250003Sadrian ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0), 3824250003Sadrian 5); 3825250003Sadrian } else if (AR_SREV_WASP(ah)) { 3826250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3827250003Sadrian ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 3828250003Sadrian ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 3829250003Sadrian } else if (AR_SREV_SCORPION(ah)) { 3830250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3831250003Sadrian ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 3832250003Sadrian ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9); 3833250003Sadrian } else if (AR_SREV_JUPITER_10(ah)) { 3834250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3835250003Sadrian ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0, 3836250003Sadrian ARRAY_LENGTH( 3837250003Sadrian ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5); 3838250003Sadrian } else if (AR_SREV_JUPITER_20(ah)) { 3839250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3840250003Sadrian ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0, 3841250003Sadrian ARRAY_LENGTH( 3842250003Sadrian ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5); 3843301421Sadrian } else if (AR_SREV_JUPITER_21(ah)) { 3844301421Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3845301421Sadrian ar9462_2p1_modes_high_ob_db_tx_gain, 3846301421Sadrian ARRAY_LENGTH( 3847301421Sadrian ar9462_2p1_modes_high_ob_db_tx_gain), 5); 3848250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 3849250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3850250003Sadrian ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0, 3851250003Sadrian ARRAY_LENGTH( 3852250003Sadrian ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5); 3853291437Sadrian } else if (AR_SREV_HONEYBEE(ah)) { 3854291437Sadrian if (AR_SREV_HONEYBEE_11(ah)) { 3855291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3856291437Sadrian qca953xModes_no_xpa_tx_gain_table_honeybee_1p1, 3857291437Sadrian ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p1), 2); 3858291437Sadrian } else { 3859291437Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3860291437Sadrian qca953xModes_no_xpa_tx_gain_table_honeybee_1p0, 3861291437Sadrian ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p0), 2); 3862291437Sadrian } 3863250003Sadrian } else { 3864250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3865250003Sadrian ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2, 3866250003Sadrian ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2), 3867250003Sadrian 5); 3868250003Sadrian } 3869250003Sadrian break; 3870250003Sadrian case 2: 3871250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3872250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3873250003Sadrian ar9331_modes_low_ob_db_tx_gain_hornet1_2, 3874250003Sadrian ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5); 3875250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3876250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3877250003Sadrian ar9331_modes_low_ob_db_tx_gain_hornet1_1, 3878250003Sadrian ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5); 3879250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3880250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3881250003Sadrian ar9485_modes_low_ob_db_tx_gain_poseidon1_1, 3882250003Sadrian ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5); 3883250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3884250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3885250003Sadrian ar9485Modes_low_ob_db_tx_gain_poseidon1_0, 3886250003Sadrian ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5); 3887250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3888250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3889250003Sadrian ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0, 3890250003Sadrian ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0), 3891250003Sadrian 5); 3892250003Sadrian } else if (AR_SREV_WASP(ah)) { 3893250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3894250003Sadrian ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0, 3895250003Sadrian ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5); 3896250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 3897250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3898250003Sadrian ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3899250003Sadrian ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); 3900250003Sadrian } else { 3901250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3902250003Sadrian ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2, 3903250003Sadrian ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2), 3904250003Sadrian 5); 3905250003Sadrian } 3906250003Sadrian break; 3907250003Sadrian case 3: 3908250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3909250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3910250003Sadrian ar9331_modes_high_power_tx_gain_hornet1_2, 3911250003Sadrian ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5); 3912250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3913250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3914250003Sadrian ar9331_modes_high_power_tx_gain_hornet1_1, 3915250003Sadrian ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5); 3916250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3917250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3918250003Sadrian ar9485_modes_high_power_tx_gain_poseidon1_1, 3919250003Sadrian ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5); 3920250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3921250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3922250003Sadrian ar9485Modes_high_power_tx_gain_poseidon1_0, 3923250003Sadrian ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5); 3924250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3925250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3926250003Sadrian ar9300Modes_high_power_tx_gain_table_ar9580_1p0, 3927250003Sadrian ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0), 3928250003Sadrian 5); 3929250003Sadrian } else if (AR_SREV_WASP(ah)) { 3930250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3931250003Sadrian ar9340Modes_high_power_tx_gain_table_wasp_1p0, 3932250003Sadrian ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0), 3933250003Sadrian 5); 3934250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 3935250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3936250003Sadrian ar956XModes_high_power_tx_gain_table_aphrodite_1p0, 3937250003Sadrian ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5); 3938250003Sadrian } else { 3939250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3940250003Sadrian ar9300Modes_high_power_tx_gain_table_osprey_2p2, 3941250003Sadrian ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2), 3942250003Sadrian 5); 3943250003Sadrian } 3944250003Sadrian break; 3945250003Sadrian case 4: 3946250003Sadrian if (AR_SREV_WASP(ah)) { 3947250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3948250003Sadrian ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0, 3949250003Sadrian ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0), 3950250003Sadrian 5); 3951250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3952250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3953250003Sadrian ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0, 3954250003Sadrian ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0), 3955250003Sadrian 5); 3956250003Sadrian } else { 3957250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3958250003Sadrian ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2, 3959250003Sadrian ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2), 3960250003Sadrian 5); 3961250003Sadrian } 3962250003Sadrian break; 3963250003Sadrian case 5: 3964250003Sadrian /* HW Green TX */ 3965250003Sadrian if (AR_SREV_POSEIDON(ah)) { 3966250003Sadrian if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3967250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3968250003Sadrian ar9485_modes_green_ob_db_tx_gain_poseidon1_1, 3969250003Sadrian sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) / 3970250003Sadrian sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5); 3971250003Sadrian } else { 3972250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3973250003Sadrian ar9485_modes_green_ob_db_tx_gain_poseidon1_0, 3974250003Sadrian sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) / 3975250003Sadrian sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5); 3976250003Sadrian } 3977250003Sadrian ahp->ah_hw_green_tx_enable = 1; 3978250003Sadrian } 3979250003Sadrian else if (AR_SREV_WASP(ah)) { 3980250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3981250003Sadrian ar9340_modes_ub124_tx_gain_table_wasp_1p0, 3982250003Sadrian sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) / 3983250003Sadrian sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5); 3984250003Sadrian } 3985250003Sadrian else if (AR_SREV_AR9580(ah)) { 3986250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3987250003Sadrian ar9300_modes_type5_tx_gain_table_ar9580_1p0, 3988250003Sadrian ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0), 3989250003Sadrian 5); 3990250003Sadrian } 3991250003Sadrian else if (AR_SREV_OSPREY_22(ah)) { 3992250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3993250003Sadrian ar9300_modes_number_5_tx_gain_table_osprey_2p2, 3994250003Sadrian ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2), 3995250003Sadrian 5); 3996250003Sadrian } 3997250003Sadrian break; 3998250003Sadrian case 6: 3999250003Sadrian if (AR_SREV_WASP(ah)) { 4000250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 4001250003Sadrian ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0, 4002250003Sadrian sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) / 4003250003Sadrian sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5); 4004250003Sadrian } 4005250003Sadrian /* HW Green TX */ 4006250003Sadrian else if (AR_SREV_POSEIDON(ah)) { 4007250003Sadrian if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 4008250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 4009250003Sadrian ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1, 4010250003Sadrian sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) / 4011250003Sadrian sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]), 4012250003Sadrian 5); 4013250003Sadrian } 4014250003Sadrian ahp->ah_hw_green_tx_enable = 1; 4015250003Sadrian } 4016250003Sadrian else if (AR_SREV_AR9580(ah)) { 4017250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 4018250003Sadrian ar9300_modes_type6_tx_gain_table_ar9580_1p0, 4019250003Sadrian ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0), 4020250003Sadrian 5); 4021250003Sadrian } 4022250003Sadrian break; 4023250003Sadrian case 7: 4024250003Sadrian if (AR_SREV_WASP(ah)) { 4025250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 4026250003Sadrian ar9340Modes_cus227_tx_gain_table_wasp_1p0, 4027250003Sadrian sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) / 4028250003Sadrian sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5); 4029250003Sadrian } 4030250003Sadrian break; 4031250003Sadrian } 4032250003Sadrian} 4033250003Sadrian 4034250003Sadrian#if ATH_ANT_DIV_COMB 4035250003Sadrianvoid 4036250003Sadrianar9300_ant_div_comb_get_config(struct ath_hal *ah, 4037250003Sadrian HAL_ANT_COMB_CONFIG *div_comb_conf) 4038250003Sadrian{ 4039250003Sadrian u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 4040250003Sadrian div_comb_conf->main_lna_conf = 4041250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val); 4042250003Sadrian div_comb_conf->alt_lna_conf = 4043250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val); 4044250003Sadrian div_comb_conf->fast_div_bias = 4045250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val); 4046250003Sadrian if (AR_SREV_HORNET_11(ah)) { 4047250003Sadrian div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1; 4048250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 4049250003Sadrian div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2; 4050250003Sadrian } else { 4051250003Sadrian div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP; 4052250003Sadrian } 4053272292Sadrian 4054272292Sadrian /* 4055272292Sadrian * XXX TODO: allow the HAL to override the rssithres and fast_div_bias 4056272292Sadrian * values (eg CUS198.) 4057272292Sadrian */ 4058250003Sadrian} 4059250003Sadrian 4060250003Sadrianvoid 4061250003Sadrianar9300_ant_div_comb_set_config(struct ath_hal *ah, 4062250003Sadrian HAL_ANT_COMB_CONFIG *div_comb_conf) 4063250003Sadrian{ 4064250003Sadrian u_int32_t reg_val; 4065250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 4066250003Sadrian 4067250003Sadrian /* DO NOTHING when set to fixed antenna for manufacturing purpose */ 4068250003Sadrian if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A 4069250003Sadrian || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) { 4070250003Sadrian return; 4071250003Sadrian } 4072250003Sadrian reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 4073250003Sadrian reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | 4074250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | 4075250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | 4076250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | 4077250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); 4078250003Sadrian reg_val |= 4079250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE( 4080250003Sadrian div_comb_conf->main_gaintb); 4081250003Sadrian reg_val |= 4082250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE( 4083250003Sadrian div_comb_conf->alt_gaintb); 4084250003Sadrian reg_val |= 4085250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE( 4086250003Sadrian div_comb_conf->main_lna_conf); 4087250003Sadrian reg_val |= 4088250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE( 4089250003Sadrian div_comb_conf->alt_lna_conf); 4090250003Sadrian reg_val |= 4091250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE( 4092250003Sadrian div_comb_conf->fast_div_bias); 4093250003Sadrian OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); 4094250003Sadrian 4095250003Sadrian} 4096250003Sadrian#endif /* ATH_ANT_DIV_COMB */ 4097250003Sadrian 4098250003Sadrianstatic void 4099250003Sadrianar9300_init_hostif_offsets(struct ath_hal *ah) 4100250003Sadrian{ 4101250003Sadrian AR_HOSTIF_REG(ah, AR_RC) = 4102250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 4103250003Sadrian AR_HOSTIF_REG(ah, AR_WA) = 4104250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 4105250003Sadrian AR_HOSTIF_REG(ah, AR_PM_STATE) = 4106250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE); 4107250003Sadrian AR_HOSTIF_REG(ah, AR_H_INFOL) = 4108250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL); 4109250003Sadrian AR_HOSTIF_REG(ah, AR_H_INFOH) = 4110250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH); 4111250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 4112250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 4113250003Sadrian AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 4114250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 4115250003Sadrian AR_HOSTIF_REG(ah, AR_EEPROM) = 4116250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL); 4117250003Sadrian AR_HOSTIF_REG(ah, AR_SREV) = 4118250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_SREV); 4119250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 4120250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4121250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 4122250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4123250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 4124250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 4125250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 4126250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 4127250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 4128250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 4129250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 4130250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4131250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 4132250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4133250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 4134250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4135250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_SERDES) = 4136250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW); 4137250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) = 4138250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD); 4139250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4140250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4141250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4142250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4143250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4144250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4145250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4146250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4147250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4148250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4149250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4150250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4151250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4152250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4153250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4154250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4155250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4156250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4157250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4158250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4159250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4160250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4161250003Sadrian AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4162250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4163250003Sadrian AR_HOSTIF_REG(ah, AR_SPARE) = 4164250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE); 4165250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) = 4166250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN); 4167250003Sadrian AR_HOSTIF_REG(ah, AR_CLKRUN) = 4168250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4169250003Sadrian AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4170250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4171250003Sadrian AR_HOSTIF_REG(ah, AR_OBS) = 4172250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4173250003Sadrian AR_HOSTIF_REG(ah, AR_RFSILENT) = 4174250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4175250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_PDPU) = 4176250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU); 4177250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_DS) = 4178250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS); 4179250003Sadrian AR_HOSTIF_REG(ah, AR_MISC) = 4180250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_MISC); 4181250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4182250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4183250003Sadrian#if 0 /* Offsets are not defined in reg_map structure */ 4184250003Sadrian AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) = 4185250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE); 4186250003Sadrian AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) = 4187250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY); 4188250003Sadrian AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) = 4189250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL); 4190250003Sadrian#endif 4191250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) = 4192250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ); 4193250003Sadrian AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4194250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4195250003Sadrian AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4196250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4197250003Sadrian AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4198250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4199250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4200250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4201250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4202250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4203250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4204250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4205250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4206250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4207250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4208250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4209250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4210250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4211250003Sadrian} 4212250003Sadrian 4213250003Sadrianstatic void 4214250003Sadrianar9340_init_hostif_offsets(struct ath_hal *ah) 4215250003Sadrian{ 4216250003Sadrian AR_HOSTIF_REG(ah, AR_RC) = 4217250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 4218250003Sadrian AR_HOSTIF_REG(ah, AR_WA) = 4219250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 4220250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 4221250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 4222250003Sadrian AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 4223250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 4224250003Sadrian AR_HOSTIF_REG(ah, AR_SREV) = 4225250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_SREV); 4226250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 4227250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4228250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 4229250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4230250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 4231250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 4232250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 4233250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 4234250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 4235250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 4236250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 4237250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4238250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 4239250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4240250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 4241250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4242250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4243250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4244250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4245250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4246250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4247250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4248250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4249250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4250250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4251250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4252250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4253250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4254250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4255250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4256250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4257250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4258250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4259250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4260250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4261250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4262250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4263250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4264250003Sadrian AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4265250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4266250003Sadrian AR_HOSTIF_REG(ah, AR_CLKRUN) = 4267250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4268250003Sadrian AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4269250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4270250003Sadrian AR_HOSTIF_REG(ah, AR_OBS) = 4271250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4272250003Sadrian AR_HOSTIF_REG(ah, AR_RFSILENT) = 4273250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4274250003Sadrian AR_HOSTIF_REG(ah, AR_MISC) = 4275250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_MISC); 4276250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4277250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4278250003Sadrian AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4279250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4280250003Sadrian AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4281250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4282250003Sadrian AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4283250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4284250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4285250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4286250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4287250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4288250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4289250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4290250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4291250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4292250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4293250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4294250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4295250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4296250003Sadrian} 4297250003Sadrian 4298250003Sadrian/* 4299250003Sadrian * Host interface register offsets are different for Osprey and Wasp 4300250003Sadrian * and hence store the offsets in hal structure 4301250003Sadrian */ 4302250003Sadrianstatic int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid) 4303250003Sadrian{ 4304250003Sadrian if (devid == AR9300_DEVID_AR9340) { 4305250003Sadrian ar9340_init_hostif_offsets(ah); 4306250003Sadrian } else { 4307250003Sadrian ar9300_init_hostif_offsets(ah); 4308250003Sadrian } 4309250003Sadrian return 0; 4310250003Sadrian} 4311250003Sadrian 4312250008Sadrian 4313250008Sadrianstatic const char* 4314250008Sadrianar9300_probe(uint16_t vendorid, uint16_t devid) 4315250008Sadrian{ 4316250008Sadrian if (vendorid != ATHEROS_VENDOR_ID) 4317250008Sadrian return AH_NULL; 4318250008Sadrian 4319250008Sadrian switch (devid) { 4320250008Sadrian case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */ 4321250008Sadrian return "Atheros AR938x"; 4322250008Sadrian case AR9300_DEVID_AR9340: /* Wasp */ 4323250008Sadrian return "Atheros AR934x"; 4324250008Sadrian case AR9300_DEVID_AR9485_PCIE: /* Poseidon */ 4325250008Sadrian return "Atheros AR9485"; 4326250008Sadrian case AR9300_DEVID_AR9580_PCIE: /* Peacock */ 4327250008Sadrian return "Atheros AR9580"; 4328250008Sadrian case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */ 4329250008Sadrian return "Atheros AR946x/AR948x"; 4330250008Sadrian case AR9300_DEVID_AR9330: /* Hornet */ 4331250008Sadrian return "Atheros AR933x"; 4332250008Sadrian case AR9300_DEVID_QCA955X: /* Scorpion */ 4333250008Sadrian return "Qualcomm Atheros QCA955x"; 4334250166Sadrian case AR9300_DEVID_QCA9565: /* Aphrodite */ 4335250166Sadrian return "Qualcomm Atheros AR9565"; 4336291437Sadrian case AR9300_DEVID_QCA953X: /* Honeybee */ 4337291437Sadrian return "Qualcomm Atheros QCA953x"; 4338265348Sadrian case AR9300_DEVID_AR1111_PCIE: 4339265348Sadrian return "Atheros AR1111"; 4340250008Sadrian default: 4341250008Sadrian return AH_NULL; 4342250008Sadrian } 4343250008Sadrian 4344250008Sadrian return AH_NULL; 4345250008Sadrian} 4346250008Sadrian 4347250008SadrianAH_CHIP(AR9300, ar9300_probe, ar9300_attach); 4348250008Sadrian 4349