1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2006 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17204644Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5211REG_H 20185377Ssam#define _DEV_ATH_AR5211REG_H 21185377Ssam 22185377Ssam/* 23185377Ssam * Definitions for the Atheros AR5211/5311 chipset. 24185377Ssam */ 25185377Ssam 26185377Ssam/* 27185377Ssam * Maui2/Spirit specific registers/fields are indicated by AR5311. 28185377Ssam * Oahu specific registers/fields are indicated by AR5211. 29185377Ssam */ 30185377Ssam 31185377Ssam/* DMA Control and Interrupt Registers */ 32185377Ssam#define AR_CR 0x0008 /* control register */ 33185377Ssam#define AR_RXDP 0x000C /* receive queue descriptor pointer */ 34185377Ssam#define AR_CFG 0x0014 /* configuration and status register */ 35185377Ssam#define AR_IER 0x0024 /* Interrupt enable register */ 36185377Ssam#define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */ 37185377Ssam#define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */ 38185377Ssam#define AR_TXCFG 0x0030 /* tx DMA size config register */ 39185377Ssam#define AR_RXCFG 0x0034 /* rx DMA size config register */ 40185377Ssam#define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */ 41185377Ssam#define AR_MIBC 0x0040 /* MIB control register */ 42185377Ssam#define AR_TOPS 0x0044 /* timeout prescale count */ 43185377Ssam#define AR_RXNPTO 0x0048 /* no frame received timeout */ 44185377Ssam#define AR_TXNPTO 0x004C /* no frame trasmitted timeout */ 45185377Ssam#define AR_RFGTO 0x0050 /* receive frame gap timeout */ 46185377Ssam#define AR_RFCNT 0x0054 /* receive frame count limit */ 47185377Ssam#define AR_MACMISC 0x0058 /* miscellaneous control/status */ 48185377Ssam#define AR5311_QDCLKGATE 0x005c /* QCU/DCU clock gating control */ 49185377Ssam#define AR_ISR 0x0080 /* Primary interrupt status register */ 50185377Ssam#define AR_ISR_S0 0x0084 /* Secondary interrupt status reg 0 */ 51185377Ssam#define AR_ISR_S1 0x0088 /* Secondary interrupt status reg 1 */ 52185377Ssam#define AR_ISR_S2 0x008c /* Secondary interrupt status reg 2 */ 53185377Ssam#define AR_ISR_S3 0x0090 /* Secondary interrupt status reg 3 */ 54185377Ssam#define AR_ISR_S4 0x0094 /* Secondary interrupt status reg 4 */ 55185377Ssam#define AR_IMR 0x00a0 /* Primary interrupt mask register */ 56185377Ssam#define AR_IMR_S0 0x00a4 /* Secondary interrupt mask reg 0 */ 57185377Ssam#define AR_IMR_S1 0x00a8 /* Secondary interrupt mask reg 1 */ 58185377Ssam#define AR_IMR_S2 0x00ac /* Secondary interrupt mask reg 2 */ 59185377Ssam#define AR_IMR_S3 0x00b0 /* Secondary interrupt mask reg 3 */ 60185377Ssam#define AR_IMR_S4 0x00b4 /* Secondary interrupt mask reg 4 */ 61185377Ssam#define AR_ISR_RAC 0x00c0 /* Primary interrupt status reg, */ 62185377Ssam/* Shadow copies with read-and-clear access */ 63185377Ssam#define AR_ISR_S0_S 0x00c4 /* Secondary interrupt status reg 0 */ 64185377Ssam#define AR_ISR_S1_S 0x00c8 /* Secondary interrupt status reg 1 */ 65185377Ssam#define AR_ISR_S2_S 0x00cc /* Secondary interrupt status reg 2 */ 66185377Ssam#define AR_ISR_S3_S 0x00d0 /* Secondary interrupt status reg 3 */ 67185377Ssam#define AR_ISR_S4_S 0x00d4 /* Secondary interrupt status reg 4 */ 68185377Ssam 69185377Ssam#define AR_Q0_TXDP 0x0800 /* Transmit Queue descriptor pointer */ 70185377Ssam#define AR_Q1_TXDP 0x0804 /* Transmit Queue descriptor pointer */ 71185377Ssam#define AR_Q2_TXDP 0x0808 /* Transmit Queue descriptor pointer */ 72185377Ssam#define AR_Q3_TXDP 0x080c /* Transmit Queue descriptor pointer */ 73185377Ssam#define AR_Q4_TXDP 0x0810 /* Transmit Queue descriptor pointer */ 74185377Ssam#define AR_Q5_TXDP 0x0814 /* Transmit Queue descriptor pointer */ 75185377Ssam#define AR_Q6_TXDP 0x0818 /* Transmit Queue descriptor pointer */ 76185377Ssam#define AR_Q7_TXDP 0x081c /* Transmit Queue descriptor pointer */ 77185377Ssam#define AR_Q8_TXDP 0x0820 /* Transmit Queue descriptor pointer */ 78185377Ssam#define AR_Q9_TXDP 0x0824 /* Transmit Queue descriptor pointer */ 79185377Ssam#define AR_QTXDP(i) (AR_Q0_TXDP + ((i)<<2)) 80185377Ssam 81185377Ssam#define AR_Q_TXE 0x0840 /* Transmit Queue enable */ 82185377Ssam#define AR_Q_TXD 0x0880 /* Transmit Queue disable */ 83185377Ssam 84185377Ssam#define AR_Q0_CBRCFG 0x08c0 /* CBR configuration */ 85185377Ssam#define AR_Q1_CBRCFG 0x08c4 /* CBR configuration */ 86185377Ssam#define AR_Q2_CBRCFG 0x08c8 /* CBR configuration */ 87185377Ssam#define AR_Q3_CBRCFG 0x08cc /* CBR configuration */ 88185377Ssam#define AR_Q4_CBRCFG 0x08d0 /* CBR configuration */ 89185377Ssam#define AR_Q5_CBRCFG 0x08d4 /* CBR configuration */ 90185377Ssam#define AR_Q6_CBRCFG 0x08d8 /* CBR configuration */ 91185377Ssam#define AR_Q7_CBRCFG 0x08dc /* CBR configuration */ 92185377Ssam#define AR_Q8_CBRCFG 0x08e0 /* CBR configuration */ 93185377Ssam#define AR_Q9_CBRCFG 0x08e4 /* CBR configuration */ 94185377Ssam#define AR_QCBRCFG(i) (AR_Q0_CBRCFG + ((i)<<2)) 95185377Ssam 96185377Ssam#define AR_Q0_RDYTIMECFG 0x0900 /* ReadyTime configuration */ 97185377Ssam#define AR_Q1_RDYTIMECFG 0x0904 /* ReadyTime configuration */ 98185377Ssam#define AR_Q2_RDYTIMECFG 0x0908 /* ReadyTime configuration */ 99185377Ssam#define AR_Q3_RDYTIMECFG 0x090c /* ReadyTime configuration */ 100185377Ssam#define AR_Q4_RDYTIMECFG 0x0910 /* ReadyTime configuration */ 101185377Ssam#define AR_Q5_RDYTIMECFG 0x0914 /* ReadyTime configuration */ 102185377Ssam#define AR_Q6_RDYTIMECFG 0x0918 /* ReadyTime configuration */ 103185377Ssam#define AR_Q7_RDYTIMECFG 0x091c /* ReadyTime configuration */ 104185377Ssam#define AR_Q8_RDYTIMECFG 0x0920 /* ReadyTime configuration */ 105185377Ssam#define AR_Q9_RDYTIMECFG 0x0924 /* ReadyTime configuration */ 106185377Ssam#define AR_QRDYTIMECFG(i) (AR_Q0_RDYTIMECFG + ((i)<<2)) 107185377Ssam 108185377Ssam#define AR_Q_ONESHOTARM_SC 0x0940 /* OneShotArm set control */ 109185377Ssam#define AR_Q_ONESHOTARM_CC 0x0980 /* OneShotArm clear control */ 110185377Ssam 111185377Ssam#define AR_Q0_MISC 0x09c0 /* Miscellaneous QCU settings */ 112185377Ssam#define AR_Q1_MISC 0x09c4 /* Miscellaneous QCU settings */ 113185377Ssam#define AR_Q2_MISC 0x09c8 /* Miscellaneous QCU settings */ 114185377Ssam#define AR_Q3_MISC 0x09cc /* Miscellaneous QCU settings */ 115185377Ssam#define AR_Q4_MISC 0x09d0 /* Miscellaneous QCU settings */ 116185377Ssam#define AR_Q5_MISC 0x09d4 /* Miscellaneous QCU settings */ 117185377Ssam#define AR_Q6_MISC 0x09d8 /* Miscellaneous QCU settings */ 118185377Ssam#define AR_Q7_MISC 0x09dc /* Miscellaneous QCU settings */ 119185377Ssam#define AR_Q8_MISC 0x09e0 /* Miscellaneous QCU settings */ 120185377Ssam#define AR_Q9_MISC 0x09e4 /* Miscellaneous QCU settings */ 121185377Ssam#define AR_QMISC(i) (AR_Q0_MISC + ((i)<<2)) 122185377Ssam 123185377Ssam#define AR_Q0_STS 0x0a00 /* Miscellaneous QCU status */ 124185377Ssam#define AR_Q1_STS 0x0a04 /* Miscellaneous QCU status */ 125185377Ssam#define AR_Q2_STS 0x0a08 /* Miscellaneous QCU status */ 126185377Ssam#define AR_Q3_STS 0x0a0c /* Miscellaneous QCU status */ 127185377Ssam#define AR_Q4_STS 0x0a10 /* Miscellaneous QCU status */ 128185377Ssam#define AR_Q5_STS 0x0a14 /* Miscellaneous QCU status */ 129185377Ssam#define AR_Q6_STS 0x0a18 /* Miscellaneous QCU status */ 130185377Ssam#define AR_Q7_STS 0x0a1c /* Miscellaneous QCU status */ 131185377Ssam#define AR_Q8_STS 0x0a20 /* Miscellaneous QCU status */ 132185377Ssam#define AR_Q9_STS 0x0a24 /* Miscellaneous QCU status */ 133185377Ssam#define AR_QSTS(i) (AR_Q0_STS + ((i)<<2)) 134185377Ssam 135185377Ssam#define AR_Q_RDYTIMESHDN 0x0a40 /* ReadyTimeShutdown status */ 136185377Ssam#define AR_D0_QCUMASK 0x1000 /* QCU Mask */ 137185377Ssam#define AR_D1_QCUMASK 0x1004 /* QCU Mask */ 138185377Ssam#define AR_D2_QCUMASK 0x1008 /* QCU Mask */ 139185377Ssam#define AR_D3_QCUMASK 0x100c /* QCU Mask */ 140185377Ssam#define AR_D4_QCUMASK 0x1010 /* QCU Mask */ 141185377Ssam#define AR_D5_QCUMASK 0x1014 /* QCU Mask */ 142185377Ssam#define AR_D6_QCUMASK 0x1018 /* QCU Mask */ 143185377Ssam#define AR_D7_QCUMASK 0x101c /* QCU Mask */ 144185377Ssam#define AR_D8_QCUMASK 0x1020 /* QCU Mask */ 145185377Ssam#define AR_D9_QCUMASK 0x1024 /* QCU Mask */ 146185377Ssam#define AR_DQCUMASK(i) (AR_D0_QCUMASK + ((i)<<2)) 147185377Ssam 148185377Ssam#define AR_D0_LCL_IFS 0x1040 /* DCU-specific IFS settings */ 149185377Ssam#define AR_D1_LCL_IFS 0x1044 /* DCU-specific IFS settings */ 150185377Ssam#define AR_D2_LCL_IFS 0x1048 /* DCU-specific IFS settings */ 151185377Ssam#define AR_D3_LCL_IFS 0x104c /* DCU-specific IFS settings */ 152185377Ssam#define AR_D4_LCL_IFS 0x1050 /* DCU-specific IFS settings */ 153185377Ssam#define AR_D5_LCL_IFS 0x1054 /* DCU-specific IFS settings */ 154185377Ssam#define AR_D6_LCL_IFS 0x1058 /* DCU-specific IFS settings */ 155185377Ssam#define AR_D7_LCL_IFS 0x105c /* DCU-specific IFS settings */ 156185377Ssam#define AR_D8_LCL_IFS 0x1060 /* DCU-specific IFS settings */ 157185377Ssam#define AR_D9_LCL_IFS 0x1064 /* DCU-specific IFS settings */ 158185377Ssam#define AR_DLCL_IFS(i) (AR_D0_LCL_IFS + ((i)<<2)) 159185377Ssam 160185377Ssam#define AR_D0_RETRY_LIMIT 0x1080 /* Retry limits */ 161185377Ssam#define AR_D1_RETRY_LIMIT 0x1084 /* Retry limits */ 162185377Ssam#define AR_D2_RETRY_LIMIT 0x1088 /* Retry limits */ 163185377Ssam#define AR_D3_RETRY_LIMIT 0x108c /* Retry limits */ 164185377Ssam#define AR_D4_RETRY_LIMIT 0x1090 /* Retry limits */ 165185377Ssam#define AR_D5_RETRY_LIMIT 0x1094 /* Retry limits */ 166185377Ssam#define AR_D6_RETRY_LIMIT 0x1098 /* Retry limits */ 167185377Ssam#define AR_D7_RETRY_LIMIT 0x109c /* Retry limits */ 168185377Ssam#define AR_D8_RETRY_LIMIT 0x10a0 /* Retry limits */ 169185377Ssam#define AR_D9_RETRY_LIMIT 0x10a4 /* Retry limits */ 170185377Ssam#define AR_DRETRY_LIMIT(i) (AR_D0_RETRY_LIMIT + ((i)<<2)) 171185377Ssam 172185377Ssam#define AR_D0_CHNTIME 0x10c0 /* ChannelTime settings */ 173185377Ssam#define AR_D1_CHNTIME 0x10c4 /* ChannelTime settings */ 174185377Ssam#define AR_D2_CHNTIME 0x10c8 /* ChannelTime settings */ 175185377Ssam#define AR_D3_CHNTIME 0x10cc /* ChannelTime settings */ 176185377Ssam#define AR_D4_CHNTIME 0x10d0 /* ChannelTime settings */ 177185377Ssam#define AR_D5_CHNTIME 0x10d4 /* ChannelTime settings */ 178185377Ssam#define AR_D6_CHNTIME 0x10d8 /* ChannelTime settings */ 179185377Ssam#define AR_D7_CHNTIME 0x10dc /* ChannelTime settings */ 180185377Ssam#define AR_D8_CHNTIME 0x10e0 /* ChannelTime settings */ 181185377Ssam#define AR_D9_CHNTIME 0x10e4 /* ChannelTime settings */ 182185377Ssam#define AR_DCHNTIME(i) (AR_D0_CHNTIME + ((i)<<2)) 183185377Ssam 184185377Ssam#define AR_D0_MISC 0x1100 /* Misc DCU-specific settings */ 185185377Ssam#define AR_D1_MISC 0x1104 /* Misc DCU-specific settings */ 186185377Ssam#define AR_D2_MISC 0x1108 /* Misc DCU-specific settings */ 187185377Ssam#define AR_D3_MISC 0x110c /* Misc DCU-specific settings */ 188185377Ssam#define AR_D4_MISC 0x1110 /* Misc DCU-specific settings */ 189185377Ssam#define AR_D5_MISC 0x1114 /* Misc DCU-specific settings */ 190185377Ssam#define AR_D6_MISC 0x1118 /* Misc DCU-specific settings */ 191185377Ssam#define AR_D7_MISC 0x111c /* Misc DCU-specific settings */ 192185377Ssam#define AR_D8_MISC 0x1120 /* Misc DCU-specific settings */ 193185377Ssam#define AR_D9_MISC 0x1124 /* Misc DCU-specific settings */ 194185377Ssam#define AR_DMISC(i) (AR_D0_MISC + ((i)<<2)) 195185377Ssam 196185377Ssam#define AR_D0_SEQNUM 0x1140 /* Frame seqnum control/status */ 197185377Ssam#define AR_D1_SEQNUM 0x1144 /* Frame seqnum control/status */ 198185377Ssam#define AR_D2_SEQNUM 0x1148 /* Frame seqnum control/status */ 199185377Ssam#define AR_D3_SEQNUM 0x114c /* Frame seqnum control/status */ 200185377Ssam#define AR_D4_SEQNUM 0x1150 /* Frame seqnum control/status */ 201185377Ssam#define AR_D5_SEQNUM 0x1154 /* Frame seqnum control/status */ 202185377Ssam#define AR_D6_SEQNUM 0x1158 /* Frame seqnum control/status */ 203185377Ssam#define AR_D7_SEQNUM 0x115c /* Frame seqnum control/status */ 204185377Ssam#define AR_D8_SEQNUM 0x1160 /* Frame seqnum control/status */ 205185377Ssam#define AR_D9_SEQNUM 0x1164 /* Frame seqnum control/status */ 206185377Ssam#define AR_DSEQNUM(i) (AR_D0_SEQNUM + ((i<<2))) 207185377Ssam 208185377Ssam/* MAC DCU-global IFS settings */ 209185377Ssam#define AR_D_GBL_IFS_SIFS 0x1030 /* DCU global SIFS settings */ 210185377Ssam#define AR_D_GBL_IFS_SLOT 0x1070 /* DC global slot interval */ 211185377Ssam#define AR_D_GBL_IFS_EIFS 0x10b0 /* DCU global EIFS setting */ 212185377Ssam#define AR_D_GBL_IFS_MISC 0x10f0 /* DCU global misc. IFS settings */ 213185377Ssam#define AR_D_FPCTL 0x1230 /* DCU frame prefetch settings */ 214185377Ssam#define AR_D_TXPSE 0x1270 /* DCU transmit pause control/status */ 215185377Ssam#define AR_D_TXBLK_CMD 0x1038 /* DCU transmit filter cmd (w/only) */ 216185377Ssam#define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) /* DCU transmit filter data */ 217185377Ssam#define AR_D_TXBLK_CLR 0x143c /* DCU clear tx filter (w/only) */ 218185377Ssam#define AR_D_TXBLK_SET 0x147c /* DCU set tx filter (w/only) */ 219185377Ssam 220185377Ssam#define AR_D_TXPSE 0x1270 /* DCU transmit pause control/status */ 221185377Ssam 222185377Ssam#define AR_RC 0x4000 /* Warm reset control register */ 223185377Ssam#define AR_SCR 0x4004 /* Sleep control register */ 224185377Ssam#define AR_INTPEND 0x4008 /* Interrupt Pending register */ 225185377Ssam#define AR_SFR 0x400C /* Sleep force register */ 226185377Ssam#define AR_PCICFG 0x4010 /* PCI configuration register */ 227185377Ssam#define AR_GPIOCR 0x4014 /* GPIO control register */ 228185377Ssam#define AR_GPIODO 0x4018 /* GPIO data output access register */ 229185377Ssam#define AR_GPIODI 0x401C /* GPIO data input access register */ 230185377Ssam#define AR_SREV 0x4020 /* Silicon Revision register */ 231185377Ssam 232185377Ssam#define AR_EEPROM_ADDR 0x6000 /* EEPROM address register (10 bit) */ 233185377Ssam#define AR_EEPROM_DATA 0x6004 /* EEPROM data register (16 bit) */ 234185377Ssam#define AR_EEPROM_CMD 0x6008 /* EEPROM command register */ 235185377Ssam#define AR_EEPROM_STS 0x600c /* EEPROM status register */ 236185377Ssam#define AR_EEPROM_CFG 0x6010 /* EEPROM configuration register */ 237185377Ssam 238185377Ssam#define AR_STA_ID0 0x8000 /* station ID0 - low 32 bits */ 239185377Ssam#define AR_STA_ID1 0x8004 /* station ID1 - upper 16 bits */ 240185377Ssam#define AR_BSS_ID0 0x8008 /* BSSID low 32 bits */ 241185377Ssam#define AR_BSS_ID1 0x800C /* BSSID upper 16 bits / AID */ 242185377Ssam#define AR_SLOT_TIME 0x8010 /* Time-out after a collision */ 243185377Ssam#define AR_TIME_OUT 0x8014 /* ACK & CTS time-out */ 244185377Ssam#define AR_RSSI_THR 0x8018 /* RSSI warning & missed beacon threshold */ 245185377Ssam#define AR_USEC 0x801c /* transmit latency register */ 246185377Ssam#define AR_BEACON 0x8020 /* beacon control value/mode bits */ 247185377Ssam#define AR_CFP_PERIOD 0x8024 /* CFP Interval (TU/msec) */ 248185377Ssam#define AR_TIMER0 0x8028 /* Next beacon time (TU/msec) */ 249185377Ssam#define AR_TIMER1 0x802c /* DMA beacon alert time (1/8 TU) */ 250185377Ssam#define AR_TIMER2 0x8030 /* Software beacon alert (1/8 TU) */ 251185377Ssam#define AR_TIMER3 0x8034 /* ATIM window time */ 252185377Ssam#define AR_CFP_DUR 0x8038 /* maximum CFP duration in TU */ 253185377Ssam#define AR_RX_FILTER 0x803C /* receive filter register */ 254185377Ssam#define AR_MCAST_FIL0 0x8040 /* multicast filter lower 32 bits */ 255185377Ssam#define AR_MCAST_FIL1 0x8044 /* multicast filter upper 32 bits */ 256185377Ssam#define AR_DIAG_SW 0x8048 /* PCU control register */ 257185377Ssam#define AR_TSF_L32 0x804c /* local clock lower 32 bits */ 258185377Ssam#define AR_TSF_U32 0x8050 /* local clock upper 32 bits */ 259185377Ssam#define AR_TST_ADDAC 0x8054 /* ADDAC test register */ 260185377Ssam#define AR_DEF_ANTENNA 0x8058 /* default antenna register */ 261185377Ssam 262185377Ssam#define AR_LAST_TSTP 0x8080 /* Time stamp of the last beacon rcvd */ 263185377Ssam#define AR_NAV 0x8084 /* current NAV value */ 264185377Ssam#define AR_RTS_OK 0x8088 /* RTS exchange success counter */ 265185377Ssam#define AR_RTS_FAIL 0x808c /* RTS exchange failure counter */ 266185377Ssam#define AR_ACK_FAIL 0x8090 /* ACK failure counter */ 267185377Ssam#define AR_FCS_FAIL 0x8094 /* FCS check failure counter */ 268185377Ssam#define AR_BEACON_CNT 0x8098 /* Valid beacon counter */ 269185377Ssam 270185377Ssam#define AR_KEYTABLE_0 0x8800 /* Encryption key table */ 271185377Ssam#define AR_KEYTABLE(n) (AR_KEYTABLE_0 + ((n)*32)) 272185377Ssam 273185377Ssam#define AR_CR_RXE 0x00000004 /* Receive enable */ 274185377Ssam#define AR_CR_RXD 0x00000020 /* Receive disable */ 275185377Ssam#define AR_CR_SWI 0x00000040 /* One-shot software interrupt */ 276185377Ssam#define AR_CR_BITS "\20\3RXE\6RXD\7SWI" 277185377Ssam 278185377Ssam#define AR_CFG_SWTD 0x00000001 /* byteswap tx descriptor words */ 279185377Ssam#define AR_CFG_SWTB 0x00000002 /* byteswap tx data buffer words */ 280185377Ssam#define AR_CFG_SWRD 0x00000004 /* byteswap rx descriptor words */ 281185377Ssam#define AR_CFG_SWRB 0x00000008 /* byteswap rx data buffer words */ 282185377Ssam#define AR_CFG_SWRG 0x00000010 /* byteswap register access data words */ 283185377Ssam#define AR_CFG_AP_ADHOC_INDICATION 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */ 284185377Ssam#define AR_CFG_PHOK 0x00000100 /* PHY OK status */ 285185377Ssam#define AR_CFG_EEBS 0x00000200 /* EEPROM busy */ 286185377Ssam#define AR_CFG_CLK_GATE_DIS 0x00000400 /* Clock gating disable (Oahu only) */ 287185377Ssam#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M 0x00060000 /* Mask of PCI core master request queue full threshold */ 288185377Ssam#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 /* Shift for PCI core master request queue full threshold */ 289185377Ssam#define AR_CFG_BITS \ 290185377Ssam "\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\10PHYOK11EEBS" 291185377Ssam 292185377Ssam#define AR_IER_ENABLE 0x00000001 /* Global interrupt enable */ 293185377Ssam#define AR_IER_DISABLE 0x00000000 /* Global interrupt disable */ 294185377Ssam#define AR_IER_BITS "\20\1ENABLE" 295185377Ssam 296185377Ssam#define AR_RTSD0_RTS_DURATION_6_M 0x000000FF 297185377Ssam#define AR_RTSD0_RTS_DURATION_6_S 0 298185377Ssam#define AR_RTSD0_RTS_DURATION_9_M 0x0000FF00 299185377Ssam#define AR_RTSD0_RTS_DURATION_9_S 8 300185377Ssam#define AR_RTSD0_RTS_DURATION_12_M 0x00FF0000 301185377Ssam#define AR_RTSD0_RTS_DURATION_12_S 16 302185377Ssam#define AR_RTSD0_RTS_DURATION_18_M 0xFF000000 303185377Ssam#define AR_RTSD0_RTS_DURATION_18_S 24 304185377Ssam 305185377Ssam#define AR_RTSD0_RTS_DURATION_24_M 0x000000FF 306185377Ssam#define AR_RTSD0_RTS_DURATION_24_S 0 307185377Ssam#define AR_RTSD0_RTS_DURATION_36_M 0x0000FF00 308185377Ssam#define AR_RTSD0_RTS_DURATION_36_S 8 309185377Ssam#define AR_RTSD0_RTS_DURATION_48_M 0x00FF0000 310185377Ssam#define AR_RTSD0_RTS_DURATION_48_S 16 311185377Ssam#define AR_RTSD0_RTS_DURATION_54_M 0xFF000000 312185377Ssam#define AR_RTSD0_RTS_DURATION_54_S 24 313185377Ssam 314185377Ssam#define AR_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */ 315185377Ssam#define AR_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */ 316185377Ssam#define AR_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */ 317185377Ssam#define AR_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */ 318185377Ssam#define AR_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */ 319185377Ssam#define AR_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */ 320185377Ssam#define AR_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */ 321185377Ssam#define AR_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */ 322185377Ssam 323185377Ssam#define AR_TXCFG_FTRIG_M 0x000003F0 /* Mask for Frame trigger level */ 324185377Ssam#define AR_TXCFG_FTRIG_S 4 /* Shift for Frame trigger level */ 325185377Ssam#define AR_TXCFG_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */ 326185377Ssam#define AR_TXCFG_FTRIG_64B 0x00000010 /* default */ 327185377Ssam#define AR_TXCFG_FTRIG_128B 0x00000020 328185377Ssam#define AR_TXCFG_FTRIG_192B 0x00000030 329185377Ssam#define AR_TXCFG_FTRIG_256B 0x00000040 /* 5 bits total */ 330185377Ssam#define AR_TXCFG_BITS "\20" 331185377Ssam 332185377Ssam#define AR5311_RXCFG_DEF_RX_ANTENNA 0x00000008 /* Default Receive Antenna */ 333185377Ssam /* Maui2/Spirit only - reserved on Oahu */ 334185377Ssam#define AR_RXCFG_ZLFDMA 0x00000010 /* Enable DMA of zero-length frame */ 335185377Ssam#define AR_RXCFG_EN_JUM 0x00000020 /* Enable jumbo rx descriptors */ 336185377Ssam#define AR_RXCFG_WR_JUM 0x00000040 /* Wrap jumbo rx descriptors */ 337185377Ssam 338185377Ssam#define AR_MIBC_COW 0x00000001 /* counter overflow warning */ 339185377Ssam#define AR_MIBC_FMC 0x00000002 /* freeze MIB counters */ 340185377Ssam#define AR_MIBC_CMC 0x00000004 /* clear MIB counters */ 341185377Ssam#define AR_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */ 342185377Ssam 343185377Ssam#define AR_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */ 344185377Ssam 345185377Ssam#define AR_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */ 346185377Ssam 347185377Ssam#define AR_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */ 348185377Ssam#define AR_TXNPTO_QCU_MASK 0x03FFFC00 /* Mask indicating the set of QCUs */ 349185377Ssam /* for which frame completions will cause */ 350185377Ssam /* a reset of the no frame transmitted timeout */ 351185377Ssam 352185377Ssam#define AR_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */ 353185377Ssam 354185377Ssam#define AR_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */ 355185377Ssam 356185377Ssam#define AR_MACMISC_DMA_OBS_M 0x000001E0 /* Mask for DMA observation bus mux select */ 357185377Ssam#define AR_MACMISC_DMA_OBS_S 5 /* Shift for DMA observation bus mux select */ 358185377Ssam#define AR_MACMISC_MISC_OBS_M 0x00000E00 /* Mask for MISC observation bus mux select */ 359185377Ssam#define AR_MACMISC_MISC_OBS_S 9 /* Shift for MISC observation bus mux select */ 360185377Ssam#define AR_MACMISC_MAC_OBS_BUS_LSB_M 0x00007000 /* Mask for MAC observation bus mux select (lsb) */ 361185377Ssam#define AR_MACMISC_MAC_OBS_BUS_LSB_S 12 /* Shift for MAC observation bus mux select (lsb) */ 362185377Ssam#define AR_MACMISC_MAC_OBS_BUS_MSB_M 0x00038000 /* Mask for MAC observation bus mux select (msb) */ 363185377Ssam#define AR_MACMISC_MAC_OBS_BUS_MSB_S 15 /* Shift for MAC observation bus mux select (msb) */ 364185377Ssam 365185377Ssam /* Maui2/Spirit only. */ 366185377Ssam#define AR5311_QDCLKGATE_QCU_M 0x0000FFFF /* Mask for QCU clock disable */ 367185377Ssam#define AR5311_QDCLKGATE_DCU_M 0x07FF0000 /* Mask for DCU clock disable */ 368185377Ssam 369185377Ssam /* Interrupt Status Registers */ 370185377Ssam#define AR_ISR_RXOK 0x00000001 /* At least one frame received sans errors */ 371185377Ssam#define AR_ISR_RXDESC 0x00000002 /* Receive interrupt request */ 372185377Ssam#define AR_ISR_RXERR 0x00000004 /* Receive error interrupt */ 373185377Ssam#define AR_ISR_RXNOPKT 0x00000008 /* No frame received within timeout clock */ 374185377Ssam#define AR_ISR_RXEOL 0x00000010 /* Received descriptor empty interrupt */ 375185377Ssam#define AR_ISR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */ 376185377Ssam#define AR_ISR_TXOK 0x00000040 /* Transmit okay interrupt */ 377185377Ssam#define AR_ISR_TXDESC 0x00000080 /* Transmit interrupt request */ 378185377Ssam#define AR_ISR_TXERR 0x00000100 /* Transmit error interrupt */ 379185377Ssam#define AR_ISR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */ 380185377Ssam#define AR_ISR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */ 381185377Ssam#define AR_ISR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */ 382185377Ssam#define AR_ISR_MIB 0x00001000 /* MIB interrupt - see MIBC */ 383185377Ssam#define AR_ISR_SWI 0x00002000 /* Software interrupt */ 384185377Ssam#define AR_ISR_RXPHY 0x00004000 /* PHY receive error interrupt */ 385185377Ssam#define AR_ISR_RXKCM 0x00008000 /* Key-cache miss interrupt */ 386185377Ssam#define AR_ISR_SWBA 0x00010000 /* Software beacon alert interrupt */ 387185377Ssam#define AR_ISR_BRSSI 0x00020000 /* Beacon threshold interrupt */ 388185377Ssam#define AR_ISR_BMISS 0x00040000 /* Beacon missed interrupt */ 389185377Ssam#define AR_ISR_HIUERR 0x00080000 /* An unexpected bus error has occurred */ 390185377Ssam#define AR_ISR_BNR 0x00100000 /* Beacon not ready interrupt */ 391185377Ssam#define AR_ISR_TIM 0x00800000 /* TIM interrupt */ 392185377Ssam#define AR_ISR_GPIO 0x01000000 /* GPIO Interrupt */ 393185377Ssam#define AR_ISR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */ 394185377Ssam#define AR_ISR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */ 395185377Ssam#define AR_ISR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */ 396185377Ssam#define AR_ISR_RESV0 0xF0000000 /* Reserved */ 397185377Ssam 398185377Ssam#define AR_ISR_S0_QCU_TXOK_M 0x000003FF /* Mask for TXOK (QCU 0-9) */ 399185377Ssam#define AR_ISR_S0_QCU_TXDESC_M 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */ 400185377Ssam 401185377Ssam#define AR_ISR_S1_QCU_TXERR_M 0x000003FF /* Mask for TXERR (QCU 0-9) */ 402185377Ssam#define AR_ISR_S1_QCU_TXEOL_M 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */ 403185377Ssam 404185377Ssam#define AR_ISR_S2_QCU_TXURN_M 0x000003FF /* Mask for TXURN (QCU 0-9) */ 405185377Ssam#define AR_ISR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */ 406185377Ssam#define AR_ISR_S2_SSERR 0x00020000 /* SERR interrupt */ 407185377Ssam#define AR_ISR_S2_DPERR 0x00040000 /* PCI bus parity error */ 408185377Ssam#define AR_ISR_S2_RESV0 0xFFF80000 /* Reserved */ 409185377Ssam 410185377Ssam#define AR_ISR_S3_QCU_QCBROVF_M 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ 411185377Ssam#define AR_ISR_S3_QCU_QCBRURN_M 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ 412185377Ssam 413185377Ssam#define AR_ISR_S4_QCU_QTRIG_M 0x000003FF /* Mask for QTRIG (QCU 0-9) */ 414185377Ssam#define AR_ISR_S4_RESV0 0xFFFFFC00 /* Reserved */ 415185377Ssam 416185377Ssam /* Interrupt Mask Registers */ 417185377Ssam#define AR_IMR_RXOK 0x00000001 /* At least one frame received sans errors */ 418185377Ssam#define AR_IMR_RXDESC 0x00000002 /* Receive interrupt request */ 419185377Ssam#define AR_IMR_RXERR 0x00000004 /* Receive error interrupt */ 420185377Ssam#define AR_IMR_RXNOPKT 0x00000008 /* No frame received within timeout clock */ 421185377Ssam#define AR_IMR_RXEOL 0x00000010 /* Received descriptor empty interrupt */ 422185377Ssam#define AR_IMR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */ 423185377Ssam#define AR_IMR_TXOK 0x00000040 /* Transmit okay interrupt */ 424185377Ssam#define AR_IMR_TXDESC 0x00000080 /* Transmit interrupt request */ 425185377Ssam#define AR_IMR_TXERR 0x00000100 /* Transmit error interrupt */ 426185377Ssam#define AR_IMR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */ 427185377Ssam#define AR_IMR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */ 428185377Ssam#define AR_IMR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */ 429185377Ssam#define AR_IMR_MIB 0x00001000 /* MIB interrupt - see MIBC */ 430185377Ssam#define AR_IMR_SWI 0x00002000 /* Software interrupt */ 431185377Ssam#define AR_IMR_RXPHY 0x00004000 /* PHY receive error interrupt */ 432185377Ssam#define AR_IMR_RXKCM 0x00008000 /* Key-cache miss interrupt */ 433185377Ssam#define AR_IMR_SWBA 0x00010000 /* Software beacon alert interrupt */ 434185377Ssam#define AR_IMR_BRSSI 0x00020000 /* Beacon threshold interrupt */ 435185377Ssam#define AR_IMR_BMISS 0x00040000 /* Beacon missed interrupt */ 436185377Ssam#define AR_IMR_HIUERR 0x00080000 /* An unexpected bus error has occurred */ 437185377Ssam#define AR_IMR_BNR 0x00100000 /* BNR interrupt */ 438185377Ssam#define AR_IMR_TIM 0x00800000 /* TIM interrupt */ 439185377Ssam#define AR_IMR_GPIO 0x01000000 /* GPIO Interrupt */ 440185377Ssam#define AR_IMR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */ 441185377Ssam#define AR_IMR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */ 442185377Ssam#define AR_IMR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */ 443185377Ssam#define AR_IMR_RESV0 0xF0000000 /* Reserved */ 444185377Ssam 445185377Ssam#define AR_IMR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */ 446185377Ssam#define AR_IMR_S0_QCU_TXOK_S 0 447185377Ssam#define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */ 448185377Ssam#define AR_IMR_S0_QCU_TXDESC_S 16 /* Shift for TXDESC (QCU 0-9) */ 449185377Ssam 450185377Ssam#define AR_IMR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */ 451185377Ssam#define AR_IMR_S1_QCU_TXERR_S 0 452185377Ssam#define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */ 453185377Ssam#define AR_IMR_S1_QCU_TXEOL_S 16 /* Shift for TXEOL (QCU 0-9) */ 454185377Ssam 455185377Ssam#define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */ 456185377Ssam#define AR_IMR_S2_QCU_TXURN_S 0 457185377Ssam#define AR_IMR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */ 458185377Ssam#define AR_IMR_S2_SSERR 0x00020000 /* SERR interrupt */ 459185377Ssam#define AR_IMR_S2_DPERR 0x00040000 /* PCI bus parity error */ 460185377Ssam#define AR_IMR_S2_RESV0 0xFFF80000 /* Reserved */ 461185377Ssam 462185377Ssam#define AR_IMR_S3_QCU_QCBROVF_M 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ 463185377Ssam#define AR_IMR_S3_QCU_QCBRURN_M 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ 464185377Ssam#define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */ 465185377Ssam 466185377Ssam#define AR_IMR_S4_QCU_QTRIG_M 0x000003FF /* Mask for QTRIG (QCU 0-9) */ 467185377Ssam#define AR_IMR_S4_RESV0 0xFFFFFC00 /* Reserved */ 468185377Ssam 469185377Ssam /* Interrupt status registers (read-and-clear access, secondary shadow copies) */ 470185377Ssam 471185377Ssam /* QCU registers */ 472185377Ssam#define AR_NUM_QCU 10 /* Only use QCU 0-9 for forward QCU compatibility */ 473185377Ssam#define AR_QCU_0 0x0001 474185377Ssam#define AR_QCU_1 0x0002 475185377Ssam#define AR_QCU_2 0x0004 476185377Ssam#define AR_QCU_3 0x0008 477185377Ssam#define AR_QCU_4 0x0010 478185377Ssam#define AR_QCU_5 0x0020 479185377Ssam#define AR_QCU_6 0x0040 480185377Ssam#define AR_QCU_7 0x0080 481185377Ssam#define AR_QCU_8 0x0100 482185377Ssam#define AR_QCU_9 0x0200 483185377Ssam 484185377Ssam#define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */ 485185377Ssam 486185377Ssam#define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */ 487185377Ssam 488185377Ssam#define AR_Q_CBRCFG_CBR_INTERVAL 0x00FFFFFF /* Mask for CBR interval (us) */ 489185377Ssam#define AR_Q_CBRCFG_CBR_INTERVAL_S 0 /* Shift for CBR interval */ 490185377Ssam#define AR_Q_CBRCFG_CBR_OVF_THRESH 0xFF000000 /* Mask for CBR overflow threshold */ 491185377Ssam#define AR_Q_CBRCFG_CBR_OVF_THRESH_S 24 /* Shift for " " " */ 492185377Ssam 493185377Ssam#define AR_Q_RDYTIMECFG_INT 0x00FFFFFF /* CBR interval (us) */ 494185377Ssam#define AR_Q_RDYTIMECFG_INT_S 0 /* Shift for ReadyTime Interval (us) */ 495185377Ssam#define AR_Q_RDYTIMECFG_DURATION_M 0x00FFFFFF /* Mask for CBR interval (us) */ 496185377Ssam#define AR_Q_RDYTIMECFG_EN 0x01000000 /* ReadyTime enable */ 497185377Ssam#define AR_Q_RDYTIMECFG_RESV0 0xFE000000 /* Reserved */ 498185377Ssam 499185377Ssam#define AR_Q_ONESHOTARM_SC_M 0x0000FFFF /* Mask for MAC_Q_ONESHOTARM_SC (QCU 0-15) */ 500185377Ssam#define AR_Q_ONESHOTARM_SC_RESV0 0xFFFF0000 /* Reserved */ 501185377Ssam 502185377Ssam#define AR_Q_ONESHOTARM_CC_M 0x0000FFFF /* Mask for MAC_Q_ONESHOTARM_CC (QCU 0-15) */ 503185377Ssam#define AR_Q_ONESHOTARM_CC_RESV0 0xFFFF0000 /* Reserved */ 504185377Ssam 505185377Ssam#define AR_Q_MISC_FSP_M 0x0000000F /* Mask for Frame Scheduling Policy */ 506185377Ssam#define AR_Q_MISC_FSP_ASAP 0 /* ASAP */ 507185377Ssam#define AR_Q_MISC_FSP_CBR 1 /* CBR */ 508185377Ssam#define AR_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */ 509185377Ssam#define AR_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */ 510185377Ssam#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */ 511185377Ssam#define AR_Q_MISC_ONE_SHOT_EN 0x00000010 /* OneShot enable */ 512185377Ssam#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 /* Disable CBR expired counter 513185377Ssam incr (empty q) */ 514185377Ssam#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 /* Disable CBR expired counter 515185377Ssam incr (empty beacon q) */ 516185377Ssam#define AR_Q_MISC_BEACON_USE 0x00000080 /* Beacon use indication */ 517185377Ssam#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT 0x00000100 /* CBR expired counter limit enable */ 518185377Ssam#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */ 519185377Ssam#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 /* Reset CBR expired counter */ 520185377Ssam#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 /* DCU frame early termination request control */ 521185377Ssam#define AR_Q_MISC_RESV0 0xFFFFF000 /* Reserved */ 522185377Ssam 523185377Ssam#define AR_Q_STS_PEND_FR_CNT_M 0x00000003 /* Mask for Pending Frame Count */ 524185377Ssam#define AR_Q_STS_RESV0 0x000000FC /* Reserved */ 525185377Ssam#define AR_Q_STS_CBR_EXP_CNT_M 0x0000FF00 /* Mask for CBR expired counter */ 526185377Ssam#define AR_Q_STS_RESV1 0xFFFF0000 /* Reserved */ 527185377Ssam 528185377Ssam#define AR_Q_RDYTIMESHDN_M 0x000003FF /* Mask for ReadyTimeShutdown status (QCU 0-9) */ 529185377Ssam 530185377Ssam /* DCU registers */ 531185377Ssam#define AR_NUM_DCU 10 /* Only use 10 DCU's for forward QCU/DCU compatibility */ 532185377Ssam#define AR_DCU_0 0x0001 533185377Ssam#define AR_DCU_1 0x0002 534185377Ssam#define AR_DCU_2 0x0004 535185377Ssam#define AR_DCU_3 0x0008 536185377Ssam#define AR_DCU_4 0x0010 537185377Ssam#define AR_DCU_5 0x0020 538185377Ssam#define AR_DCU_6 0x0040 539185377Ssam#define AR_DCU_7 0x0080 540185377Ssam#define AR_DCU_8 0x0100 541185377Ssam#define AR_DCU_9 0x0200 542185377Ssam 543185377Ssam#define AR_D_QCUMASK_M 0x000003FF /* Mask for QCU Mask (QCU 0-9) */ 544185377Ssam#define AR_D_QCUMASK_RESV0 0xFFFFFC00 /* Reserved */ 545185377Ssam 546185377Ssam#define AR_D_LCL_IFS_CWMIN 0x000003FF /* Mask for CW_MIN */ 547185377Ssam#define AR_D_LCL_IFS_CWMIN_S 0 /* Shift for CW_MIN */ 548185377Ssam#define AR_D_LCL_IFS_CWMAX 0x000FFC00 /* Mask for CW_MAX */ 549185377Ssam#define AR_D_LCL_IFS_CWMAX_S 10 /* Shift for CW_MAX */ 550185377Ssam#define AR_D_LCL_IFS_AIFS 0x0FF00000 /* Mask for AIFS */ 551185377Ssam#define AR_D_LCL_IFS_AIFS_S 20 /* Shift for AIFS */ 552185377Ssam#define AR_D_LCL_IFS_RESV0 0xF0000000 /* Reserved */ 553185377Ssam 554185377Ssam#define AR_D_RETRY_LIMIT_FR_SH 0x0000000F /* Mask for frame short retry limit */ 555185377Ssam#define AR_D_RETRY_LIMIT_FR_SH_S 0 /* Shift for frame short retry limit */ 556185377Ssam#define AR_D_RETRY_LIMIT_FR_LG 0x000000F0 /* Mask for frame long retry limit */ 557185377Ssam#define AR_D_RETRY_LIMIT_FR_LG_S 4 /* Shift for frame long retry limit */ 558185377Ssam#define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 /* Mask for station short retry limit */ 559185377Ssam#define AR_D_RETRY_LIMIT_STA_SH_S 8 /* Shift for station short retry limit */ 560185377Ssam#define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 /* Mask for station short retry limit */ 561185377Ssam#define AR_D_RETRY_LIMIT_STA_LG_S 14 /* Shift for station short retry limit */ 562185377Ssam#define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 /* Reserved */ 563185377Ssam 564185377Ssam#define AR_D_CHNTIME_EN 0x00100000 /* ChannelTime enable */ 565185377Ssam#define AR_D_CHNTIME_RESV0 0xFFE00000 /* Reserved */ 566185377Ssam#define AR_D_CHNTIME_DUR 0x000FFFFF /* Mask for ChannelTime duration (us) */ 567185377Ssam#define AR_D_CHNTIME_DUR_S 0 /* Shift for ChannelTime duration */ 568185377Ssam 569185377Ssam#define AR_D_MISC_BKOFF_THRESH_M 0x000007FF /* Mask for Backoff threshold setting */ 570185377Ssam#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 /* Backoff during a frag burst */ 571185377Ssam#define AR_D_MISC_HCF_POLL_EN 0x00000800 /* HFC poll enable */ 572185377Ssam#define AR_D_MISC_BKOFF_PERSISTENCE 0x00001000 /* Backoff persistence factor setting */ 573185377Ssam#define AR_D_MISC_FR_PREFETCH_EN 0x00002000 /* Frame prefetch enable */ 574185377Ssam#define AR_D_MISC_VIR_COL_HANDLING_M 0x0000C000 /* Mask for Virtual collision handling policy */ 575185377Ssam#define AR_D_MISC_VIR_COL_HANDLING_NORMAL 0 /* Normal */ 576185377Ssam#define AR_D_MISC_VIR_COL_HANDLING_MODIFIED 1 /* Modified */ 577185377Ssam#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 2 /* Ignore */ 578185377Ssam#define AR_D_MISC_BEACON_USE 0x00010000 /* Beacon use indication */ 579185377Ssam#define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 /* Mask for DCU arbiter lockout control */ 580185377Ssam#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 /* Shift for DCU arbiter lockout control */ 581185377Ssam#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout */ 582185377Ssam#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame */ 583185377Ssam#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */ 584185377Ssam#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 /* DCU arbiter lockout ignore control */ 585185377Ssam#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Sequence number increment disable */ 586185377Ssam#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Post-frame backoff disable */ 587185377Ssam#define AR_D_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual coll. handling policy */ 588185377Ssam#define AR_D_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS handling policy */ 589185377Ssam#define AR5311_D_MISC_SEQ_NUM_CONTROL 0x01000000 /* Sequence Number local or global */ 590185377Ssam /* Maui2/Spirit only, reserved on Oahu */ 591185377Ssam#define AR_D_MISC_RESV0 0xFE000000 /* Reserved */ 592185377Ssam 593185377Ssam#define AR_D_SEQNUM_M 0x00000FFF /* Mask for value of sequence number */ 594185377Ssam#define AR_D_SEQNUM_RESV0 0xFFFFF000 /* Reserved */ 595185377Ssam 596185377Ssam#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 /* Mask forLFSR slice select */ 597185377Ssam#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode indication */ 598185377Ssam#define AR_D_GBL_IFS_MISC_SIFS_DURATION_USEC 0x000003F0 /* Mask for SIFS duration (us) */ 599185377Ssam#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 /* Mask for microsecond duration */ 600185377Ssam#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 /* Mask for DCU arbiter delay */ 601185377Ssam#define AR_D_GBL_IFS_MISC_RESV0 0xFFC00000 /* Reserved */ 602185377Ssam 603185377Ssam/* Oahu only */ 604185377Ssam#define AR_D_TXPSE_CTRL_M 0x000003FF /* Mask of DCUs to pause (DCUs 0-9) */ 605185377Ssam#define AR_D_TXPSE_RESV0 0x0000FC00 /* Reserved */ 606185377Ssam#define AR_D_TXPSE_STATUS 0x00010000 /* Transmit pause status */ 607185377Ssam#define AR_D_TXPSE_RESV1 0xFFFE0000 /* Reserved */ 608185377Ssam 609185377Ssam /* DMA & PCI Registers in PCI space (usable during sleep) */ 610185377Ssam#define AR_RC_MAC 0x00000001 /* MAC reset */ 611185377Ssam#define AR_RC_BB 0x00000002 /* Baseband reset */ 612185377Ssam#define AR_RC_RESV0 0x00000004 /* Reserved */ 613185377Ssam#define AR_RC_RESV1 0x00000008 /* Reserved */ 614185377Ssam#define AR_RC_PCI 0x00000010 /* PCI-core reset */ 615185377Ssam#define AR_RC_BITS "\20\1MAC\2BB\3RESV0\4RESV1\5RPCI" 616185377Ssam 617185377Ssam#define AR_SCR_SLDUR 0x0000ffff /* sleep duration mask, units of 128us */ 618185377Ssam#define AR_SCR_SLDUR_S 0 619185377Ssam#define AR_SCR_SLE 0x00030000 /* sleep enable mask */ 620185377Ssam#define AR_SCR_SLE_S 16 /* sleep enable bits shift */ 621228980Sdim/* 622228980Sdim * The previous values for the following three defines were: 623228980Sdim * 624228980Sdim * AR_SCR_SLE_WAKE 0x00000000 625228980Sdim * AR_SCR_SLE_SLP 0x00010000 626228980Sdim * AR_SCR_SLE_NORM 0x00020000 627228980Sdim * 628228980Sdim * However, these have been pre-shifted with AR_SCR_SLE_S. The 629228980Sdim * OS_REG_READ() macro would attempt to shift them again, effectively 630228980Sdim * shifting out any of the set bits completely. 631228980Sdim */ 632228980Sdim#define AR_SCR_SLE_WAKE 0 /* force wake */ 633228980Sdim#define AR_SCR_SLE_SLP 1 /* force sleep */ 634228980Sdim#define AR_SCR_SLE_NORM 2 /* sleep logic normal operation */ 635185377Ssam#define AR_SCR_SLE_UNITS 0x00000008 /* SCR units/TU */ 636185377Ssam#define AR_SCR_BITS "\20\20SLE_SLP\21SLE" 637185377Ssam 638185377Ssam#define AR_INTPEND_TRUE 0x00000001 /* interrupt pending */ 639185377Ssam#define AR_INTPEND_BITS "\20\1IP" 640185377Ssam 641185377Ssam#define AR_SFR_SLEEP 0x00000001 /* force sleep */ 642185377Ssam 643185377Ssam#define AR_PCICFG_CLKRUNEN 0x00000004 /* enable PCI CLKRUN function */ 644185377Ssam#define AR_PCICFG_EEPROM_SIZE_M 0x00000018 /* Mask for EEPROM size */ 645185377Ssam#define AR_PCICFG_EEPROM_SIZE_S 3 /* Mask for EEPROM size */ 646185377Ssam#define AR_PCICFG_EEPROM_SIZE_4K 0 /* EEPROM size 4 Kbit */ 647185377Ssam#define AR_PCICFG_EEPROM_SIZE_8K 1 /* EEPROM size 8 Kbit */ 648185377Ssam#define AR_PCICFG_EEPROM_SIZE_16K 2 /* EEPROM size 16 Kbit */ 649185377Ssam#define AR_PCICFG_EEPROM_SIZE_FAILED 3 /* Failure */ 650185377Ssam#define AR_PCICFG_LEDCTL 0x00000060 /* LED control Status */ 651185377Ssam#define AR_PCICFG_LEDCTL_NONE 0x00000000 /* STA is not associated or trying */ 652185377Ssam#define AR_PCICFG_LEDCTL_PEND 0x00000020 /* STA is trying to associate */ 653185377Ssam#define AR_PCICFG_LEDCTL_ASSOC 0x00000040 /* STA is associated */ 654185377Ssam#define AR_PCICFG_PCI_BUS_SEL_M 0x00000380 /* Mask for PCI observation bus mux select */ 655185377Ssam#define AR_PCICFG_DIS_CBE_FIX 0x00000400 /* Disable fix for bad PCI CBE# generation */ 656185377Ssam#define AR_PCICFG_SL_INTEN 0x00000800 /* enable interrupt line assertion when asleep */ 657185377Ssam#define AR_PCICFG_RESV0 0x00001000 /* Reserved */ 658185377Ssam#define AR_PCICFG_SL_INPEN 0x00002000 /* Force asleep when an interrupt is pending */ 659185377Ssam#define AR_PCICFG_RESV1 0x0000C000 /* Reserved */ 660185377Ssam#define AR_PCICFG_SPWR_DN 0x00010000 /* mask for sleep/awake indication */ 661185377Ssam#define AR_PCICFG_LEDMODE 0x000E0000 /* LED mode */ 662185377Ssam#define AR_PCICFG_LEDMODE_PROP 0x00000000 /* Blink prop to filtered tx/rx */ 663185377Ssam#define AR_PCICFG_LEDMODE_RPROP 0x00020000 /* Blink prop to unfiltered tx/rx */ 664185377Ssam#define AR_PCICFG_LEDMODE_SPLIT 0x00040000 /* Blink power for tx/net for rx */ 665185377Ssam#define AR_PCICFG_LEDMODE_RAND 0x00060000 /* Blink randomly */ 666185377Ssam#define AR_PCICFG_LEDBLINK 0x00700000 /* LED blink threshold select */ 667185377Ssam#define AR_PCICFG_LEDBLINK_S 20 668185377Ssam#define AR_PCICFG_LEDSLOW 0x00800000 /* LED slowest blink rate mode */ 669185377Ssam#define AR_PCICFG_RESV2 0xFF000000 /* Reserved */ 670185377Ssam#define AR_PCICFG_BITS "\20\3CLKRUNEN\13SL_INTEN" 671185377Ssam 672185377Ssam#define AR_GPIOCR_CR_SHIFT 2 /* Each CR is 2 bits */ 673185377Ssam#define AR_GPIOCR_0_CR_N 0x00000000 /* Input only mode for GPIODO[0] */ 674185377Ssam#define AR_GPIOCR_0_CR_0 0x00000001 /* Output only if GPIODO[0] = 0 */ 675185377Ssam#define AR_GPIOCR_0_CR_1 0x00000002 /* Output only if GPIODO[0] = 1 */ 676185377Ssam#define AR_GPIOCR_0_CR_A 0x00000003 /* Always output */ 677185377Ssam#define AR_GPIOCR_1_CR_N 0x00000000 /* Input only mode for GPIODO[1] */ 678185377Ssam#define AR_GPIOCR_1_CR_0 0x00000004 /* Output only if GPIODO[1] = 0 */ 679185377Ssam#define AR_GPIOCR_1_CR_1 0x00000008 /* Output only if GPIODO[1] = 1 */ 680185377Ssam#define AR_GPIOCR_1_CR_A 0x0000000C /* Always output */ 681185377Ssam#define AR_GPIOCR_2_CR_N 0x00000000 /* Input only mode for GPIODO[2] */ 682185377Ssam#define AR_GPIOCR_2_CR_0 0x00000010 /* Output only if GPIODO[2] = 0 */ 683185377Ssam#define AR_GPIOCR_2_CR_1 0x00000020 /* Output only if GPIODO[2] = 1 */ 684185377Ssam#define AR_GPIOCR_2_CR_A 0x00000030 /* Always output */ 685185377Ssam#define AR_GPIOCR_3_CR_N 0x00000000 /* Input only mode for GPIODO[3] */ 686185377Ssam#define AR_GPIOCR_3_CR_0 0x00000040 /* Output only if GPIODO[3] = 0 */ 687185377Ssam#define AR_GPIOCR_3_CR_1 0x00000080 /* Output only if GPIODO[3] = 1 */ 688185377Ssam#define AR_GPIOCR_3_CR_A 0x000000C0 /* Always output */ 689185377Ssam#define AR_GPIOCR_4_CR_N 0x00000000 /* Input only mode for GPIODO[4] */ 690185377Ssam#define AR_GPIOCR_4_CR_0 0x00000100 /* Output only if GPIODO[4] = 0 */ 691185377Ssam#define AR_GPIOCR_4_CR_1 0x00000200 /* Output only if GPIODO[4] = 1 */ 692185377Ssam#define AR_GPIOCR_4_CR_A 0x00000300 /* Always output */ 693185377Ssam#define AR_GPIOCR_5_CR_N 0x00000000 /* Input only mode for GPIODO[5] */ 694185377Ssam#define AR_GPIOCR_5_CR_0 0x00000400 /* Output only if GPIODO[5] = 0 */ 695185377Ssam#define AR_GPIOCR_5_CR_1 0x00000800 /* Output only if GPIODO[5] = 1 */ 696185377Ssam#define AR_GPIOCR_5_CR_A 0x00000C00 /* Always output */ 697185377Ssam#define AR_GPIOCR_INT_SHIFT 12 /* Interrupt select field shifter */ 698185377Ssam#define AR_GPIOCR_INT_MASK 0x00007000 /* Interrupt select field mask */ 699185377Ssam#define AR_GPIOCR_INT_SEL0 0x00000000 /* Select Interrupt Pin GPIO_0 */ 700185377Ssam#define AR_GPIOCR_INT_SEL1 0x00001000 /* Select Interrupt Pin GPIO_1 */ 701185377Ssam#define AR_GPIOCR_INT_SEL2 0x00002000 /* Select Interrupt Pin GPIO_2 */ 702185377Ssam#define AR_GPIOCR_INT_SEL3 0x00003000 /* Select Interrupt Pin GPIO_3 */ 703185377Ssam#define AR_GPIOCR_INT_SEL4 0x00004000 /* Select Interrupt Pin GPIO_4 */ 704185377Ssam#define AR_GPIOCR_INT_SEL5 0x00005000 /* Select Interrupt Pin GPIO_5 */ 705185377Ssam#define AR_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO Interrupt */ 706185377Ssam#define AR_GPIOCR_INT_SELL 0x00000000 /* Generate Interrupt if selected pin is low */ 707185377Ssam#define AR_GPIOCR_INT_SELH 0x00010000 /* Generate Interrupt if selected pin is high */ 708185377Ssam 709185377Ssam#define AR_SREV_ID_M 0x000000FF /* Mask to read SREV info */ 710185377Ssam#define AR_PCICFG_EEPROM_SIZE_16K 2 /* EEPROM size 16 Kbit */ 711185377Ssam#define AR_SREV_ID_S 4 /* Major Rev Info */ 712185377Ssam#define AR_SREV_REVISION_M 0x0000000F /* Chip revision level */ 713185377Ssam#define AR_SREV_FPGA 1 714185377Ssam#define AR_SREV_D2PLUS 2 715185377Ssam#define AR_SREV_D2PLUS_MS 3 /* metal spin */ 716185377Ssam#define AR_SREV_CRETE 4 717185377Ssam#define AR_SREV_CRETE_MS 5 /* FCS metal spin */ 718185377Ssam#define AR_SREV_CRETE_MS23 7 /* 2.3 metal spin (6 skipped) */ 719185377Ssam#define AR_SREV_CRETE_23 8 /* 2.3 full tape out */ 720185377Ssam#define AR_SREV_VERSION_M 0x000000F0 /* Chip version indication */ 721185377Ssam#define AR_SREV_VERSION_CRETE 0 722185377Ssam#define AR_SREV_VERSION_MAUI_1 1 723185377Ssam#define AR_SREV_VERSION_MAUI_2 2 724185377Ssam#define AR_SREV_VERSION_SPIRIT 3 725185377Ssam#define AR_SREV_VERSION_OAHU 4 726185377Ssam#define AR_SREV_OAHU_ES 0 /* Engineering Sample */ 727185377Ssam#define AR_SREV_OAHU_PROD 2 /* Production */ 728185377Ssam 729185377Ssam#define RAD5_SREV_MAJOR 0x10 /* All current supported ar5211 5 GHz radios are rev 0x10 */ 730185377Ssam#define RAD5_SREV_PROD 0x15 /* Current production level radios */ 731185377Ssam#define RAD2_SREV_MAJOR 0x20 /* All current supported ar5211 2 GHz radios are rev 0x10 */ 732185377Ssam 733185377Ssam /* EEPROM Registers in the MAC */ 734185377Ssam#define AR_EEPROM_CMD_READ 0x00000001 735185377Ssam#define AR_EEPROM_CMD_WRITE 0x00000002 736185377Ssam#define AR_EEPROM_CMD_RESET 0x00000004 737185377Ssam 738185377Ssam#define AR_EEPROM_STS_READ_ERROR 0x00000001 739185377Ssam#define AR_EEPROM_STS_READ_COMPLETE 0x00000002 740185377Ssam#define AR_EEPROM_STS_WRITE_ERROR 0x00000004 741185377Ssam#define AR_EEPROM_STS_WRITE_COMPLETE 0x00000008 742185377Ssam 743185377Ssam#define AR_EEPROM_CFG_SIZE_M 0x00000003 /* Mask for EEPROM size determination override */ 744185377Ssam#define AR_EEPROM_CFG_SIZE_AUTO 0 745185377Ssam#define AR_EEPROM_CFG_SIZE_4KBIT 1 746185377Ssam#define AR_EEPROM_CFG_SIZE_8KBIT 2 747185377Ssam#define AR_EEPROM_CFG_SIZE_16KBIT 3 748185377Ssam#define AR_EEPROM_CFG_DIS_WAIT_WRITE_COMPL 0x00000004 /* Disable wait for write completion */ 749185377Ssam#define AR_EEPROM_CFG_CLOCK_M 0x00000018 /* Mask for EEPROM clock rate control */ 750185377Ssam#define AR_EEPROM_CFG_CLOCK_S 3 /* Shift for EEPROM clock rate control */ 751185377Ssam#define AR_EEPROM_CFG_CLOCK_156KHZ 0 752185377Ssam#define AR_EEPROM_CFG_CLOCK_312KHZ 1 753185377Ssam#define AR_EEPROM_CFG_CLOCK_625KHZ 2 754185377Ssam#define AR_EEPROM_CFG_RESV0 0x000000E0 /* Reserved */ 755185377Ssam#define AR_EEPROM_CFG_PROT_KEY_M 0x00FFFF00 /* Mask for EEPROM protection key */ 756185377Ssam#define AR_EEPROM_CFG_PROT_KEY_S 8 /* Shift for EEPROM protection key */ 757185377Ssam#define AR_EEPROM_CFG_EN_L 0x01000000 /* EPRM_EN_L setting */ 758185377Ssam 759185377Ssam /* MAC PCU Registers */ 760185377Ssam#define AR_STA_ID1_SADH_MASK 0x0000FFFF /* Mask for upper 16 bits of MAC addr */ 761185377Ssam#define AR_STA_ID1_STA_AP 0x00010000 /* Device is AP */ 762185377Ssam#define AR_STA_ID1_ADHOC 0x00020000 /* Device is ad-hoc */ 763185377Ssam#define AR_STA_ID1_PWR_SAV 0x00040000 /* Power save reporting in self-generated frames */ 764185377Ssam#define AR_STA_ID1_KSRCHDIS 0x00080000 /* Key search disable */ 765185377Ssam#define AR_STA_ID1_PCF 0x00100000 /* Observe PCF */ 766185377Ssam#define AR_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ 767185377Ssam#define AR_STA_ID1_DESC_ANTENNA 0x00400000 /* Update default antenna w/ TX antenna */ 768185377Ssam#define AR_STA_ID1_RTS_USE_DEF 0x00800000 /* Use default antenna to send RTS */ 769185377Ssam#define AR_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mb/s rate for ACK & CTS */ 770185377Ssam#define AR_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate for ACK & CTS */ 771185377Ssam#define AR_STA_ID1_BITS \ 772185377Ssam "\20\20AP\21ADHOC\22PWR_SAV\23KSRCHDIS\25PCF" 773185377Ssam 774185377Ssam#define AR_BSS_ID1_U16_M 0x0000FFFF /* Mask for upper 16 bits of BSSID */ 775185377Ssam#define AR_BSS_ID1_AID_M 0xFFFF0000 /* Mask for association ID */ 776185377Ssam#define AR_BSS_ID1_AID_S 16 /* Shift for association ID */ 777185377Ssam 778185377Ssam#define AR_SLOT_TIME_MASK 0x000007FF /* Slot time mask */ 779185377Ssam 780185377Ssam#define AR_TIME_OUT_ACK 0x00001FFF /* Mask for ACK time-out */ 781185377Ssam#define AR_TIME_OUT_ACK_S 0 /* Shift for ACK time-out */ 782185377Ssam#define AR_TIME_OUT_CTS 0x1FFF0000 /* Mask for CTS time-out */ 783185377Ssam#define AR_TIME_OUT_CTS_S 16 /* Shift for CTS time-out */ 784185377Ssam 785185377Ssam#define AR_RSSI_THR_MASK 0x000000FF /* Mask for Beacon RSSI warning threshold */ 786185377Ssam#define AR_RSSI_THR_BM_THR 0x0000FF00 /* Mask for Missed beacon threshold */ 787185377Ssam#define AR_RSSI_THR_BM_THR_S 8 /* Shift for Missed beacon threshold */ 788185377Ssam 789185377Ssam#define AR_USEC_M 0x0000007F /* Mask for clock cycles in 1 usec */ 790185377Ssam#define AR_USEC_32_M 0x00003F80 /* Mask for number of 32MHz clock cycles in 1 usec */ 791185377Ssam#define AR_USEC_32_S 7 /* Shift for number of 32MHz clock cycles in 1 usec */ 792185377Ssam/* 793185377Ssam * Tx/Rx latencies are to signal start and are in usecs. 794185377Ssam * 795185377Ssam * NOTE: AR5211/AR5311 difference: on Oahu, the TX latency field 796185377Ssam * has increased from 6 bits to 9 bits. The RX latency field 797185377Ssam * is unchanged, but is shifted over 3 bits. 798185377Ssam */ 799185377Ssam#define AR5311_USEC_TX_LAT_M 0x000FC000 /* Tx latency */ 800185377Ssam#define AR5311_USEC_TX_LAT_S 14 801185377Ssam#define AR5311_USEC_RX_LAT_M 0x03F00000 /* Rx latency */ 802185377Ssam#define AR5311_USEC_RX_LAT_S 20 803185377Ssam 804185377Ssam#define AR5211_USEC_TX_LAT_M 0x007FC000 /* Tx latency */ 805185377Ssam#define AR5211_USEC_TX_LAT_S 14 806185377Ssam#define AR5211_USEC_RX_LAT_M 0x1F800000 /* Rx latency */ 807185377Ssam#define AR5211_USEC_RX_LAT_S 23 808185377Ssam 809185377Ssam 810185377Ssam#define AR_BEACON_PERIOD 0x0000FFFF /* Beacon period in TU/msec */ 811185377Ssam#define AR_BEACON_PERIOD_S 0 /* Byte offset of PERIOD start*/ 812185377Ssam#define AR_BEACON_TIM 0x007F0000 /* Byte offset of TIM start */ 813185377Ssam#define AR_BEACON_TIM_S 16 /* Byte offset of TIM start */ 814185377Ssam#define AR_BEACON_EN 0x00800000 /* beacon enable */ 815185377Ssam#define AR_BEACON_RESET_TSF 0x01000000 /* Clears TSF to 0 */ 816185377Ssam#define AR_BEACON_BITS "\20\27ENABLE\30RESET_TSF" 817185377Ssam 818185377Ssam#define AR_RX_FILTER_ALL 0x00000000 /* Disallow all frames */ 819185377Ssam#define AR_RX_UCAST 0x00000001 /* Allow unicast frames */ 820185377Ssam#define AR_RX_MCAST 0x00000002 /* Allow multicast frames */ 821185377Ssam#define AR_RX_BCAST 0x00000004 /* Allow broadcast frames */ 822185377Ssam#define AR_RX_CONTROL 0x00000008 /* Allow control frames */ 823185377Ssam#define AR_RX_BEACON 0x00000010 /* Allow beacon frames */ 824185377Ssam#define AR_RX_PROM 0x00000020 /* Promiscuous mode */ 825185377Ssam#define AR_RX_PHY_ERR 0x00000040 /* Allow all phy errors */ 826185377Ssam#define AR_RX_PHY_RADAR 0x00000080 /* Allow radar phy errors */ 827185377Ssam#define AR_RX_FILTER_BITS \ 828185377Ssam "\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROMISC\7PHY_ERR\10PHY_RADAR" 829185377Ssam 830185377Ssam#define AR_DIAG_SW_CACHE_ACK 0x00000001 /* disable ACK if no valid key*/ 831185377Ssam#define AR_DIAG_SW_DIS_ACK 0x00000002 /* disable ACK generation */ 832185377Ssam#define AR_DIAG_SW_DIS_CTS 0x00000004 /* disable CTS generation */ 833185377Ssam#define AR_DIAG_SW_DIS_ENCRYPT 0x00000008 /* disable encryption */ 834185377Ssam#define AR_DIAG_SW_DIS_DECRYPT 0x00000010 /* disable decryption */ 835185377Ssam#define AR_DIAG_SW_DIS_RX 0x00000020 /* disable receive */ 836185377Ssam#define AR_DIAG_SW_CORR_FCS 0x00000080 /* corrupt FCS */ 837185377Ssam#define AR_DIAG_SW_CHAN_INFO 0x00000100 /* dump channel info */ 838185377Ssam#define AR_DIAG_SW_EN_SCRAMSD 0x00000200 /* enable fixed scrambler seed*/ 839185377Ssam#define AR5311_DIAG_SW_USE_ECO 0x00000400 /* "super secret" use ECO enable bit */ 840185377Ssam#define AR_DIAG_SW_SCRAM_SEED_M 0x0001FC00 /* Fixed scrambler seed mask */ 841185377Ssam#define AR_DIAG_SW_SCRAM_SEED_S 10 /* Fixed scrambler seed shfit */ 842185377Ssam#define AR_DIAG_SW_FRAME_NV0 0x00020000 /* accept frames of non-zero protocol version */ 843185377Ssam#define AR_DIAG_SW_OBS_PT_SEL_M 0x000C0000 /* Observation point select */ 844185377Ssam#define AR_DIAG_SW_OBS_PT_SEL_S 18 /* Observation point select */ 845185377Ssam#define AR_DIAG_SW_BITS \ 846185377Ssam "\20\1DIS_CACHE_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_RX"\ 847185377Ssam "\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED\14USE_ECO\24FRAME_NV0" 848185377Ssam 849185377Ssam#define AR_KEYTABLE_KEY0(n) (AR_KEYTABLE(n) + 0) /* key bit 0-31 */ 850185377Ssam#define AR_KEYTABLE_KEY1(n) (AR_KEYTABLE(n) + 4) /* key bit 32-47 */ 851185377Ssam#define AR_KEYTABLE_KEY2(n) (AR_KEYTABLE(n) + 8) /* key bit 48-79 */ 852185377Ssam#define AR_KEYTABLE_KEY3(n) (AR_KEYTABLE(n) + 12) /* key bit 80-95 */ 853185377Ssam#define AR_KEYTABLE_KEY4(n) (AR_KEYTABLE(n) + 16) /* key bit 96-127 */ 854185377Ssam#define AR_KEYTABLE_TYPE(n) (AR_KEYTABLE(n) + 20) /* key type */ 855185377Ssam#define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */ 856185377Ssam#define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */ 857185377Ssam#define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */ 858185377Ssam#define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES 128 bit key */ 859185377Ssam#define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */ 860185377Ssam#define AR_KEYTABLE_MAC0(n) (AR_KEYTABLE(n) + 24) /* MAC address 1-32 */ 861185377Ssam#define AR_KEYTABLE_MAC1(n) (AR_KEYTABLE(n) + 28) /* MAC address 33-47 */ 862185377Ssam#define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */ 863185377Ssam 864185377Ssam#endif /* _DEV_ATH_AR5211REG_H */ 865