1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2004 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17204644Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5210REG_H 20185377Ssam#define _DEV_ATH_AR5210REG_H 21185377Ssam 22185377Ssam/* 23185377Ssam * Register defintions for the Atheros AR5210/5110 MAC/Basedband 24185377Ssam * Processor for IEEE 802.11a 5-GHz Wireless LANs. 25185377Ssam */ 26185377Ssam 27185377Ssam#ifndef PCI_VENDOR_ATHEROS 28185377Ssam#define PCI_VENDOR_ATHEROS 0x168c 29185377Ssam#endif 30185377Ssam#define PCI_PRODUCT_ATHEROS_AR5210 0x0007 31185377Ssam#define PCI_PRODUCT_ATHEROS_AR5210_OLD 0x0004 32185377Ssam 33185377Ssam/* DMA Registers */ 34185377Ssam#define AR_TXDP0 0x0000 /* TX queue pointer 0 register */ 35185377Ssam#define AR_TXDP1 0x0004 /* TX queue pointer 1 register */ 36185377Ssam#define AR_CR 0x0008 /* Command register */ 37185377Ssam#define AR_RXDP 0x000c /* RX queue descriptor ptr register */ 38185377Ssam#define AR_CFG 0x0014 /* Configuration and status register */ 39185377Ssam#define AR_ISR 0x001c /* Interrupt status register */ 40185377Ssam#define AR_IMR 0x0020 /* Interrupt mask register */ 41185377Ssam#define AR_IER 0x0024 /* Interrupt global enable register */ 42185377Ssam#define AR_BCR 0x0028 /* Beacon control register */ 43185377Ssam#define AR_BSR 0x002c /* Beacon status register */ 44185377Ssam#define AR_TXCFG 0x0030 /* TX configuration register */ 45185377Ssam#define AR_RXCFG 0x0034 /* RX configuration register */ 46185377Ssam#define AR_MIBC 0x0040 /* MIB control register */ 47185377Ssam#define AR_TOPS 0x0044 /* Timeout prescale register */ 48185377Ssam#define AR_RXNOFRM 0x0048 /* RX no frame timeout register */ 49185377Ssam#define AR_TXNOFRM 0x004c /* TX no frame timeout register */ 50185377Ssam#define AR_RPGTO 0x0050 /* RX frame gap timeout register */ 51185377Ssam#define AR_RFCNT 0x0054 /* RX frame count limit register */ 52185377Ssam#define AR_MISC 0x0058 /* Misc control and status register */ 53185377Ssam#define AR_RC 0x4000 /* Reset control */ 54185377Ssam#define AR_SCR 0x4004 /* Sleep control */ 55185377Ssam#define AR_INTPEND 0x4008 /* Interrupt pending */ 56185377Ssam#define AR_SFR 0x400c /* Force sleep */ 57185377Ssam#define AR_PCICFG 0x4010 /* PCI configuration */ 58185377Ssam#define AR_GPIOCR 0x4014 /* GPIO configuration */ 59185377Ssam#define AR_GPIODO 0x4018 /* GPIO data output */ 60185377Ssam#define AR_GPIODI 0x401c /* GPIO data input */ 61185377Ssam#define AR_SREV 0x4020 /* Silicon revision */ 62185377Ssam/* EEPROM Access Registers */ 63185377Ssam#define AR_EP_AIR_BASE 0x6000 /* EEPROM access initiation regs base */ 64185377Ssam#define AR_EP_AIR(n) (AR_EP_AIR_BASE + (n)*4) 65185377Ssam#define AR_EP_RDATA 0x6800 /* EEPROM read data register */ 66185377Ssam#define AR_EP_STA 0x6c00 /* EEPROM access status register */ 67185377Ssam/* PCU Registers */ 68185377Ssam#define AR_STA_ID0 0x8000 /* Lower 32bits of MAC address */ 69185377Ssam#define AR_STA_ID1 0x8004 /* Upper 16bits of MAC address */ 70185377Ssam#define AR_BSS_ID0 0x8008 /* Lower 32bits of BSSID */ 71185377Ssam#define AR_BSS_ID1 0x800c /* Upper 16bits of BSSID */ 72185377Ssam#define AR_SLOT_TIME 0x8010 /* Length of a back-off */ 73185377Ssam#define AR_TIME_OUT 0x8014 /* Timeout to wait for ACK and CTS */ 74185377Ssam#define AR_RSSI_THR 0x8018 /* Beacon RSSI warning threshold */ 75185377Ssam#define AR_RETRY_LMT 0x801c /* Short and long frame retry limit */ 76185377Ssam#define AR_USEC 0x8020 /* Transmit latency */ 77185377Ssam#define AR_BEACON 0x8024 /* Beacon control */ 78185377Ssam#define AR_CFP_PERIOD 0x8028 /* CFP period */ 79185377Ssam#define AR_TIMER0 0x802c /* Next beacon time */ 80185377Ssam#define AR_TIMER1 0x8030 /* Next DMA beacon alert time */ 81185377Ssam#define AR_TIMER2 0x8034 /* Next software beacon alert time */ 82185377Ssam#define AR_TIMER3 0x8038 /* Next ATIM window time */ 83185377Ssam#define AR_IFS0 0x8040 /* Protocol timers */ 84185377Ssam#define AR_IFS1 0x8044 /* Protocol time and control */ 85185377Ssam#define AR_CFP_DUR 0x8048 /* Maximum CFP duration */ 86185377Ssam#define AR_RX_FILTER 0x804c /* Receive filter */ 87185377Ssam#define AR_MCAST_FIL0 0x8050 /* Lower 32bits of mcast filter mask */ 88185377Ssam#define AR_MCAST_FIL1 0x8054 /* Upper 16bits of mcast filter mask */ 89185377Ssam#define AR_TX_MASK0 0x8058 /* Lower 32bits of TX mask */ 90185377Ssam#define AR_TX_MASK1 0x805c /* Upper 16bits of TX mask */ 91185377Ssam#define AR_CLR_TMASK 0x8060 /* Clear TX mask */ 92185377Ssam#define AR_TRIG_LEV 0x8064 /* Minimum FIFO fill level before TX */ 93185377Ssam#define AR_DIAG_SW 0x8068 /* PCU control */ 94185377Ssam#define AR_TSF_L32 0x806c /* Lower 32bits of local clock */ 95185377Ssam#define AR_TSF_U32 0x8070 /* Upper 32bits of local clock */ 96185377Ssam#define AR_LAST_TSTP 0x8080 /* Lower 32bits of last beacon tstamp */ 97185377Ssam#define AR_RETRY_CNT 0x8084 /* Current short or long retry cnt */ 98185377Ssam#define AR_BACKOFF 0x8088 /* Back-off status */ 99185377Ssam#define AR_NAV 0x808c /* Current NAV value */ 100185377Ssam#define AR_RTS_OK 0x8090 /* RTS success counter */ 101185377Ssam#define AR_RTS_FAIL 0x8094 /* RTS failure counter */ 102185377Ssam#define AR_ACK_FAIL 0x8098 /* ACK failure counter */ 103185377Ssam#define AR_FCS_FAIL 0x809c /* FCS failure counter */ 104185377Ssam#define AR_BEACON_CNT 0x80a0 /* Valid beacon counter */ 105185377Ssam#define AR_KEYTABLE_0 0x9000 /* Encryption key table */ 106185377Ssam#define AR_KEYTABLE(n) (AR_KEYTABLE_0 + ((n)*32)) 107185377Ssam 108185377Ssam#define AR_CR_TXE0 0x00000001 /* TX queue 0 enable */ 109185377Ssam#define AR_CR_TXE1 0x00000002 /* TX queue 1 enable */ 110185377Ssam#define AR_CR_RXE 0x00000004 /* RX enable */ 111185377Ssam#define AR_CR_TXD0 0x00000008 /* TX queue 0 disable */ 112185377Ssam#define AR_CR_TXD1 0x00000010 /* TX queue 1 disable */ 113185377Ssam#define AR_CR_RXD 0x00000020 /* RX disable */ 114185377Ssam#define AR_CR_SWI 0x00000040 /* software interrupt */ 115185377Ssam#define AR_CR_BITS \ 116185377Ssam "\20\1TXE0\2TXE1\3RXE\4TXD0\5TXD1\6RXD\7SWI" 117185377Ssam 118185377Ssam#define AR_CFG_SWTD 0x00000001 /* BE for TX desc */ 119185377Ssam#define AR_CFG_SWTB 0x00000002 /* BE for TX data */ 120185377Ssam#define AR_CFG_SWRD 0x00000004 /* BE for RX desc */ 121185377Ssam#define AR_CFG_SWRB 0x00000008 /* BE for RX data */ 122185377Ssam#define AR_CFG_SWRG 0x00000010 /* BE for registers */ 123185377Ssam#define AR_CFG_EEBS 0x00000200 /* EEPROM busy */ 124185377Ssam#define AR_CFG_TXCNT 0x00007800 /* number of TX desc in Q */ 125185377Ssam#define AR_CFG_TXCNT_S 11 126185377Ssam#define AR_CFG_TXFSTAT 0x00008000 /* TX DMA status */ 127185377Ssam#define AR_CFG_TXFSTRT 0x00010000 /* re-enable TX DMA */ 128185377Ssam#define AR_CFG_BITS \ 129185377Ssam "\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\14EEBS\17TXFSTAT\20TXFSTRT" 130185377Ssam 131185377Ssam#define AR_ISR_RXOK_INT 0x00000001 /* RX frame OK */ 132185377Ssam#define AR_ISR_RXDESC_INT 0x00000002 /* RX intr request */ 133185377Ssam#define AR_ISR_RXERR_INT 0x00000004 /* RX error */ 134185377Ssam#define AR_ISR_RXNOFRM_INT 0x00000008 /* no frame received */ 135185377Ssam#define AR_ISR_RXEOL_INT 0x00000010 /* RX desc empty */ 136185377Ssam#define AR_ISR_RXORN_INT 0x00000020 /* RX fifo overrun */ 137185377Ssam#define AR_ISR_TXOK_INT 0x00000040 /* TX frame OK */ 138185377Ssam#define AR_ISR_TXDESC_INT 0x00000080 /* TX intr request */ 139185377Ssam#define AR_ISR_TXERR_INT 0x00000100 /* TX error */ 140185377Ssam#define AR_ISR_TXNOFRM_INT 0x00000200 /* no frame transmitted */ 141185377Ssam#define AR_ISR_TXEOL_INT 0x00000400 /* TX desc empty */ 142185377Ssam#define AR_ISR_TXURN_INT 0x00000800 /* TX fifo underrun */ 143185377Ssam#define AR_ISR_MIB_INT 0x00001000 /* MIB interrupt */ 144185377Ssam#define AR_ISR_SWI_INT 0x00002000 /* software interrupt */ 145185377Ssam#define AR_ISR_RXPHY_INT 0x00004000 /* PHY RX error */ 146185377Ssam#define AR_ISR_RXKCM_INT 0x00008000 /* Key cache miss */ 147185377Ssam#define AR_ISR_SWBA_INT 0x00010000 /* software beacon alert */ 148185377Ssam#define AR_ISR_BRSSI_INT 0x00020000 /* beacon threshold */ 149185377Ssam#define AR_ISR_BMISS_INT 0x00040000 /* beacon missed */ 150185377Ssam#define AR_ISR_MCABT_INT 0x00100000 /* master cycle abort */ 151185377Ssam#define AR_ISR_SSERR_INT 0x00200000 /* SERR on PCI */ 152185377Ssam#define AR_ISR_DPERR_INT 0x00400000 /* Parity error on PCI */ 153185377Ssam#define AR_ISR_GPIO_INT 0x01000000 /* GPIO interrupt */ 154185377Ssam#define AR_ISR_BITS \ 155185377Ssam "\20\1RXOK\2RXDESC\3RXERR\4RXNOFM\5RXEOL\6RXORN\7TXOK\10TXDESC"\ 156185377Ssam "\11TXERR\12TXNOFRM\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"\ 157185377Ssam "\21SWBA\22BRSSI\23BMISS\24MCABT\25SSERR\26DPERR\27GPIO" 158185377Ssam 159185377Ssam#define AR_IMR_RXOK_INT 0x00000001 /* RX frame OK */ 160185377Ssam#define AR_IMR_RXDESC_INT 0x00000002 /* RX intr request */ 161185377Ssam#define AR_IMR_RXERR_INT 0x00000004 /* RX error */ 162185377Ssam#define AR_IMR_RXNOFRM_INT 0x00000008 /* no frame received */ 163185377Ssam#define AR_IMR_RXEOL_INT 0x00000010 /* RX desc empty */ 164185377Ssam#define AR_IMR_RXORN_INT 0x00000020 /* RX fifo overrun */ 165185377Ssam#define AR_IMR_TXOK_INT 0x00000040 /* TX frame OK */ 166185377Ssam#define AR_IMR_TXDESC_INT 0x00000080 /* TX intr request */ 167185377Ssam#define AR_IMR_TXERR_INT 0x00000100 /* TX error */ 168185377Ssam#define AR_IMR_TXNOFRM_INT 0x00000200 /* no frame transmitted */ 169185377Ssam#define AR_IMR_TXEOL_INT 0x00000400 /* TX desc empty */ 170185377Ssam#define AR_IMR_TXURN_INT 0x00000800 /* TX fifo underrun */ 171185377Ssam#define AR_IMR_MIB_INT 0x00001000 /* MIB interrupt */ 172185377Ssam#define AR_IMR_SWI_INT 0x00002000 /* software interrupt */ 173185377Ssam#define AR_IMR_RXPHY_INT 0x00004000 /* PHY RX error */ 174185377Ssam#define AR_IMR_RXKCM_INT 0x00008000 /* Key cache miss */ 175185377Ssam#define AR_IMR_SWBA_INT 0x00010000 /* software beacon alert */ 176185377Ssam#define AR_IMR_BRSSI_INT 0x00020000 /* beacon threshold */ 177185377Ssam#define AR_IMR_BMISS_INT 0x00040000 /* beacon missed */ 178185377Ssam#define AR_IMR_MCABT_INT 0x00100000 /* master cycle abort */ 179185377Ssam#define AR_IMR_SSERR_INT 0x00200000 /* SERR on PCI */ 180185377Ssam#define AR_IMR_DPERR_INT 0x00400000 /* Parity error on PCI */ 181185377Ssam#define AR_IMR_GPIO_INT 0x01000000 /* GPIO interrupt */ 182185377Ssam#define AR_IMR_BITS AR_ISR_BITS 183185377Ssam 184185377Ssam#define AR_IER_DISABLE 0x00000000 /* pseudo-flag */ 185185377Ssam#define AR_IER_ENABLE 0x00000001 /* global interrupt enable */ 186185377Ssam#define AR_IER_BITS "\20\1ENABLE" 187185377Ssam 188185377Ssam#define AR_BCR_BCMD 0x00000001 /* ad hoc beacon mode */ 189185377Ssam#define AR_BCR_BDMAE 0x00000002 /* beacon DMA enable */ 190185377Ssam#define AR_BCR_TQ1FV 0x00000004 /* use TXQ1 for non-beacon */ 191185377Ssam#define AR_BCR_TQ1V 0x00000008 /* TXQ1 valid for beacon */ 192185377Ssam#define AR_BCR_BCGET 0x00000010 /* force a beacon fetch */ 193185377Ssam#define AR_BCR_BITS "\20\1BCMD\2BDMAE\3TQ1FV\4TQ1V\5BCGET" 194185377Ssam 195185377Ssam#define AR_BSR_BDLYSW 0x00000001 /* software beacon delay */ 196185377Ssam#define AR_BSR_BDLYDMA 0x00000002 /* DMA beacon delay */ 197185377Ssam#define AR_BSR_TXQ1F 0x00000004 /* TXQ1 fetch */ 198185377Ssam#define AR_BSR_ATIMDLY 0x00000008 /* ATIM delay */ 199185377Ssam#define AR_BSR_SNPBCMD 0x00000100 /* snapshot of BCMD */ 200185377Ssam#define AR_BSR_SNPBDMAE 0x00000200 /* snapshot of BDMAE */ 201185377Ssam#define AR_BSR_SNPTQ1FV 0x00000400 /* snapshot of TQ1FV */ 202185377Ssam#define AR_BSR_SNPTQ1V 0x00000800 /* snapshot of TQ1V */ 203185377Ssam#define AR_BSR_SNAPPEDBCRVALID 0x00001000 /* snapshot of BCR are valid */ 204185377Ssam#define AR_BSR_SWBA_CNT 0x00ff0000 /* software beacon alert cnt */ 205185377Ssam#define AR_BSR_BITS \ 206185377Ssam "\20\1BDLYSW\2BDLYDMA\3TXQ1F\4ATIMDLY\11SNPBCMD\12SNPBDMAE"\ 207185377Ssam "\13SNPTQ1FV\14SNPTQ1V\15SNAPPEDBCRVALID" 208185377Ssam 209185377Ssam#define AR_TXCFG_SDMAMR 0x00000007 /* DMA burst size 2^(2+x) */ 210185377Ssam#define AR_TXCFG_TXFSTP 0x00000008 /* Stop TX DMA on filtered */ 211185377Ssam#define AR_TXCFG_TXFULL 0x00000070 /* TX DMA desc Q full thresh */ 212185377Ssam#define AR_TXCFG_TXCONT_EN 0x00000080 /* Enable continuous TX mode */ 213185377Ssam#define AR_TXCFG_BITS "\20\3TXFSTP\7TXCONT_EN" 214185377Ssam 215185377Ssam#define AR_RXCFG_SDMAMW 0x00000007 /* DMA burst size 2^(2+x) */ 216185377Ssam#define AR_RXCFG_ZLFDMA 0x00000010 /* enable zero length DMA */ 217185377Ssam 218185377Ssam/* DMA sizes used for both AR_TXCFG_SDMAMR and AR_RXCFG_SDMAMW */ 219185377Ssam#define AR_DMASIZE_4B 0 /* DMA size 4 bytes */ 220185377Ssam#define AR_DMASIZE_8B 1 /* DMA size 8 bytes */ 221185377Ssam#define AR_DMASIZE_16B 2 /* DMA size 16 bytes */ 222185377Ssam#define AR_DMASIZE_32B 3 /* DMA size 32 bytes */ 223185377Ssam#define AR_DMASIZE_64B 4 /* DMA size 64 bytes */ 224185377Ssam#define AR_DMASIZE_128B 5 /* DMA size 128 bytes */ 225185377Ssam#define AR_DMASIZE_256B 6 /* DMA size 256 bytes */ 226185377Ssam#define AR_DMASIZE_512B 7 /* DMA size 512 bytes */ 227185377Ssam 228185377Ssam#define AR_MIBC_COW 0x00000001 /* counter overflow warning */ 229185377Ssam#define AR_MIBC_FMC 0x00000002 /* freeze MIB counters */ 230185377Ssam#define AR_MIBC_CMC 0x00000004 /* clear MIB counters */ 231185377Ssam#define AR_MIBC_MCS 0x00000008 /* MIB counter strobe */ 232185377Ssam 233185377Ssam#define AR_RFCNT_RFCL 0x0000000f /* RX frame count limit */ 234185377Ssam 235185377Ssam#define AR_MISC_LED_DECAY 0x001c0000 /* LED decay rate */ 236185377Ssam#define AR_MISC_LED_BLINK 0x00e00000 /* LED blink rate */ 237185377Ssam 238185377Ssam#define AR_RC_RPCU 0x00000001 /* PCU Warm Reset */ 239185377Ssam#define AR_RC_RDMA 0x00000002 /* DMA Warm Reset */ 240185377Ssam#define AR_RC_RMAC 0x00000004 /* MAC Warm Reset */ 241185377Ssam#define AR_RC_RPHY 0x00000008 /* PHY Warm Reset */ 242185377Ssam#define AR_RC_RPCI 0x00000010 /* PCI Core Warm Reset */ 243185377Ssam#define AR_RC_BITS "\20\1RPCU\2RDMA\3RMAC\4RPHY\5RPCI" 244185377Ssam 245185377Ssam#define AR_SCR_SLDUR 0x0000ffff /* sleep duration */ 246185377Ssam#define AR_SCR_SLE 0x00030000 /* sleep enable */ 247185377Ssam#define AR_SCR_SLE_S 16 248228980Sdim/* 249228980Sdim * The previous values for the following three defines were: 250228980Sdim * 251228980Sdim * AR_SCR_SLE_WAKE 0x00000000 252228980Sdim * AR_SCR_SLE_SLP 0x00010000 253228980Sdim * AR_SCR_SLE_ALLOW 0x00020000 254228980Sdim * 255228980Sdim * However, these have been pre-shifted with AR_SCR_SLE_S. The 256228980Sdim * OS_REG_READ() macro would attempt to shift them again, effectively 257228980Sdim * shifting out any of the set bits completely. 258228980Sdim */ 259228980Sdim#define AR_SCR_SLE_WAKE 0 /* force wake */ 260228980Sdim#define AR_SCR_SLE_SLP 1 /* force sleep */ 261228980Sdim#define AR_SCR_SLE_ALLOW 2 /* allow to control sleep */ 262185377Ssam#define AR_SCR_BITS "\20\20SLE_SLP\21SLE_ALLOW" 263185377Ssam 264185377Ssam#define AR_INTPEND_IP 0x00000001 /* interrupt pending */ 265185377Ssam#define AR_INTPEND_BITS "\20\1IP" 266185377Ssam 267185377Ssam#define AR_SFR_SF 0x00000001 /* force sleep immediately */ 268185377Ssam 269185377Ssam#define AR_PCICFG_EEPROMSEL 0x00000001 /* EEPROM access enable */ 270185377Ssam#define AR_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable */ 271185377Ssam#define AR_PCICFG_LED_PEND 0x00000020 /* LED for assoc pending */ 272185377Ssam#define AR_PCICFG_LED_ACT 0x00000040 /* LED for assoc active */ 273185377Ssam#define AR_PCICFG_SL_INTEN 0x00000800 /* Enable sleep intr */ 274185377Ssam#define AR_PCICFG_LED_BCTL 0x00001000 /* LED blink for local act */ 275185377Ssam#define AR_PCICFG_SL_INPEN 0x00002800 /* sleep even intr pending */ 276185377Ssam#define AR_PCICFG_SPWR_DN 0x00010000 /* sleep indication */ 277185377Ssam#define AR_PCICFG_BITS \ 278185377Ssam "\20\1EEPROMSEL\3CLKRUNEN\5LED_PEND\6LED_ACT\13SL_INTEN"\ 279185377Ssam "\14LED_BCTL\20SPWR_DN" 280185377Ssam 281185377Ssam#define AR_GPIOCR_IN(n) (0<<((n)*2)) /* input-only */ 282185377Ssam#define AR_GPIOCR_OUT0(n) (1<<((n)*2)) /* output-only if GPIODO = 0 */ 283185377Ssam#define AR_GPIOCR_OUT1(n) (2<<((n)*2)) /* output-only if GPIODO = 1 */ 284185377Ssam#define AR_GPIOCR_OUT(n) (3<<((n)*2)) /* always output */ 285185377Ssam#define AR_GPIOCR_ALL(n) (3<<((n)*2)) /* all bits for pin */ 286185377Ssam#define AR_GPIOCR_INT_SEL(n) ((n)<<12) /* GPIO interrupt pin select */ 287185377Ssam#define AR_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ 288185377Ssam#define AR_GPIOCR_INT_SELL 0x00000000 /* Interrupt if pin is low */ 289185377Ssam#define AR_GPIOCR_INT_SELH 0x00010000 /* Interrupt if pin is high */ 290185377Ssam 291185377Ssam#define AR_SREV_CRETE 4 /* Crete 1st version */ 292185377Ssam#define AR_SREV_CRETE_MS 5 /* Crete FCS version */ 293185377Ssam#define AR_SREV_CRETE_23 8 /* Crete version 2.3 */ 294185377Ssam 295185377Ssam#define AR_EP_STA_RDERR 0x00000001 /* read error */ 296185377Ssam#define AR_EP_STA_RDCMPLT 0x00000002 /* read complete */ 297185377Ssam#define AR_EP_STA_WRERR 0x00000004 /* write error */ 298185377Ssam#define AR_EP_STA_WRCMPLT 0x00000008 /* write complete */ 299185377Ssam#define AR_EP_STA_BITS \ 300185377Ssam "\20\1RDERR\2RDCMPLT\3WRERR\4WRCMPLT" 301185377Ssam 302185377Ssam#define AR_STA_ID1_AP 0x00010000 /* Access Point Operation */ 303185377Ssam#define AR_STA_ID1_ADHOC 0x00020000 /* ad hoc Operation */ 304185377Ssam#define AR_STA_ID1_PWR_SV 0x00040000 /* power save report enable */ 305185377Ssam#define AR_STA_ID1_NO_KEYSRCH 0x00080000 /* key table search disable */ 306185377Ssam#define AR_STA_ID1_NO_PSPOLL 0x00100000 /* auto PS-POLL disable */ 307185377Ssam#define AR_STA_ID1_PCF 0x00200000 /* PCF observation enable */ 308185377Ssam#define AR_STA_ID1_DESC_ANTENNA 0x00400000 /* use antenna in TX desc */ 309185377Ssam#define AR_STA_ID1_DEFAULT_ANTENNA 0x00800000 /* toggle default antenna */ 310185377Ssam#define AR_STA_ID1_ACKCTS_6MB 0x01000000 /* use 6Mbps for ACK/CTS */ 311185377Ssam#define AR_STA_ID1_BITS \ 312185377Ssam "\20\20AP\21ADHOC\22PWR_SV\23NO_KEYSRCH\24NO_PSPOLL\25PCF"\ 313185377Ssam "\26DESC_ANTENNA\27DEFAULT_ANTENNA\30ACKCTS_6MB" 314185377Ssam 315185377Ssam#define AR_BSS_ID1_AID 0xffff0000 /* association ID */ 316185377Ssam#define AR_BSS_ID1_AID_S 16 317185377Ssam 318185377Ssam#define AR_TIME_OUT_ACK 0x00001fff /* ACK timeout */ 319185377Ssam#define AR_TIME_OUT_ACK_S 0 320185377Ssam#define AR_TIME_OUT_CTS 0x1fff0000 /* CTS timeout */ 321185377Ssam#define AR_TIME_OUT_CTS_S 16 322185377Ssam 323185377Ssam#define AR_RSSI_THR_BM_THR 0x00000700 /* missed beacon threshold */ 324185377Ssam#define AR_RSSI_THR_BM_THR_S 8 325185377Ssam 326185377Ssam#define AR_RETRY_LMT_SH_RETRY 0x0000000f /* short frame retry limit */ 327185377Ssam#define AR_RETRY_LMT_SH_RETRY_S 0 328185377Ssam#define AR_RETRY_LMT_LG_RETRY 0x000000f0 /* long frame retry limit */ 329185377Ssam#define AR_RETRY_LMT_LG_RETRY_S 4 330185377Ssam#define AR_RETRY_LMT_SSH_RETRY 0x00003f00 /* short station retry limit */ 331185377Ssam#define AR_RETRY_LMT_SSH_RETRY_S 8 332185377Ssam#define AR_RETRY_LMT_SLG_RETRY 0x000fc000 /* long station retry limit */ 333185377Ssam#define AR_RETRY_LMT_SLG_RETRY_S 14 334185377Ssam#define AR_RETRY_LMT_CW_MIN 0x3ff00000 /* minimum contention window */ 335185377Ssam#define AR_RETRY_LMT_CW_MIN_S 20 336185377Ssam 337185377Ssam#define AR_USEC_1 0x0000007f /* number of clk in 1us */ 338185377Ssam#define AR_USEC_1_S 0 339185377Ssam#define AR_USEC_32 0x00003f80 /* number of 32MHz clk in 1us */ 340185377Ssam#define AR_USEC_32_S 7 341185377Ssam#define AR_USEC_TX_LATENCY 0x000fc000 /* transmit latency in us */ 342185377Ssam#define AR_USEC_TX_LATENCY_S 14 343185377Ssam#define AR_USEC_RX_LATENCY 0x03f00000 /* receive latency in us */ 344185377Ssam#define AR_USEC_RX_LATENCY_S 20 345185377Ssam 346185377Ssam#define AR_BEACON_PERIOD 0x0000ffff /* beacon period in TU/ms */ 347185377Ssam#define AR_BEACON_PERIOD_S 0 348185377Ssam#define AR_BEACON_TIM 0x007f0000 /* byte offset */ 349185377Ssam#define AR_BEACON_TIM_S 16 350185377Ssam#define AR_BEACON_EN 0x00800000 /* beacon transmission enable */ 351185377Ssam#define AR_BEACON_RESET_TSF 0x01000000 /* TSF reset oneshot */ 352185377Ssam#define AR_BEACON_BITS "\20\27ENABLE\30RESET_TSF" 353185377Ssam 354185377Ssam#define AR_IFS0_SIFS 0x000007ff /* SIFS in core clock cycles */ 355185377Ssam#define AR_IFS0_SIFS_S 0 356185377Ssam#define AR_IFS0_DIFS 0x007ff800 /* DIFS in core clock cycles */ 357185377Ssam#define AR_IFS0_DIFS_S 11 358185377Ssam 359185377Ssam#define AR_IFS1_PIFS 0x00000fff /* Programmable IFS */ 360185377Ssam#define AR_IFS1_PIFS_S 0 361185377Ssam#define AR_IFS1_EIFS 0x03fff000 /* EIFS in core clock cycles */ 362185377Ssam#define AR_IFS1_EIFS_S 12 363185377Ssam#define AR_IFS1_CS_EN 0x04000000 /* carrier sense enable */ 364185377Ssam 365185377Ssam#define AR_RX_FILTER_UNICAST 0x00000001 /* unicast frame enable */ 366185377Ssam#define AR_RX_FILTER_MULTICAST 0x00000002 /* multicast frame enable */ 367185377Ssam#define AR_RX_FILTER_BROADCAST 0x00000004 /* broadcast frame enable */ 368185377Ssam#define AR_RX_FILTER_CONTROL 0x00000008 /* control frame enable */ 369185377Ssam#define AR_RX_FILTER_BEACON 0x00000010 /* beacon frame enable */ 370185377Ssam#define AR_RX_FILTER_PROMISCUOUS 0x00000020 /* promiscuous receive enable */ 371185377Ssam#define AR_RX_FILTER_BITS \ 372185377Ssam "\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROMISC" 373185377Ssam 374185377Ssam#define AR_DIAG_SW_DIS_WEP_ACK 0x00000001 /* disable ACK if no key found*/ 375185377Ssam#define AR_DIAG_SW_DIS_ACK 0x00000002 /* disable ACK generation */ 376185377Ssam#define AR_DIAG_SW_DIS_CTS 0x00000004 /* disable CTS generation */ 377185377Ssam#define AR_DIAG_SW_DIS_ENC 0x00000008 /* encryption disable */ 378185377Ssam#define AR_DIAG_SW_DIS_DEC 0x00000010 /* decryption disable */ 379185377Ssam#define AR_DIAG_SW_DIS_TX 0x00000020 /* TX disable */ 380185377Ssam#define AR_DIAG_SW_DIS_RX 0x00000040 /* RX disable */ 381185377Ssam#define AR_DIAG_SW_LOOP_BACK 0x00000080 /* TX data loopback enable */ 382185377Ssam#define AR_DIAG_SW_CORR_FCS 0x00000100 /* corrupt FCS enable */ 383185377Ssam#define AR_DIAG_SW_CHAN_INFO 0x00000200 /* channel information enable */ 384185377Ssam#define AR_DIAG_SW_EN_SCRAM_SEED 0x00000400 /* use fixed scrambler seed */ 385185377Ssam#define AR_DIAG_SW_SCVRAM_SEED 0x0003f800 /* fixed scrambler seed */ 386185377Ssam#define AR_DIAG_SW_DIS_SEQ_INC 0x00040000 /* seq increment disable */ 387185377Ssam#define AR_DIAG_SW_FRAME_NV0 0x00080000 /* accept frame vers != 0 */ 388243317Sadrian#define AR_DIAG_SW_DIS_CRYPTO (AR_DIAG_SW_DIS_ENC | AR_DIAG_SW_DIS_DEC) 389185377Ssam#define AR_DIAG_SW_BITS \ 390185377Ssam "\20\1DIS_WEP_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_TX"\ 391185377Ssam "\7DIS_RX\10LOOP_BACK\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED"\ 392185377Ssam "\22DIS_SEQ_INC\24FRAME_NV0" 393185377Ssam 394185377Ssam#define AR_RETRY_CNT_SSH 0x0000003f /* current short retry count */ 395185377Ssam#define AR_RETRY_CNT_SLG 0x00000fc0 /* current long retry count */ 396185377Ssam 397185377Ssam#define AR_BACKOFF_CW 0x000003ff /* current contention window */ 398185377Ssam#define AR_BACKOFF_CNT 0x03ff0000 /* backoff count */ 399185377Ssam 400185377Ssam#define AR_KEYTABLE_KEY0(n) (AR_KEYTABLE(n) + 0) /* key bit 0-31 */ 401185377Ssam#define AR_KEYTABLE_KEY1(n) (AR_KEYTABLE(n) + 4) /* key bit 32-47 */ 402185377Ssam#define AR_KEYTABLE_KEY2(n) (AR_KEYTABLE(n) + 8) /* key bit 48-79 */ 403185377Ssam#define AR_KEYTABLE_KEY3(n) (AR_KEYTABLE(n) + 12) /* key bit 80-95 */ 404185377Ssam#define AR_KEYTABLE_KEY4(n) (AR_KEYTABLE(n) + 16) /* key bit 96-127 */ 405185377Ssam#define AR_KEYTABLE_TYPE(n) (AR_KEYTABLE(n) + 20) /* key type */ 406185377Ssam#define AR_KEYTABLE_TYPE_40 0x00000000 /* 40 bit key */ 407185377Ssam#define AR_KEYTABLE_TYPE_104 0x00000001 /* 104 bit key */ 408185377Ssam#define AR_KEYTABLE_TYPE_128 0x00000003 /* 128 bit key */ 409185377Ssam#define AR_KEYTABLE_MAC0(n) (AR_KEYTABLE(n) + 24) /* MAC address 1-32 */ 410185377Ssam#define AR_KEYTABLE_MAC1(n) (AR_KEYTABLE(n) + 28) /* MAC address 33-47 */ 411185377Ssam#define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */ 412185377Ssam 413185377Ssam#endif /* _DEV_ATH_AR5210REG_H */ 414