1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_internal.h" 21#include "ah_devid.h" 22 23#include "ar9300/ar9300desc.h" 24#include "ar9300/ar9300.h" 25#include "ar9300/ar9300reg.h" 26#include "ar9300/ar9300phy.h" 27#include "ar9300/ar9300paprd.h" 28 29#include "ar9300/ar9300_stub.h" 30#include "ar9300/ar9300_stub_funcs.h" 31 32 33/* Add static register initialization vectors */ 34#include "ar9300/ar9300_osprey22.ini" 35#include "ar9300/ar9330_11.ini" 36#include "ar9300/ar9330_12.ini" 37#include "ar9300/ar9340.ini" 38#include "ar9300/ar9485.ini" 39#include "ar9300/ar9485_1_1.ini" 40#include "ar9300/ar9300_jupiter10.ini" 41/* TODO: convert the 2.0 code to use the new initvals from ath9k */ 42#include "ar9300/ar9300_jupiter20.ini" 43#include "ar9300/ar9462_2p0_initvals.h" 44#include "ar9300/ar9462_2p1_initvals.h" 45#include "ar9300/ar9580.ini" 46#include "ar9300/ar955x.ini" 47#include "ar9300/ar953x.ini" 48#include "ar9300/ar9300_aphrodite10.ini" 49 50 51/* Include various freebsd specific HAL methods */ 52#include "ar9300/ar9300_freebsd.h" 53 54/* XXX duplicate in ar9300_radio.c ? */ 55static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, 56 struct ieee80211_channel *chan); 57 58static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); 59static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); 60static inline void ar9300_hw_detach(struct ath_hal *ah); 61static int16_t ar9300_get_nf_adjust(struct ath_hal *ah, 62 const HAL_CHANNEL_INTERNAL *c); 63#if 0 64int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 65 HAL_CAL_QUERY query); 66#endif 67 68#if ATH_TRAFFIC_FAST_RECOVER 69unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); 70#endif 71static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid); 72 73 74static void 75ar9300_disable_pcie_phy(struct ath_hal *ah); 76 77static const HAL_PERCAL_DATA iq_cal_single_sample = 78 {IQ_MISMATCH_CAL, 79 MIN_CAL_SAMPLES, 80 PER_MAX_LOG_COUNT, 81 ar9300_iq_cal_collect, 82 ar9300_iq_calibration}; 83 84#if 0 85static HAL_CALIBRATION_TIMER ar9300_cals[] = 86 { {IQ_MISMATCH_CAL, /* Cal type */ 87 1200000, /* Cal interval */ 88 0 /* Cal timestamp */ 89 }, 90 {TEMP_COMP_CAL, 91 5000, 92 0 93 }, 94 }; 95#endif 96 97#if ATH_PCIE_ERROR_MONITOR 98 99int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) 100{ 101 u_int32_t val; 102 103 /* Clear the counters */ 104 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0); 105 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0); 106 107 /* Read the previous value */ 108 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 109 110 /* Set auto_stop */ 111 if (b_auto_stop) { 112 val |= 113 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 114 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 115 RPLY_NUM_RO_ERR_CTR_AUTO_STOP; 116 } else { 117 val &= ~( 118 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 119 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 120 RPLY_NUM_RO_ERR_CTR_AUTO_STOP); 121 } 122 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 123 124 /* 125 * Start to run. 126 * This has to be done separately from the above auto_stop flag setting, 127 * to avoid a HW race condition. 128 */ 129 val |= 130 RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | 131 RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN; 132 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val); 133 134 return 0; 135} 136 137int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters) 138{ 139 u_int32_t val; 140 ar_pcie_error_moniter_counters *p_counters = 141 (ar_pcie_error_moniter_counters*) p_read_counters; 142 143 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0); 144 145 p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); 146 p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); 147 p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); 148 149 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1); 150 151 p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); 152 p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); 153 154 return 0; 155} 156 157int ar9300_stop_pcie_error_monitor(struct ath_hal *ah) 158{ 159 u_int32_t val; 160 161 /* Read the previous value */ 162 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 163 164 val &= ~( 165 RCVD_ERR_CTR_RUN | 166 BAD_TLP_ERR_CTR_RUN | 167 BAD_DLLP_ERR_CTR_RUN | 168 RPLY_TO_ERR_CTR_RUN | 169 RPLY_NUM_RO_ERR_CTR_RUN); 170 171 /* Start to stop */ 172 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 173 174 return 0; 175} 176 177#endif /* ATH_PCIE_ERROR_MONITOR */ 178 179#if 0 180/* WIN32 does not support C99 */ 181static const struct ath_hal_private ar9300hal = { 182 { 183 ar9300_get_rate_table, /* ah_get_rate_table */ 184 ar9300_detach, /* ah_detach */ 185 186 /* Reset Functions */ 187 ar9300_reset, /* ah_reset */ 188 ar9300_phy_disable, /* ah_phy_disable */ 189 ar9300_disable, /* ah_disable */ 190 ar9300_config_pci_power_save, /* ah_config_pci_power_save */ 191 ar9300_set_pcu_config, /* ah_set_pcu_config */ 192 ar9300_calibration, /* ah_per_calibration */ 193 ar9300_reset_cal_valid, /* ah_reset_cal_valid */ 194 ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */ 195 196#if ATH_ANT_DIV_COMB 197 ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */ 198#endif /* ATH_ANT_DIV_COMB */ 199#ifdef ATH_SUPPORT_DFS 200 ar9300_radar_wait, /* ah_radar_wait */ 201 202 /* New DFS functions */ 203 ar9300_check_dfs, /* ah_ar_check_dfs */ 204 ar9300_dfs_found, /* ah_ar_dfs_found */ 205 ar9300_enable_dfs, /* ah_ar_enable_dfs */ 206 ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */ 207 ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */ 208 ar9300_adjust_difs, /* ah_adjust_difs */ 209 ar9300_dfs_config_fft, /* ah_dfs_config_fft */ 210 ar9300_dfs_cac_war, /* ah_dfs_cac_war */ 211 ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */ 212#endif 213 ar9300_get_extension_channel, /* ah_get_extension_channel */ 214 ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */ 215 216 /* Transmit functions */ 217 ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */ 218 ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */ 219 ar9300_setup_tx_queue, /* ah_setup_tx_queue */ 220 ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */ 221 ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */ 222 ar9300_release_tx_queue, /* ah_release_tx_queue */ 223 ar9300_reset_tx_queue, /* ah_reset_tx_queue */ 224 ar9300_get_tx_dp, /* ah_get_tx_dp */ 225 ar9300_set_tx_dp, /* ah_set_tx_dp */ 226 ar9300_num_tx_pending, /* ah_num_tx_pending */ 227 ar9300_start_tx_dma, /* ah_start_tx_dma */ 228 ar9300_stop_tx_dma, /* ah_stop_tx_dma */ 229 ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */ 230 ar9300_abort_tx_dma, /* ah_abort_tx_dma */ 231 ar9300_fill_tx_desc, /* ah_fill_tx_desc */ 232 ar9300_set_desc_link, /* ah_set_desc_link */ 233 ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */ 234 ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */ 235#ifdef ATH_SWRETRY 236 ar9300_clear_dest_mask, /* ah_clear_dest_mask */ 237#endif 238 ar9300_proc_tx_desc, /* ah_proc_tx_desc */ 239 ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */ 240 ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */ 241 AH_NULL, /* ah_get_tx_intr_queue */ 242 ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */ 243 ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */ 244 ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */ 245 246 /* RX Functions */ 247 ar9300_get_rx_dp, /* ah_get_rx_dp */ 248 ar9300_set_rx_dp, /* ah_set_rx_dp */ 249 ar9300_enable_receive, /* ah_enable_receive */ 250 ar9300_stop_dma_receive, /* ah_stop_dma_receive */ 251 ar9300_start_pcu_receive, /* ah_start_pcu_receive */ 252 ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */ 253 ar9300_set_multicast_filter, /* ah_set_multicast_filter */ 254 ar9300_get_rx_filter, /* ah_get_rx_filter */ 255 ar9300_set_rx_filter, /* ah_set_rx_filter */ 256 ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */ 257 ar9300_set_rx_abort, /* ah_set_rx_abort */ 258 AH_NULL, /* ah_setup_rx_desc */ 259 ar9300_proc_rx_desc, /* ah_proc_rx_desc */ 260 ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */ 261 ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */ 262 ar9300_ani_ar_poll, /* ah_rx_monitor */ 263 ar9300_process_mib_intr, /* ah_proc_mib_event */ 264 265 /* Misc Functions */ 266 ar9300_get_capability, /* ah_get_capability */ 267 ar9300_set_capability, /* ah_set_capability */ 268 ar9300_get_diag_state, /* ah_get_diag_state */ 269 ar9300_get_mac_address, /* ah_get_mac_address */ 270 ar9300_set_mac_address, /* ah_set_mac_address */ 271 ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */ 272 ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */ 273 ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */ 274 ar9300_set_led_state, /* ah_set_led_state */ 275 ar9300_set_power_led_state, /* ah_setpowerledstate */ 276 ar9300_set_network_led_state, /* ah_setnetworkledstate */ 277 ar9300_write_associd, /* ah_write_associd */ 278 ar9300_force_tsf_sync, /* ah_force_tsf_sync */ 279 ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */ 280 ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */ 281 ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */ 282 ar9300_gpio_get, /* ah_gpio_get */ 283 ar9300_gpio_set, /* ah_gpio_set */ 284 ar9300_gpio_get_intr, /* ah_gpio_get_intr */ 285 ar9300_gpio_set_intr, /* ah_gpio_set_intr */ 286 ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */ 287 ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */ 288 ar9300_gpio_get_mask, /* ah_gpio_get_mask */ 289 ar9300_gpio_set_mask, /* ah_gpio_set_mask */ 290 ar9300_get_tsf32, /* ah_get_tsf32 */ 291 ar9300_get_tsf64, /* ah_get_tsf64 */ 292 ar9300_get_tsf2_32, /* ah_get_tsf2_32 */ 293 ar9300_reset_tsf, /* ah_reset_tsf */ 294 ar9300_detect_card_present, /* ah_detect_card_present */ 295 ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */ 296 ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */ 297 ar9300_get_rfgain, /* ah_get_rf_gain */ 298 ar9300_get_def_antenna, /* ah_get_def_antenna */ 299 ar9300_set_def_antenna, /* ah_set_def_antenna */ 300 ar9300_set_slot_time, /* ah_set_slot_time */ 301 ar9300_set_ack_timeout, /* ah_set_ack_timeout */ 302 ar9300_get_ack_timeout, /* ah_get_ack_timeout */ 303 ar9300_set_coverage_class, /* ah_set_coverage_class */ 304 ar9300_set_quiet, /* ah_set_quiet */ 305 ar9300_set_antenna_switch, /* ah_set_antenna_switch */ 306 ar9300_get_desc_info, /* ah_get_desc_info */ 307 ar9300_select_ant_config, /* ah_select_ant_config */ 308 ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */ 309 ar9300_ant_swcom_sel, /* ah_ant_swcom_sel */ 310 ar9300_enable_tpc, /* ah_enable_tpc */ 311 AH_NULL, /* ah_olpc_temp_compensation */ 312#if ATH_SUPPORT_CRDC 313 ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/ 314#endif 315 ar9300_disable_phy_restart, /* ah_disable_phy_restart */ 316 ar9300_enable_keysearch_always, 317 ar9300_interference_is_present, /* ah_interference_is_present */ 318 ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */ 319 ar9300_get_tpc_tables, /* ah_get_tpc_tables */ 320 /* Key Cache Functions */ 321 ar9300_get_key_cache_size, /* ah_get_key_cache_size */ 322 ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */ 323 ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */ 324 ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */ 325 ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */ 326 ar9300_print_keycache, /* ah_print_key_cache */ 327#if ATH_SUPPORT_KEYPLUMB_WAR 328 ar9300_check_key_cache_entry, /* ah_check_key_cache_entry */ 329#endif 330 /* Power Management Functions */ 331 ar9300_set_power_mode, /* ah_set_power_mode */ 332 ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */ 333#if ATH_WOW 334 ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */ 335 ar9300_wow_enable, /* ah_wow_enable */ 336 ar9300_wow_wake_up, /* ah_wow_wake_up */ 337#if ATH_WOW_OFFLOAD 338 ar9300_wowoffload_prep, /* ah_wow_offload_prep */ 339 ar9300_wowoffload_post, /* ah_wow_offload_post */ 340 ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */ 341 ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */ 342 ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */ 343 ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */ 344 ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */ 345 ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */ 346#endif /* ATH_WOW_OFFLOAD */ 347#endif 348 349 /* Get Channel Noise */ 350 ath_hal_get_chan_noise, /* ah_get_chan_noise */ 351 ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */ 352 ar9300_get_nf_from_reg, /* ah_get_nf_from_reg */ 353 ar9300_get_rx_nf_offset, /* ah_get_rx_nf_offset */ 354 355 /* Beacon Functions */ 356 ar9300_beacon_init, /* ah_beacon_init */ 357 ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */ 358 359 /* Interrupt Functions */ 360 ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */ 361 ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */ 362 ar9300_get_interrupts, /* ah_get_interrupts */ 363 ar9300_set_interrupts, /* ah_set_interrupts */ 364 ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */ 365 ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */ 366 ar9300ForceVCS, 367 ar9300SetDfs3StreamFix, 368 ar9300Get3StreamSignature, 369 370 /* 11n specific functions (NOT applicable to ar9300) */ 371 ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */ 372 /* Update rxchain */ 373 ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/ 374 /*Updating locationing register */ 375 ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/ 376 /* Start PAPRD functions */ 377 ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */ 378 ar9300_paprd_init_table, /* ah_paprd_init_table */ 379 ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */ 380 ar9300_paprd_create_curve, /* ah_paprd_create_curve */ 381 ar9300_paprd_is_done, /* ah_paprd_is_done */ 382 ar9300_enable_paprd, /* ah_PAPRDEnable */ 383 ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */ 384 ar9300_is_tx_done, /* ah_is_tx_done */ 385 ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/ 386 ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */ 387 /* End PAPRD functions */ 388 ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */ 389 ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */ 390 ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */ 391 ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */ 392 ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */ 393 ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */ 394 ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */ 395 ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */ 396 ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */ 397 ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */ 398 ar9300_set_smart_antenna, /* ah_setSmartAntenna */ 399 ar9300_detect_bb_hang, /* ah_detect_bb_hang */ 400 ar9300_detect_mac_hang, /* ah_detect_mac_hang */ 401 ar9300_set_immunity, /* ah_immunity */ 402 ar9300_get_hw_hangs, /* ah_get_hang_types */ 403 ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */ 404 ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */ 405 ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */ 406 ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */ 407 ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */ 408 ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */ 409 ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */ 410 ar9300_dma_reg_dump, /* ah_dma_reg_dump */ 411 412 /* force_ppm specific functions */ 413 ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */ 414 ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */ 415 ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */ 416 ar9300_ppm_force, /* ah_ppm_force */ 417 ar9300_ppm_un_force, /* ah_ppm_un_force */ 418 ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */ 419 420 ar9300_get_spur_info, /* ah_get_spur_info */ 421 ar9300_set_spur_info, /* ah_get_spur_info */ 422 423 ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */ 424 425 ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */ 426 ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */ 427 428 /* radio measurement specific functions */ 429 ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */ 430 ar9300_get_vow_stats, /* ah_get_vow_stats */ 431 ar9300_clear_mib_counters, /* ah_clear_mib_counters */ 432#if ATH_GEN_RANDOMNESS 433 ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */ 434#endif 435#ifdef ATH_BT_COEX 436 /* Bluetooth Coexistence functions */ 437 ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */ 438 ar9300_bt_coex_config, /* ah_bt_coex_config */ 439 ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */ 440 ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */ 441 ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */ 442 ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */ 443 ar9300_bt_coex_disable, /* ah_bt_coex_disable */ 444 ar9300_bt_coex_enable, /* ah_bt_coex_enable */ 445 ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/ 446 ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/ 447#endif 448 /* Generic Timer functions */ 449 ar9300_alloc_generic_timer, /* ah_gentimer_alloc */ 450 ar9300_free_generic_timer, /* ah_gentimer_free */ 451 ar9300_start_generic_timer, /* ah_gentimer_start */ 452 ar9300_stop_generic_timer, /* ah_gentimer_stop */ 453 ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */ 454 455 ar9300_set_dcs_mode, /* ah_set_dcs_mode */ 456 ar9300_get_dcs_mode, /* ah_get_dcs_mode */ 457 458#if ATH_ANT_DIV_COMB 459 ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */ 460 ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */ 461#endif 462 463 ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */ 464 ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */ 465 ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */ 466 467#if ATH_PCIE_ERROR_MONITOR 468 ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */ 469 ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/ 470 ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/ 471#endif /* ATH_PCIE_ERROR_MONITOR */ 472 473#if ATH_SUPPORT_SPECTRAL 474 /* Spectral scan */ 475 ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */ 476 ar9300_get_spectral_params, /* ah_ar_get_spectral_config */ 477 ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */ 478 ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */ 479 ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */ 480 ar9300_is_spectral_active, /* ah_ar_is_spectral_active */ 481 ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */ 482 ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */ 483#endif /* ATH_SUPPORT_SPECTRAL */ 484 485 486 ar9300_promisc_mode, /* ah_promisc_mode */ 487 ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */ 488 ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */ 489 ar9300_set_proxy_sta, /* ah_set_proxy_sta */ 490 ar9300_get_cal_intervals, /* ah_get_cal_intervals */ 491#if ATH_TRAFFIC_FAST_RECOVER 492 ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */ 493#endif 494#ifdef ATH_SUPPORT_HTC 495 AH_NULL, 496#endif 497 498#ifdef ATH_TX99_DIAG 499 /* Tx99 functions */ 500#ifdef ATH_SUPPORT_HTC 501 AH_NULL, 502 AH_NULL, 503 AH_NULL, 504 AH_NULL, 505 AH_NULL, 506 AH_NULL, 507 AH_NULL, 508#else 509 AH_NULL, 510 AH_NULL, 511 ar9300_tx99_channel_pwr_update, /* ah_tx99channelpwrupdate */ 512 ar9300_tx99_start, /* ah_tx99start */ 513 ar9300_tx99_stop, /* ah_tx99stop */ 514 ar9300_tx99_chainmsk_setup, /* ah_tx99_chainmsk_setup */ 515 ar9300_tx99_set_single_carrier, /* ah_tx99_set_single_carrier */ 516#endif 517#endif 518 ar9300_chk_rssi_update_tx_pwr, 519 ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */ 520 ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */ 521#if ATH_SUPPORT_MCI 522 /* MCI Coexistence Functions */ 523 ar9300_mci_setup, /* ah_mci_setup */ 524 ar9300_mci_send_message, /* ah_mci_send_message */ 525 ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */ 526 ar9300_mci_state, /* ah_mci_state */ 527 ar9300_mci_detach, /* ah_mci_detach */ 528#endif 529 ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */ 530 ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */ 531 ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/ 532 ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */ 533 ar9300_mat_enable, /* ah_mat_enable */ 534 ar9300_dump_keycache, /* ah_dump_keycache */ 535 ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */ 536 ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */ 537 ar9300_set_ctl_pwr, /* ah_set_ctl_pwr */ 538 ar9300_set_txchainmaskopt, /* ah_set_txchainmaskopt */ 539 }, 540 541 ar9300_get_channel_edges, /* ah_get_channel_edges */ 542 ar9300_get_wireless_modes, /* ah_get_wireless_modes */ 543 ar9300_eeprom_read_word, /* ah_eeprom_read */ 544 AH_NULL, 545 ar9300_eeprom_dump_support, /* ah_eeprom_dump */ 546 ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */ 547 548 ar9300_get_nf_adjust, /* ah_get_nf_adjust */ 549 /* rest is zero'd by compiler */ 550}; 551#endif 552 553/* 554 * Read MAC version/revision information from Chip registers and initialize 555 * local data structures. 556 */ 557void 558ar9300_read_revisions(struct ath_hal *ah) 559{ 560 u_int32_t val; 561 562 /* XXX verify if this is the correct way to read revision on Osprey */ 563 /* new SREV format for Sowl and later */ 564 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 565 566 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { 567 /* XXX: AR_SREV register in Wasp reads 0 */ 568 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; 569 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { 570 /* XXX: AR_SREV register in Scorpion reads 0 */ 571 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; 572 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA953X) { 573 /* XXX: AR_SREV register in HoneyBEE reads 0 */ 574 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_HONEYBEE; 575 } else { 576 /* 577 * Include 6-bit Chip Type (masked to 0) 578 * to differentiate from pre-Sowl versions 579 */ 580 AH_PRIVATE(ah)->ah_macVersion = 581 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 582 } 583 584 585 586 587 588#ifdef AH_SUPPORT_HORNET 589 /* 590 * EV74984, due to Hornet 1.1 didn't update WMAC revision, 591 * so that have to read SoC's revision ID instead 592 */ 593 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) { 594#define AR_SOC_RST_REVISION_ID 0xB8060090 595#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 596 if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) 597 == AR_SREV_REVISION_HORNET_11) 598 { 599 AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11; 600 } else { 601 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 602 } 603#undef REG_READ 604#undef AR_SOC_RST_REVISION_ID 605 } else 606#endif 607 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP) 608 { 609#define AR_SOC_RST_REVISION_ID 0xB8060090 610#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 611 612 AH_PRIVATE(ah)->ah_macRev = 613 REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; 614#undef REG_READ 615#undef AR_SOC_RST_REVISION_ID 616 } 617 else 618 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 619 620 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 621 AH_PRIVATE(ah)->ah_ispcie = AH_TRUE; 622 } 623 else { 624 AH_PRIVATE(ah)->ah_ispcie = 625 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 626 } 627 628} 629 630/* 631 * Attach for an AR9300 part. 632 */ 633struct ath_hal * 634ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, 635 HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, 636 HAL_STATUS *status) 637{ 638 struct ath_hal_9300 *ahp; 639 struct ath_hal *ah; 640 struct ath_hal_private *ahpriv; 641 HAL_STATUS ecode; 642 643 HAL_NO_INTERSPERSED_READS; 644 645 /* NB: memory is returned zero'd */ 646 ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, ah_config, status); 647 if (ahp == AH_NULL) { 648 return AH_NULL; 649 } 650 ah = &ahp->ah_priv.h; 651 ar9300_init_offsets(ah, devid); 652 ahpriv = AH_PRIVATE(ah); 653// AH_PRIVATE(ah)->ah_bustype = bustype; 654 655 /* FreeBSD: to make OTP work for now, provide this.. */ 656 AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE); 657 if (AH9300(ah)->ah_cal_mem == NULL) { 658 ath_hal_printf(ah, "%s: caldata malloc failed!\n", __func__); 659 ecode = HAL_EIO; 660 goto bad; 661 } 662 663 /* 664 * If eepromdata is not NULL, copy it it into ah_cal_mem. 665 */ 666 if (eepromdata != NULL) 667 OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE); 668 669 /* XXX FreeBSD: enable RX mitigation */ 670 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 671 672 /* interrupt mitigation */ 673#ifdef AR5416_INT_MITIGATION 674 if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) { 675 ahp->ah_intr_mitigation_rx = AH_TRUE; 676 } 677#else 678 /* Enable Rx mitigation (default) */ 679 ahp->ah_intr_mitigation_rx = AH_TRUE; 680 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 681 682#endif 683#ifdef HOST_OFFLOAD 684 /* Reset default Rx mitigation values for Hornet */ 685 if (AR_SREV_HORNET(ah)) { 686 ahp->ah_intr_mitigation_rx = AH_FALSE; 687#ifdef AR5416_INT_MITIGATION 688 ah->ah_config.ath_hal_intr_mitigation_rx = 0; 689#endif 690 } 691#endif 692 693 if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) { 694 ahp->ah_intr_mitigation_tx = AH_TRUE; 695 } 696 697 /* 698 * Read back AR_WA into a permanent copy and set bits 14 and 17. 699 * We need to do this to avoid RMW of this register. 700 * Do this before calling ar9300_set_reset_reg. 701 * If not, the AR_WA register which was inited via EEPROM 702 * will get wiped out. 703 */ 704 ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); 705 /* Set Bits 14 and 17 in the AR_WA register. */ 706 ahp->ah_wa_reg_val |= 707 AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE; 708 709 if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */ 710 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__); 711 ecode = HAL_EIO; 712 goto bad; 713 } 714 715 if (AR_SREV_JUPITER(ah) 716#if ATH_WOW_OFFLOAD 717 && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14) 718#endif 719 ) 720 { 721 /* Jupiter doesn't need bit 14 to be set. */ 722 ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE; 723 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 724 } 725 726#if ATH_SUPPORT_MCI 727 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 728#if 1 729 ah->ah_btCoexSetWeights = ar9300_mci_bt_coex_set_weights; 730 ah->ah_btCoexDisable = ar9300_mci_bt_coex_disable; 731 ah->ah_btCoexEnable = ar9300_mci_bt_coex_enable; 732#endif 733 ahp->ah_mci_ready = AH_FALSE; 734 ahp->ah_mci_bt_state = MCI_BT_SLEEP; 735 ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; 736 ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN; 737 ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT; 738 ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT; 739 ahp->ah_mci_coex_bt_version_known = AH_FALSE; 740 ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */ 741 /* will be updated before boot up sequence */ 742 ahp->ah_mci_coex_is_2g = AH_TRUE; 743 ahp->ah_mci_coex_wlan_channels_update = AH_FALSE; 744 ahp->ah_mci_coex_wlan_channels[0] = 0x00000000; 745 ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff; 746 ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff; 747 ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff; 748 ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */ 749 ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */ 750 ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */ 751 ahp->ah_mci_need_flush_btinfo = AH_FALSE; 752 ahp->ah_mci_wlan_cal_seq = 0; 753 ahp->ah_mci_wlan_cal_done = 0; 754 } 755#endif /* ATH_SUPPORT_MCI */ 756 757#if ATH_WOW_OFFLOAD 758 ahp->ah_mcast_filter_l32_set = 0; 759 ahp->ah_mcast_filter_u32_set = 0; 760#endif 761 762 if (AR_SREV_HORNET(ah)) { 763#ifdef AH_SUPPORT_HORNET 764 if (!AR_SREV_HORNET_11(ah)) { 765 /* 766 * Do not check bootstrap register, which cannot be trusted 767 * due to s26 switch issue on CUS164/AP121. 768 */ 769 ahp->clk_25mhz = 1; 770 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 771 } else { 772 /* check bootstrap clock setting */ 773#define AR_SOC_SEL_25M_40M 0xB80600AC 774#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); 775#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 776 if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { 777 ahp->clk_25mhz = 0; 778 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 779 "Bootstrap clock 40MHz\n"); 780 } else { 781 ahp->clk_25mhz = 1; 782 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 783 "Bootstrap clock 25MHz\n"); 784 } 785#undef REG_READ 786#undef REG_WRITE 787#undef AR_SOC_SEL_25M_40M 788 } 789#endif /* AH_SUPPORT_HORNET */ 790 } 791 792 if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 793 /* check bootstrap clock setting */ 794#define AR9340_SOC_SEL_25M_40M 0xB80600B0 795#define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ 796#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 797 if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) { 798 ahp->clk_25mhz = 0; 799 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); 800 } else { 801 ahp->clk_25mhz = 1; 802 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 803 } 804#undef REG_READ 805#undef AR9340_SOC_SEL_25M_40M 806#undef AR9340_REF_CLK_40 807 } 808 809 if (AR_SREV_HONEYBEE(ah)) { 810 ahp->clk_25mhz = 1; 811 } 812 813 ar9300_init_pll(ah, AH_NULL); 814 815 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 816 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__); 817 ecode = HAL_EIO; 818 goto bad; 819 } 820 821 /* No serialization of Register Accesses needed. */ 822 ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF; 823 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n", 824 __func__, ah->ah_config.ah_serialise_reg_war); 825 826 /* 827 * Add mac revision check when needed. 828 * - Osprey 1.0 and 2.0 no longer supported. 829 */ 830 if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) && 831 (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) || 832 (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY && 833 ahpriv->ah_macVersion != AR_SREV_VERSION_WASP && 834 ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET && 835 ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON && 836 ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION && 837 ahpriv->ah_macVersion != AR_SREV_VERSION_HONEYBEE && 838 ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER && 839 ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) { 840 HALDEBUG(ah, HAL_DEBUG_RESET, 841 "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 842 __func__, 843 ahpriv->ah_macVersion, 844 ahpriv->ah_macRev); 845 ecode = HAL_ENOTSUPP; 846 goto bad; 847 } 848 849 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 850 851 /* Setup supported calibrations */ 852 ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; 853 ahp->ah_supp_cals = IQ_MISMATCH_CAL; 854 855 /* Enable ANI */ 856 ahp->ah_ani_function = HAL_ANI_ALL; 857 858 /* Enable RIFS */ 859 ahp->ah_rifs_enabled = AH_TRUE; 860 861 /* by default, stop RX also in abort txdma, due to 862 "Unable to stop TxDMA" msg observed */ 863 ahp->ah_abort_txdma_norx = AH_TRUE; 864 865 /* do not use optional tx chainmask by default */ 866 ahp->ah_tx_chainmaskopt = 0; 867 868 ahp->ah_skip_rx_iq_cal = AH_FALSE; 869 ahp->ah_rx_cal_complete = AH_FALSE; 870 ahp->ah_rx_cal_chan = 0; 871 ahp->ah_rx_cal_chan_flag = 0; 872 873 HALDEBUG(ah, HAL_DEBUG_RESET, 874 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 875 ahpriv->ah_macVersion, 876 ahpriv->ah_macRev); 877 878 if (AR_SREV_HORNET_12(ah)) { 879 /* mac */ 880 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 881 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 882 ar9331_hornet1_2_mac_core, 883 ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2); 884 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 885 ar9331_hornet1_2_mac_postamble, 886 ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5); 887 888 /* bb */ 889 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 890 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 891 ar9331_hornet1_2_baseband_core, 892 ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2); 893 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 894 ar9331_hornet1_2_baseband_postamble, 895 ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5); 896 897 /* radio */ 898 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 899 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 900 ar9331_hornet1_2_radio_core, 901 ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2); 902 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 903 904 /* soc */ 905 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 906 ar9331_hornet1_2_soc_preamble, 907 ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2); 908 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 909 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 910 ar9331_hornet1_2_soc_postamble, 911 ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2); 912 913 /* rx/tx gain */ 914 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 915 ar9331_common_rx_gain_hornet1_2, 916 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 917 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 918 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 919 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 920 921 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 922 923 /* Japan 2484Mhz CCK settings */ 924 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 925 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484, 926 ARRAY_LENGTH( 927 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2); 928 929#if 0 /* ATH_WOW */ 930 /* SerDes values during WOW sleep */ 931 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 932 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 933#endif 934 935 /* additional clock settings */ 936 if (AH9300(ah)->clk_25mhz) { 937 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 938 ar9331_hornet1_2_xtal_25M, 939 ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2); 940 } else { 941 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 942 ar9331_hornet1_2_xtal_40M, 943 ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2); 944 } 945 946 } else if (AR_SREV_HORNET_11(ah)) { 947 /* mac */ 948 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 949 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 950 ar9331_hornet1_1_mac_core, 951 ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2); 952 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 953 ar9331_hornet1_1_mac_postamble, 954 ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5); 955 956 /* bb */ 957 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 958 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 959 ar9331_hornet1_1_baseband_core, 960 ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2); 961 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 962 ar9331_hornet1_1_baseband_postamble, 963 ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5); 964 965 /* radio */ 966 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 967 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 968 ar9331_hornet1_1_radio_core, 969 ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2); 970 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 971 972 /* soc */ 973 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 974 ar9331_hornet1_1_soc_preamble, 975 ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2); 976 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 977 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 978 ar9331_hornet1_1_soc_postamble, 979 ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2); 980 981 /* rx/tx gain */ 982 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 983 ar9331_common_rx_gain_hornet1_1, 984 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 985 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 986 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 987 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 988 989 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 990 991 /* Japan 2484Mhz CCK settings */ 992 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 993 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484, 994 ARRAY_LENGTH( 995 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2); 996 997#if 0 /* ATH_WOW */ 998 /* SerDes values during WOW sleep */ 999 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1000 N(ar9300_pcie_phy_awow), 2); 1001#endif 1002 1003 /* additional clock settings */ 1004 if (AH9300(ah)->clk_25mhz) { 1005 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1006 ar9331_hornet1_1_xtal_25M, 1007 ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2); 1008 } else { 1009 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1010 ar9331_hornet1_1_xtal_40M, 1011 ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2); 1012 } 1013 1014 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 1015 /* mac */ 1016 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1017 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1018 ar9485_poseidon1_1_mac_core, 1019 ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2); 1020 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1021 ar9485_poseidon1_1_mac_postamble, 1022 ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5); 1023 1024 /* bb */ 1025 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1026 ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2); 1027 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1028 ar9485_poseidon1_1_baseband_core, 1029 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2); 1030 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1031 ar9485_poseidon1_1_baseband_postamble, 1032 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5); 1033 1034 /* radio */ 1035 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1036 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1037 ar9485_poseidon1_1_radio_core, 1038 ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2); 1039 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1040 ar9485_poseidon1_1_radio_postamble, 1041 ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2); 1042 1043 /* soc */ 1044 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1045 ar9485_poseidon1_1_soc_preamble, 1046 ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2); 1047 1048 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1049 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1050 1051 /* rx/tx gain */ 1052 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1053 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 1054 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 1055 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1056 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 1057 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 1058 1059 /* Japan 2484Mhz CCK settings */ 1060 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1061 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484, 1062 ARRAY_LENGTH( 1063 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); 1064 1065 /* Load PCIE SERDES settings from INI */ 1066 if (ah->ah_config.ath_hal_pcie_clock_req) { 1067 /* Pci-e Clock Request = 1 */ 1068 if (ah->ah_config.ath_hal_pll_pwr_save 1069 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1070 { 1071 /* Sleep Setting */ 1072 if (ah->ah_config.ath_hal_pll_pwr_save & 1073 AR_PCIE_PLL_PWRSAVE_ON_D3) 1074 { 1075 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1076 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1077 ARRAY_LENGTH( 1078 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1079 2); 1080 } else { 1081 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1082 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1083 ARRAY_LENGTH( 1084 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1085 2); 1086 } 1087 /* Awake Setting */ 1088 if (ah->ah_config.ath_hal_pll_pwr_save & 1089 AR_PCIE_PLL_PWRSAVE_ON_D0) 1090 { 1091 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1092 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1093 ARRAY_LENGTH( 1094 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1095 2); 1096 } else { 1097 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1098 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1099 ARRAY_LENGTH( 1100 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1101 2); 1102 } 1103 1104 } else { 1105 /*Use driver default setting*/ 1106 /* Sleep Setting */ 1107 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1108 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1109 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1110 2); 1111 /* Awake Setting */ 1112 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1113 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1114 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1115 2); 1116 } 1117 } else { 1118 /* Pci-e Clock Request = 0 */ 1119 if (ah->ah_config.ath_hal_pll_pwr_save 1120 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1121 { 1122 /* Sleep Setting */ 1123 if (ah->ah_config.ath_hal_pll_pwr_save & 1124 AR_PCIE_PLL_PWRSAVE_ON_D3) 1125 { 1126 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1127 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1128 ARRAY_LENGTH( 1129 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1130 2); 1131 } else { 1132 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1133 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1134 ARRAY_LENGTH( 1135 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1136 2); 1137 } 1138 /* Awake Setting */ 1139 if (ah->ah_config.ath_hal_pll_pwr_save & 1140 AR_PCIE_PLL_PWRSAVE_ON_D0) 1141 { 1142 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1143 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1144 ARRAY_LENGTH( 1145 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1146 2); 1147 } else { 1148 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1149 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1150 ARRAY_LENGTH( 1151 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1152 2); 1153 } 1154 1155 } else { 1156 /*Use driver default setting*/ 1157 /* Sleep Setting */ 1158 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1159 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1160 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1161 2); 1162 /* Awake Setting */ 1163 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1164 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1165 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1166 2); 1167 } 1168 } 1169 /* pcie ps setting will honor registry setting, default is 0 */ 1170 //ah->ah_config.ath_hal_pciePowerSaveEnable = 0; 1171 } else if (AR_SREV_POSEIDON(ah)) { 1172 /* mac */ 1173 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1174 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1175 ar9485_poseidon1_0_mac_core, 1176 ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2); 1177 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1178 ar9485_poseidon1_0_mac_postamble, 1179 ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5); 1180 1181 /* bb */ 1182 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1183 ar9485_poseidon1_0, 1184 ARRAY_LENGTH(ar9485_poseidon1_0), 2); 1185 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1186 ar9485_poseidon1_0_baseband_core, 1187 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2); 1188 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1189 ar9485_poseidon1_0_baseband_postamble, 1190 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5); 1191 1192 /* radio */ 1193 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1194 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1195 ar9485_poseidon1_0_radio_core, 1196 ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2); 1197 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1198 ar9485_poseidon1_0_radio_postamble, 1199 ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2); 1200 1201 /* soc */ 1202 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1203 ar9485_poseidon1_0_soc_preamble, 1204 ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2); 1205 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1206 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1207 1208 /* rx/tx gain */ 1209 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1210 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 1211 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 1212 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1213 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 1214 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 1215 1216 /* Japan 2484Mhz CCK settings */ 1217 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1218 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484, 1219 ARRAY_LENGTH( 1220 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); 1221 1222 /* Load PCIE SERDES settings from INI */ 1223 if (ah->ah_config.ath_hal_pcie_clock_req) { 1224 /* Pci-e Clock Request = 1 */ 1225 if (ah->ah_config.ath_hal_pll_pwr_save 1226 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1227 { 1228 /* Sleep Setting */ 1229 if (ah->ah_config.ath_hal_pll_pwr_save & 1230 AR_PCIE_PLL_PWRSAVE_ON_D3) 1231 { 1232 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1233 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1234 ARRAY_LENGTH( 1235 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1236 2); 1237 } else { 1238 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1239 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1240 ARRAY_LENGTH( 1241 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1242 2); 1243 } 1244 /* Awake Setting */ 1245 if (ah->ah_config.ath_hal_pll_pwr_save & 1246 AR_PCIE_PLL_PWRSAVE_ON_D0) 1247 { 1248 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1249 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1250 ARRAY_LENGTH( 1251 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1252 2); 1253 } else { 1254 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1255 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1256 ARRAY_LENGTH( 1257 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1258 2); 1259 } 1260 1261 } else { 1262 /*Use driver default setting*/ 1263 /* Sleep Setting */ 1264 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1265 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1266 ARRAY_LENGTH( 1267 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1268 2); 1269 /* Awake Setting */ 1270 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1271 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1272 ARRAY_LENGTH( 1273 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1274 2); 1275 } 1276 } else { 1277 /* Pci-e Clock Request = 0 */ 1278 if (ah->ah_config.ath_hal_pll_pwr_save 1279 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1280 { 1281 /* Sleep Setting */ 1282 if (ah->ah_config.ath_hal_pll_pwr_save & 1283 AR_PCIE_PLL_PWRSAVE_ON_D3) 1284 { 1285 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1286 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1287 ARRAY_LENGTH( 1288 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1289 2); 1290 } else { 1291 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1292 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1293 ARRAY_LENGTH( 1294 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1295 2); 1296 } 1297 /* Awake Setting */ 1298 if (ah->ah_config.ath_hal_pll_pwr_save & 1299 AR_PCIE_PLL_PWRSAVE_ON_D0) 1300 { 1301 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1302 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1303 ARRAY_LENGTH( 1304 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1305 2); 1306 } else { 1307 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1308 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1309 ARRAY_LENGTH( 1310 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1311 2); 1312 } 1313 1314 } else { 1315 /*Use driver default setting*/ 1316 /* Sleep Setting */ 1317 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1318 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1319 ARRAY_LENGTH( 1320 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1321 2); 1322 /* Awake Setting */ 1323 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1324 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1325 ARRAY_LENGTH( 1326 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1327 2); 1328 } 1329 } 1330 /* pcie ps setting will honor registry setting, default is 0 */ 1331 /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/ 1332 1333#if 0 /* ATH_WOW */ 1334 /* SerDes values during WOW sleep */ 1335 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1336 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1337#endif 1338 1339 } else if (AR_SREV_WASP(ah)) { 1340 /* mac */ 1341 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1342 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1343 ar9340_wasp_1p0_mac_core, 1344 ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2); 1345 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1346 ar9340_wasp_1p0_mac_postamble, 1347 ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5); 1348 1349 /* bb */ 1350 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1351 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1352 ar9340_wasp_1p0_baseband_core, 1353 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2); 1354 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1355 ar9340_wasp_1p0_baseband_postamble, 1356 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5); 1357 1358 /* radio */ 1359 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1360 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1361 ar9340_wasp_1p0_radio_core, 1362 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2); 1363 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1364 ar9340_wasp_1p0_radio_postamble, 1365 ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5); 1366 1367 /* soc */ 1368 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1369 ar9340_wasp_1p0_soc_preamble, 1370 ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2); 1371 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1372 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1373 ar9340_wasp_1p0_soc_postamble, 1374 ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5); 1375 1376 /* rx/tx gain */ 1377 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1378 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 1379 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 1380 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1381 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 1382 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 1383 1384 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1385 1386 /* Fast clock modal settings */ 1387 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1388 ar9340Modes_fast_clock_wasp_1p0, 1389 ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3); 1390 1391 /* XXX TODO: need to add this for freebsd; it's missing from the current .ini files */ 1392#if 0 1393 /* Japan 2484Mhz CCK settings */ 1394 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1395 ar9340_wasp_1p0_baseband_core_txfir_coeff_japan_2484, 1396 ARRAY_LENGTH( 1397 ar9340_wasp_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1398#endif 1399 1400 /* Additional setttings for 40Mhz */ 1401 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, 1402 ar9340_wasp_1p0_radio_core_40M, 1403 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2); 1404 1405 /* DFS */ 1406 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1407 ar9340_wasp_1p0_baseband_postamble_dfs_channel, 1408 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3); 1409 } else if (AR_SREV_SCORPION(ah)) { 1410 /* mac */ 1411 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1412 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1413 ar955x_scorpion_1p0_mac_core, 1414 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2); 1415 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1416 ar955x_scorpion_1p0_mac_postamble, 1417 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5); 1418 1419 /* bb */ 1420 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1421 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1422 ar955x_scorpion_1p0_baseband_core, 1423 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2); 1424 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1425 ar955x_scorpion_1p0_baseband_postamble, 1426 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5); 1427 1428 /* radio */ 1429 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1430 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1431 ar955x_scorpion_1p0_radio_core, 1432 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2); 1433 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1434 ar955x_scorpion_1p0_radio_postamble, 1435 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5); 1436 1437 /* soc */ 1438 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1439 ar955x_scorpion_1p0_soc_preamble, 1440 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2); 1441 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1442 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1443 ar955x_scorpion_1p0_soc_postamble, 1444 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5); 1445 1446 /* rx/tx gain */ 1447 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1448 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 1449 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 1450 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1451 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 1452 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 1453 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1454 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 1455 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5); 1456 1457 /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1458 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1459 1460 /* Fast clock modal settings */ 1461 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1462 ar955xModes_fast_clock_scorpion_1p0, 1463 ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3); 1464 1465 /* Additional setttings for 40Mhz */ 1466 //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1467 // ar955x_scorpion_1p0_radio_core_40M, 1468 // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2); 1469 } else if (AR_SREV_HONEYBEE(ah)) { 1470 /* mac */ 1471 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1472 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1473 qca953x_honeybee_1p0_mac_core, 1474 ARRAY_LENGTH(qca953x_honeybee_1p0_mac_core), 2); 1475 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1476 qca953x_honeybee_1p0_mac_postamble, 1477 ARRAY_LENGTH(qca953x_honeybee_1p0_mac_postamble), 5); 1478 1479 /* bb */ 1480 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1481 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1482 qca953x_honeybee_1p0_baseband_core, 1483 ARRAY_LENGTH(qca953x_honeybee_1p0_baseband_core), 2); 1484 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1485 qca953x_honeybee_1p0_baseband_postamble, 1486 ARRAY_LENGTH(qca953x_honeybee_1p0_baseband_postamble), 5); 1487 1488 /* radio */ 1489 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1490 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1491 qca953x_honeybee_1p0_radio_core, 1492 ARRAY_LENGTH(qca953x_honeybee_1p0_radio_core), 2); 1493 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1494 qca953x_honeybee_1p0_radio_postamble, 1495 ARRAY_LENGTH(qca953x_honeybee_1p0_radio_postamble), 5); 1496 1497 /* soc */ 1498 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1499 qca953x_honeybee_1p0_soc_preamble, 1500 ARRAY_LENGTH(qca953x_honeybee_1p0_soc_preamble), 2); 1501 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1502 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1503 qca953x_honeybee_1p0_soc_postamble, 1504 ARRAY_LENGTH(qca953x_honeybee_1p0_soc_postamble), 5); 1505 1506 /* rx/tx gain */ 1507 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1508 qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0, 1509 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0), 2); 1510 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1511 qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0, 1512 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0), 5); 1513 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1514 qca953xModes_no_xpa_tx_gain_table_honeybee_1p0, 1515 ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p0), 2); 1516 1517 /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1518 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1519 1520 /* Fast clock modal settings */ 1521 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1522 qca953xModes_fast_clock_honeybee_1p0, 1523 ARRAY_LENGTH(qca953xModes_fast_clock_honeybee_1p0), 3); 1524 1525 /* Additional setttings for 40Mhz */ 1526 //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1527 // qca953x_honeybee_1p0_radio_core_40M, 1528 // ARRAY_LENGTH(qca953x_honeybee_1p0_radio_core_40M), 2); 1529 1530 } else if (AR_SREV_JUPITER_10(ah)) { 1531 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1532 1533 /* mac */ 1534 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1535 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1536 ar9300_jupiter_1p0_mac_core, 1537 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2); 1538 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1539 ar9300_jupiter_1p0_mac_postamble, 1540 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5); 1541 1542 /* bb */ 1543 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1544 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1545 ar9300_jupiter_1p0_baseband_core, 1546 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2); 1547 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1548 ar9300_jupiter_1p0_baseband_postamble, 1549 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5); 1550 1551 /* radio */ 1552 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1553 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1554 ar9300_jupiter_1p0_radio_core, 1555 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2); 1556 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1557 ar9300_jupiter_1p0_radio_postamble, 1558 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5); 1559 1560 /* soc */ 1561 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1562 ar9300_jupiter_1p0_soc_preamble, 1563 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2); 1564 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1565 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1566 ar9300_jupiter_1p0_soc_postamble, 1567 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5); 1568 1569 /* rx/tx gain */ 1570 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1571 ar9300_common_rx_gain_table_jupiter_1p0, 1572 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 1573 1574 /* Load PCIE SERDES settings from INI */ 1575 if (ah->ah_config.ath_hal_pcie_clock_req) { 1576 /* Pci-e Clock Request = 1 */ 1577 /* 1578 * PLL ON + clkreq enable is not a valid combination, 1579 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1580 */ 1581 { 1582 /*Use driver default setting*/ 1583 /* Awake -> Sleep Setting */ 1584 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1585 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1586 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1587 2); 1588 /* Sleep -> Awake Setting */ 1589 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1590 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1591 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1592 2); 1593 } 1594 } 1595 else { 1596 /* 1597 * Since Jupiter 1.0 and 2.0 share the same device id and will be 1598 * installed with same INF, but Jupiter 1.0 has issue with PLL OFF. 1599 * 1600 * Force Jupiter 1.0 to use ON/ON setting. 1601 */ 1602 ah->ah_config.ath_hal_pll_pwr_save = 0; 1603 /* Pci-e Clock Request = 0 */ 1604 if (ah->ah_config.ath_hal_pll_pwr_save & 1605 AR_PCIE_PLL_PWRSAVE_CONTROL) 1606 { 1607 /* Awake -> Sleep Setting */ 1608 if (ah->ah_config.ath_hal_pll_pwr_save & 1609 AR_PCIE_PLL_PWRSAVE_ON_D3) 1610 { 1611 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1612 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1613 ARRAY_LENGTH( 1614 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1615 2); 1616 } 1617 else { 1618 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1619 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1620 ARRAY_LENGTH( 1621 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1622 2); 1623 } 1624 /* Sleep -> Awake Setting */ 1625 if (ah->ah_config.ath_hal_pll_pwr_save & 1626 AR_PCIE_PLL_PWRSAVE_ON_D0) 1627 { 1628 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1629 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1630 ARRAY_LENGTH( 1631 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1632 2); 1633 } 1634 else { 1635 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1636 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1637 ARRAY_LENGTH( 1638 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1639 2); 1640 } 1641 1642 } 1643 else { 1644 /*Use driver default setting*/ 1645 /* Awake -> Sleep Setting */ 1646 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1647 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1648 ARRAY_LENGTH( 1649 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1650 2); 1651 /* Sleep -> Awake Setting */ 1652 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1653 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1654 ARRAY_LENGTH( 1655 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1656 2); 1657 } 1658 } 1659 /* 1660 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1661 * 0 for merlin 1662 */ 1663 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1664 1665#if 0 // ATH_WOW 1666 /* SerDes values during WOW sleep */ 1667 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1668 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1669#endif 1670 1671 /* Fast clock modal settings */ 1672 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1673 ar9300_modes_fast_clock_jupiter_1p0, 1674 ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3); 1675 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1676 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484, 1677 ARRAY_LENGTH( 1678 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1679 1680 } 1681 else if (AR_SREV_JUPITER_20_OR_LATER(ah)) { 1682 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1683 1684 /* FreeBSD: just override the registers for jupiter 2.1 */ 1685 /* XXX TODO: refactor this stuff out; reinit all the 2.1 registers */ 1686 1687 /* mac */ 1688 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1689 1690 if (AR_SREV_JUPITER_21(ah)) { 1691 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1692 ar9462_2p1_mac_core, 1693 ARRAY_LENGTH(ar9462_2p1_mac_core), 2); 1694 } else { 1695 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1696 ar9300_jupiter_2p0_mac_core, 1697 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); 1698 } 1699 1700 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1701 ar9300_jupiter_2p0_mac_postamble, 1702 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5); 1703 1704 /* bb */ 1705 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1706 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1707 ar9300_jupiter_2p0_baseband_core, 1708 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2); 1709 1710 if (AR_SREV_JUPITER_21(ah)) { 1711 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1712 ar9462_2p1_baseband_postamble, 1713 ARRAY_LENGTH(ar9462_2p1_baseband_postamble), 5); 1714 } else { 1715 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1716 ar9300_jupiter_2p0_baseband_postamble, 1717 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); 1718 } 1719 1720 /* radio */ 1721 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1722 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1723 ar9300_jupiter_2p0_radio_core, 1724 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2); 1725 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1726 ar9300_jupiter_2p0_radio_postamble, 1727 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5); 1728 INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant, 1729 ar9300_jupiter_2p0_radio_postamble_sys2ant, 1730 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5); 1731 1732 /* soc */ 1733 if (AR_SREV_JUPITER_21(ah)) { 1734 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1735 ar9462_2p1_soc_preamble, 1736 ARRAY_LENGTH(ar9462_2p1_soc_preamble), 2); 1737 } else { 1738 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1739 ar9300_jupiter_2p0_soc_preamble, 1740 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); 1741 } 1742 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1743 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1744 ar9300_jupiter_2p0_soc_postamble, 1745 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5); 1746 1747 /* rx/tx gain */ 1748 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1749 ar9300Common_rx_gain_table_jupiter_2p0, 1750 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 1751 1752 /* BTCOEX */ 1753 INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR, 1754 ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table, 1755 ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2); 1756 1757 /* Load PCIE SERDES settings from INI */ 1758 if (ah->ah_config.ath_hal_pcie_clock_req) { 1759 /* Pci-e Clock Request = 1 */ 1760 /* 1761 * PLL ON + clkreq enable is not a valid combination, 1762 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1763 */ 1764 { 1765 /*Use driver default setting*/ 1766 /* Awake -> Sleep Setting */ 1767 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1768 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1769 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1770 2); 1771 /* Sleep -> Awake Setting */ 1772 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1773 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1774 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1775 2); 1776 } 1777 } 1778 else { 1779 /* Pci-e Clock Request = 0 */ 1780 if (ah->ah_config.ath_hal_pll_pwr_save & 1781 AR_PCIE_PLL_PWRSAVE_CONTROL) 1782 { 1783 /* Awake -> Sleep Setting */ 1784 if (ah->ah_config.ath_hal_pll_pwr_save & 1785 AR_PCIE_PLL_PWRSAVE_ON_D3) 1786 { 1787 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1788 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1789 ARRAY_LENGTH( 1790 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1791 2); 1792 } 1793 else { 1794 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1795 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1796 ARRAY_LENGTH( 1797 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1798 2); 1799 } 1800 /* Sleep -> Awake Setting */ 1801 if (ah->ah_config.ath_hal_pll_pwr_save & 1802 AR_PCIE_PLL_PWRSAVE_ON_D0) 1803 { 1804 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1805 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1806 ARRAY_LENGTH( 1807 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1808 2); 1809 } 1810 else { 1811 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1812 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1813 ARRAY_LENGTH( 1814 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1815 2); 1816 } 1817 1818 } 1819 else { 1820 /*Use driver default setting*/ 1821 /* Awake -> Sleep Setting */ 1822 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1823 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1824 ARRAY_LENGTH( 1825 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1826 2); 1827 /* Sleep -> Awake Setting */ 1828 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1829 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1830 ARRAY_LENGTH( 1831 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1832 2); 1833 } 1834 } 1835 1836 /* 1837 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1838 * 0 for merlin 1839 */ 1840 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1841 1842#if 0 // ATH_WOW 1843 /* SerDes values during WOW sleep */ 1844 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1845 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1846#endif 1847 1848 /* Fast clock modal settings */ 1849 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1850 ar9300Modes_fast_clock_jupiter_2p0, 1851 ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3); 1852 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1853 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484, 1854 ARRAY_LENGTH( 1855 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2); 1856 1857 } else if (AR_SREV_APHRODITE(ah)) { 1858 /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */ 1859 1860 /* mac */ 1861 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1862 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1863 ar956X_aphrodite_1p0_mac_core, 1864 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2); 1865 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1866 ar956X_aphrodite_1p0_mac_postamble, 1867 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5); 1868 1869 /* bb */ 1870 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1871 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1872 ar956X_aphrodite_1p0_baseband_core, 1873 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2); 1874 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1875 ar956X_aphrodite_1p0_baseband_postamble, 1876 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5); 1877 1878//mark jupiter have but aphrodite don't have 1879// /* radio */ 1880// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1881// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1882// ar9300_aphrodite_1p0_radio_core, 1883// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2); 1884// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1885// ar9300_aphrodite_1p0_radio_postamble, 1886// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5); 1887 1888 /* soc */ 1889 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1890 ar956X_aphrodite_1p0_soc_preamble, 1891 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2); 1892 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1893 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1894 ar956X_aphrodite_1p0_soc_postamble, 1895 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5); 1896 1897 /* rx/tx gain */ 1898 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1899 ar956XCommon_rx_gain_table_aphrodite_1p0, 1900 ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2); 1901 //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1902 // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0, 1903 // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0), 1904 // 5); 1905 1906 1907 /* 1908 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1909 * 0 for merlin 1910 */ 1911 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1912 1913#if 0 // ATH_WOW 1914 /* SerDes values during WOW sleep */ 1915 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1916 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1917#endif 1918 /* Fast clock modal settings */ 1919 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1920 ar956XModes_fast_clock_aphrodite_1p0, 1921 ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3); 1922 1923 } else if (AR_SREV_AR9580(ah)) { 1924 /* 1925 * AR9580/Peacock - 1926 * new INI format (pre, core, post arrays per subsystem) 1927 */ 1928 1929 /* mac */ 1930 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1931 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1932 ar9300_ar9580_1p0_mac_core, 1933 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2); 1934 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1935 ar9300_ar9580_1p0_mac_postamble, 1936 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5); 1937 1938 /* bb */ 1939 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1940 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1941 ar9300_ar9580_1p0_baseband_core, 1942 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2); 1943 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1944 ar9300_ar9580_1p0_baseband_postamble, 1945 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5); 1946 1947 /* radio */ 1948 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1949 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1950 ar9300_ar9580_1p0_radio_core, 1951 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2); 1952 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1953 ar9300_ar9580_1p0_radio_postamble, 1954 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5); 1955 1956 /* soc */ 1957 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1958 ar9300_ar9580_1p0_soc_preamble, 1959 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2); 1960 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1961 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1962 ar9300_ar9580_1p0_soc_postamble, 1963 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5); 1964 1965 /* rx/tx gain */ 1966 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1967 ar9300_common_rx_gain_table_ar9580_1p0, 1968 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 1969 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1970 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 1971 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); 1972 1973 /* DFS */ 1974 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1975 ar9300_ar9580_1p0_baseband_postamble_dfs_channel, 1976 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3); 1977 1978 1979 /* Load PCIE SERDES settings from INI */ 1980 1981 /*D3 Setting */ 1982 if (ah->ah_config.ath_hal_pcie_clock_req) { 1983 if (ah->ah_config.ath_hal_pll_pwr_save & 1984 AR_PCIE_PLL_PWRSAVE_CONTROL) 1985 { //registry control 1986 if (ah->ah_config.ath_hal_pll_pwr_save & 1987 AR_PCIE_PLL_PWRSAVE_ON_D3) 1988 { //bit1, in to D3 1989 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1990 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1991 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1992 2); 1993 } else { 1994 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1995 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1996 ARRAY_LENGTH( 1997 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1998 2); 1999 } 2000 } else {//no registry control, default is pll on 2001 INIT_INI_ARRAY( 2002 &ahp->ah_ini_pcie_serdes, 2003 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2004 ARRAY_LENGTH( 2005 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2006 2); 2007 } 2008 } else { 2009 if (ah->ah_config.ath_hal_pll_pwr_save & 2010 AR_PCIE_PLL_PWRSAVE_CONTROL) 2011 { //registry control 2012 if (ah->ah_config.ath_hal_pll_pwr_save & 2013 AR_PCIE_PLL_PWRSAVE_ON_D3) 2014 { //bit1, in to D3 2015 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2016 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 2017 ARRAY_LENGTH( 2018 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 2019 2); 2020 } else { 2021 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2022 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2023 ARRAY_LENGTH( 2024 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2025 2); 2026 } 2027 } else {//no registry control, default is pll on 2028 INIT_INI_ARRAY( 2029 &ahp->ah_ini_pcie_serdes, 2030 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2031 ARRAY_LENGTH( 2032 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2033 2); 2034 } 2035 } 2036 2037 /*D0 Setting */ 2038 if (ah->ah_config.ath_hal_pcie_clock_req) { 2039 if (ah->ah_config.ath_hal_pll_pwr_save & 2040 AR_PCIE_PLL_PWRSAVE_CONTROL) 2041 { //registry control 2042 if (ah->ah_config.ath_hal_pll_pwr_save & 2043 AR_PCIE_PLL_PWRSAVE_ON_D0) 2044 { //bit2, out of D3 2045 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2046 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 2047 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 2048 2); 2049 2050 } else { 2051 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2052 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2053 ARRAY_LENGTH( 2054 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2055 2); 2056 } 2057 } else { //no registry control, default is pll on 2058 INIT_INI_ARRAY( 2059 &ahp->ah_ini_pcie_serdes_low_power, 2060 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2061 ARRAY_LENGTH( 2062 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2063 2); 2064 } 2065 } else { 2066 if (ah->ah_config.ath_hal_pll_pwr_save & 2067 AR_PCIE_PLL_PWRSAVE_CONTROL) 2068 {//registry control 2069 if (ah->ah_config.ath_hal_pll_pwr_save & 2070 AR_PCIE_PLL_PWRSAVE_ON_D0) 2071 {//bit2, out of D3 2072 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2073 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 2074 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 2075 2); 2076 } else { 2077 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2078 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2079 ARRAY_LENGTH( 2080 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2081 2); 2082 } 2083 } else { //no registry control, default is pll on 2084 INIT_INI_ARRAY( 2085 &ahp->ah_ini_pcie_serdes_low_power, 2086 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2087 ARRAY_LENGTH( 2088 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2089 2); 2090 } 2091 } 2092 2093 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2094 2095#if 0 /* ATH_WOW */ 2096 /* SerDes values during WOW sleep */ 2097 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2098 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2099#endif 2100 2101 /* Fast clock modal settings */ 2102 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2103 ar9300Modes_fast_clock_ar9580_1p0, 2104 ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3); 2105 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2106 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484, 2107 ARRAY_LENGTH( 2108 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2); 2109 2110 } else { 2111 /* 2112 * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem) 2113 */ 2114 2115 /* mac */ 2116 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 2117 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 2118 ar9300_osprey_2p2_mac_core, 2119 ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2); 2120 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 2121 ar9300_osprey_2p2_mac_postamble, 2122 ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5); 2123 2124 /* bb */ 2125 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 2126 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 2127 ar9300_osprey_2p2_baseband_core, 2128 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2); 2129 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 2130 ar9300_osprey_2p2_baseband_postamble, 2131 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5); 2132 2133 /* radio */ 2134 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 2135 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 2136 ar9300_osprey_2p2_radio_core, 2137 ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2); 2138 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 2139 ar9300_osprey_2p2_radio_postamble, 2140 ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5); 2141 2142 /* soc */ 2143 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 2144 ar9300_osprey_2p2_soc_preamble, 2145 ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2); 2146 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 2147 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 2148 ar9300_osprey_2p2_soc_postamble, 2149 ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5); 2150 2151 /* rx/tx gain */ 2152 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 2153 ar9300_common_rx_gain_table_osprey_2p2, 2154 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 2155 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 2156 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 2157 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); 2158 2159 /* DFS */ 2160 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 2161 ar9300_osprey_2p2_baseband_postamble_dfs_channel, 2162 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3); 2163 2164 /* Load PCIE SERDES settings from INI */ 2165 2166 /*D3 Setting */ 2167 if (ah->ah_config.ath_hal_pcie_clock_req) { 2168 if (ah->ah_config.ath_hal_pll_pwr_save & 2169 AR_PCIE_PLL_PWRSAVE_CONTROL) 2170 { //registry control 2171 if (ah->ah_config.ath_hal_pll_pwr_save & 2172 AR_PCIE_PLL_PWRSAVE_ON_D3) 2173 { //bit1, in to D3 2174 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2175 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2176 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2177 2); 2178 } else { 2179 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2180 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2181 ARRAY_LENGTH( 2182 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2183 2); 2184 } 2185 } else {//no registry control, default is pll on 2186#ifndef ATH_BUS_PM 2187 INIT_INI_ARRAY( 2188 &ahp->ah_ini_pcie_serdes, 2189 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2190 ARRAY_LENGTH( 2191 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2192 2); 2193#else 2194 //no registry control, default is pll off 2195 INIT_INI_ARRAY( 2196 &ahp->ah_ini_pcie_serdes, 2197 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2198 ARRAY_LENGTH( 2199 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2200 2); 2201#endif 2202 2203 } 2204 } else { 2205 if (ah->ah_config.ath_hal_pll_pwr_save & 2206 AR_PCIE_PLL_PWRSAVE_CONTROL) 2207 { //registry control 2208 if (ah->ah_config.ath_hal_pll_pwr_save & 2209 AR_PCIE_PLL_PWRSAVE_ON_D3) 2210 { //bit1, in to D3 2211 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2212 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2213 ARRAY_LENGTH( 2214 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2215 2); 2216 } else { 2217 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2218 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2219 ARRAY_LENGTH( 2220 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2221 2); 2222 } 2223 } else { 2224#ifndef ATH_BUS_PM 2225 //no registry control, default is pll on 2226 INIT_INI_ARRAY( 2227 &ahp->ah_ini_pcie_serdes, 2228 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2229 ARRAY_LENGTH( 2230 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2231 2); 2232#else 2233 //no registry control, default is pll off 2234 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2235 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); 2236#endif 2237 } 2238 } 2239 2240 /*D0 Setting */ 2241 if (ah->ah_config.ath_hal_pcie_clock_req) { 2242 if (ah->ah_config.ath_hal_pll_pwr_save & 2243 AR_PCIE_PLL_PWRSAVE_CONTROL) 2244 { //registry control 2245 if (ah->ah_config.ath_hal_pll_pwr_save & 2246 AR_PCIE_PLL_PWRSAVE_ON_D0) 2247 { //bit2, out of D3 2248 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2249 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2250 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2251 2); 2252 2253 } else { 2254 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2255 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2256 ARRAY_LENGTH( 2257 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2258 2); 2259 } 2260 } else { //no registry control, default is pll on 2261 INIT_INI_ARRAY( 2262 &ahp->ah_ini_pcie_serdes_low_power, 2263 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2264 ARRAY_LENGTH( 2265 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2266 2); 2267 } 2268 } else { 2269 if (ah->ah_config.ath_hal_pll_pwr_save & 2270 AR_PCIE_PLL_PWRSAVE_CONTROL) 2271 {//registry control 2272 if (ah->ah_config.ath_hal_pll_pwr_save & 2273 AR_PCIE_PLL_PWRSAVE_ON_D0) 2274 {//bit2, out of D3 2275 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2276 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2277 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2278 2); 2279 } else { 2280 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2281 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2282 ARRAY_LENGTH( 2283 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2284 2); 2285 } 2286 } else { //no registry control, default is pll on 2287 INIT_INI_ARRAY( 2288 &ahp->ah_ini_pcie_serdes_low_power, 2289 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2290 ARRAY_LENGTH( 2291 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2292 2); 2293 } 2294 } 2295 2296 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2297 2298#ifdef ATH_BUS_PM 2299 /*Use HAL to config PCI powersave by writing into the SerDes Registers */ 2300 ah->ah_config.ath_hal_pcie_ser_des_write = 1; 2301#endif 2302 2303#if 0 /* ATH_WOW */ 2304 /* SerDes values during WOW sleep */ 2305 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2306 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2307#endif 2308 2309 /* Fast clock modal settings */ 2310 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2311 ar9300Modes_fast_clock_osprey_2p2, 2312 ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3); 2313 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2314 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484, 2315 ARRAY_LENGTH( 2316 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2); 2317 2318 } 2319 2320 if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) 2321 { 2322#define AR_SOC_RST_OTP_INTF 0xB80600B4 2323#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2324 2325 ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF); 2326 if (AR_SREV_SCORPION(ah)) { 2327 ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12; 2328 } 2329 ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode); 2330#undef REG_READ 2331#undef AR_SOC_RST_OTP_INTF 2332 } else { 2333 ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP); 2334 } 2335 2336 2337 if (ahpriv->ah_ispcie) { 2338 ar9300_config_pci_power_save(ah, 0, 0); 2339 } else { 2340 ar9300_disable_pcie_phy(ah); 2341 } 2342 ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__); 2343 ecode = ar9300_hw_attach(ah); 2344 if (ecode != HAL_OK) { 2345 goto bad; 2346 } 2347 2348 /* set gain table pointers according to values read from the eeprom */ 2349 ar9300_tx_gain_table_apply(ah); 2350 ar9300_rx_gain_table_apply(ah); 2351 2352 /* 2353 ** 2354 ** Got everything we need now to setup the capabilities. 2355 */ 2356 2357 if (!ar9300_fill_capability_info(ah)) { 2358 HALDEBUG(ah, HAL_DEBUG_RESET, 2359 "%s:failed ar9300_fill_capability_info\n", __func__); 2360 ecode = HAL_EEREAD; 2361 goto bad; 2362 } 2363 ecode = ar9300_init_mac_addr(ah); 2364 if (ecode != HAL_OK) { 2365 HALDEBUG(ah, HAL_DEBUG_RESET, 2366 "%s: failed initializing mac address\n", __func__); 2367 goto bad; 2368 } 2369 2370 /* 2371 * Initialize receive buffer size to MAC default 2372 */ 2373 ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT; 2374 2375#if ATH_WOW 2376#if 0 2377 /* 2378 * Needs to be removed once we stop using XB92 XXX 2379 * FIXME: Check with latest boards too - SriniK 2380 */ 2381 ar9300_wow_set_gpio_reset_low(ah); 2382#endif 2383 2384 /* 2385 * Clear the Wow Status. 2386 */ 2387 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), 2388 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | 2389 AR_PMCTRL_WOW_PME_CLR); 2390 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, 2391 AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); 2392#endif 2393 2394 /* 2395 * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n 2396 * with aggregation enabled or disabled. 2397 */ 2398 ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 2399 2400 if (AR_SREV_HORNET(ah)) { 2401 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ; 2402 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2403 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2404 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2405 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2406 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2407 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2408 } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2409 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ; 2410 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2411 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ; 2412 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ; 2413 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2414 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ; 2415 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2416 } else { 2417 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ; 2418 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2419 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2420 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 2421 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ; 2422 } else { 2423 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2424 } 2425 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2426 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2427 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2428 } 2429 2430 2431 2432 2433 /* init BB Panic Watchdog timeout */ 2434 if (AR_SREV_HORNET(ah)) { 2435 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET; 2436 } else { 2437 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO; 2438 } 2439 2440 2441 /* 2442 * Determine whether tx IQ calibration HW should be enabled, 2443 * and whether tx IQ calibration should be performed during 2444 * AGC calibration, or separately. 2445 */ 2446 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2447 /* 2448 * Register not initialized yet. This flag will be re-initialized 2449 * after INI loading following each reset. 2450 */ 2451 ahp->tx_iq_cal_enable = 1; 2452 /* if tx IQ cal is enabled, do it together with AGC cal */ 2453 ahp->tx_iq_cal_during_agc_cal = 1; 2454 } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) { 2455 ahp->tx_iq_cal_enable = 1; 2456 ahp->tx_iq_cal_during_agc_cal = 1; 2457 } else { 2458 /* osprey, hornet, wasp */ 2459 ahp->tx_iq_cal_enable = 1; 2460 ahp->tx_iq_cal_during_agc_cal = 0; 2461 } 2462 return ah; 2463 2464bad: 2465 if (ahp) { 2466 ar9300_detach((struct ath_hal *) ahp); 2467 } 2468 if (status) { 2469 *status = ecode; 2470 } 2471 return AH_NULL; 2472} 2473 2474void 2475ar9300_detach(struct ath_hal *ah) 2476{ 2477 HALASSERT(ah != AH_NULL); 2478 HALASSERT(ah->ah_magic == AR9300_MAGIC); 2479 2480 /* Make sure that chip is awake before writing to it */ 2481 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 2482 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 2483 "%s: failed to wake up chip\n", 2484 __func__); 2485 } 2486 2487 ar9300_hw_detach(ah); 2488 ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 2489 2490// ath_hal_hdprintf_deregister(ah); 2491 2492 if (AH9300(ah)->ah_cal_mem) 2493 ath_hal_free(AH9300(ah)->ah_cal_mem); 2494 AH9300(ah)->ah_cal_mem = AH_NULL; 2495 2496 ath_hal_free(ah); 2497} 2498 2499struct ath_hal_9300 * 2500ar9300_new_state(u_int16_t devid, HAL_SOFTC sc, 2501 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, 2502 uint16_t *eepromdata, 2503 HAL_OPS_CONFIG *ah_config, 2504 HAL_STATUS *status) 2505{ 2506 static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] = 2507 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2508 struct ath_hal_9300 *ahp; 2509 struct ath_hal *ah; 2510 2511 /* NB: memory is returned zero'd */ 2512 ahp = ath_hal_malloc(sizeof(struct ath_hal_9300)); 2513 if (ahp == AH_NULL) { 2514 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2515 "%s: cannot allocate memory for state block\n", 2516 __func__); 2517 *status = HAL_ENOMEM; 2518 return AH_NULL; 2519 } 2520 2521 ah = &ahp->ah_priv.h; 2522 /* set initial values */ 2523 2524 /* stub everything first */ 2525 ar9300_set_stub_functions(ah); 2526 2527 /* setup the FreeBSD HAL methods */ 2528 ar9300_attach_freebsd_ops(ah); 2529 2530 /* These are private to this particular file, so .. */ 2531 ah->ah_disablePCIE = ar9300_disable_pcie_phy; 2532 AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust; 2533 AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits; 2534 2535#if 0 2536 /* Attach Osprey structure as default hal structure */ 2537 OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv)); 2538#endif 2539 2540#if 0 2541 AH_PRIVATE(ah)->amem_handle = amem_handle; 2542 AH_PRIVATE(ah)->ah_osdev = osdev; 2543#endif 2544 ah->ah_sc = sc; 2545 ah->ah_st = st; 2546 ah->ah_sh = sh; 2547 ah->ah_magic = AR9300_MAGIC; 2548 AH_PRIVATE(ah)->ah_devid = devid; 2549 2550 AH_PRIVATE(ah)->ah_flags = 0; 2551 2552 /* 2553 ** Initialize factory defaults in the private space 2554 */ 2555// ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm); 2556 ar9300_config_defaults_freebsd(ah, ah_config); 2557 2558 /* XXX FreeBSD: cal is always in EEPROM */ 2559#if 0 2560 if (!hal_conf_parm->calInFlash) { 2561 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2562 } 2563#endif 2564 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2565 2566#if 0 2567 if (ar9300_eep_data_in_flash(ah)) { 2568 ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read; 2569 ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL; 2570 } else { 2571 ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word; 2572 } 2573#endif 2574 2575 /* XXX FreeBSD - for now, just supports EEPROM reading */ 2576 ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word; 2577 2578 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 2579 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 2580 2581 ahp->ah_atim_window = 0; /* [0..1000] */ 2582 2583 ahp->ah_diversity_control = 2584 ah->ah_config.ath_hal_diversity_control; 2585 ahp->ah_antenna_switch_swap = 2586 ah->ah_config.ath_hal_antenna_switch_swap; 2587 2588 /* 2589 * Enable MIC handling. 2590 */ 2591 ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 2592 ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */ 2593 ahp->ah_slot_time = (u_int) -1; 2594 ahp->ah_ack_timeout = (u_int) -1; 2595 OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN); 2596 2597 /* 2598 * 11g-specific stuff 2599 */ 2600 ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */ 2601 2602 /* SM power mode: Attach time, disable any setting */ 2603 ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT; 2604 2605 return ahp; 2606} 2607 2608HAL_BOOL 2609ar9300_chip_test(struct ath_hal *ah) 2610{ 2611 /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/ 2612 u_int32_t reg_addr[2] = { AR_STA_ID0 }; 2613 u_int32_t reg_hold[2]; 2614 u_int32_t pattern_data[4] = 2615 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 2616 int i, j; 2617 2618 /* Test PHY & MAC registers */ 2619 for (i = 0; i < 1; i++) { 2620 u_int32_t addr = reg_addr[i]; 2621 u_int32_t wr_data, rd_data; 2622 2623 reg_hold[i] = OS_REG_READ(ah, addr); 2624 for (j = 0; j < 0x100; j++) { 2625 wr_data = (j << 16) | j; 2626 OS_REG_WRITE(ah, addr, wr_data); 2627 rd_data = OS_REG_READ(ah, addr); 2628 if (rd_data != wr_data) { 2629 HALDEBUG(ah, HAL_DEBUG_REGIO, 2630 "%s: address test failed addr: " 2631 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2632 __func__, addr, wr_data, rd_data); 2633 return AH_FALSE; 2634 } 2635 } 2636 for (j = 0; j < 4; j++) { 2637 wr_data = pattern_data[j]; 2638 OS_REG_WRITE(ah, addr, wr_data); 2639 rd_data = OS_REG_READ(ah, addr); 2640 if (wr_data != rd_data) { 2641 HALDEBUG(ah, HAL_DEBUG_REGIO, 2642 "%s: address test failed addr: " 2643 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2644 __func__, addr, wr_data, rd_data); 2645 return AH_FALSE; 2646 } 2647 } 2648 OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]); 2649 } 2650 OS_DELAY(100); 2651 return AH_TRUE; 2652} 2653 2654/* 2655 * Store the channel edges for the requested operational mode 2656 */ 2657HAL_BOOL 2658ar9300_get_channel_edges(struct ath_hal *ah, 2659 u_int16_t flags, u_int16_t *low, u_int16_t *high) 2660{ 2661 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2662 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2663 2664 if (flags & IEEE80211_CHAN_5GHZ) { 2665 *low = p_cap->halLow5GhzChan; 2666 *high = p_cap->halHigh5GhzChan; 2667 return AH_TRUE; 2668 } 2669 if ((flags & IEEE80211_CHAN_2GHZ)) { 2670 *low = p_cap->halLow2GhzChan; 2671 *high = p_cap->halHigh2GhzChan; 2672 2673 return AH_TRUE; 2674 } 2675 return AH_FALSE; 2676} 2677 2678HAL_BOOL 2679ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn) 2680{ 2681 AH_PRIVATE(ah)->ah_currentRD = regdmn; 2682 return AH_TRUE; 2683} 2684 2685/* 2686 * Fill all software cached or static hardware state information. 2687 * Return failure if capabilities are to come from EEPROM and 2688 * cannot be read. 2689 */ 2690HAL_BOOL 2691ar9300_fill_capability_info(struct ath_hal *ah) 2692{ 2693#define AR_KEYTABLE_SIZE 128 2694 struct ath_hal_9300 *ahp = AH9300(ah); 2695 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2696 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2697 u_int16_t cap_field = 0, eeval; 2698 2699 ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE); 2700 eeval = ar9300_eeprom_get(ahp, EEP_REG_0); 2701 2702 /* XXX record serial number */ 2703 AH_PRIVATE(ah)->ah_currentRD = eeval; 2704 2705 /* Always enable fast clock; leave it up to EEPROM and channel */ 2706 p_cap->halSupportsFastClock5GHz = AH_TRUE; 2707 2708 p_cap->halIntrMitigation = AH_TRUE; 2709 eeval = ar9300_eeprom_get(ahp, EEP_REG_1); 2710 AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT; 2711 2712 /* Read the capability EEPROM location */ 2713 cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP); 2714 2715 /* Construct wireless mode from EEPROM */ 2716 p_cap->halWirelessModes = 0; 2717 eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE); 2718 2719 /* 2720 * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1, 2721 * or we won't have 11n support. 2722 */ 2723 ah->ah_config.ath_hal_ht_enable = 1; 2724 2725 if (eeval & AR9300_OPFLAGS_11A) { 2726 p_cap->halWirelessModes |= HAL_MODE_11A | 2727 ((!ah->ah_config.ath_hal_ht_enable || 2728 (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 : 2729 (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 : 2730 (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)))); 2731 } 2732 if (eeval & AR9300_OPFLAGS_11G) { 2733 p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G | 2734 ((!ah->ah_config.ath_hal_ht_enable || 2735 (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 : 2736 (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 : 2737 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS)))); 2738 } 2739 2740 /* Get chainamsks from eeprom */ 2741 p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK); 2742 p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK); 2743 2744 2745 2746#define owl_get_ntxchains(_txchainmask) \ 2747 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 2748 2749 /* FreeBSD: Update number of TX/RX streams */ 2750 p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask); 2751 p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask); 2752 2753 2754 /* 2755 * This being a newer chip supports TKIP non-splitmic mode. 2756 * 2757 */ 2758 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2759 p_cap->halTkipMicTxRxKeySupport = AH_TRUE; 2760 2761 p_cap->halLow2GhzChan = 2312; 2762 p_cap->halHigh2GhzChan = 2732; 2763 2764 p_cap->halLow5GhzChan = 4920; 2765 p_cap->halHigh5GhzChan = 6100; 2766 2767 p_cap->halCipherCkipSupport = AH_FALSE; 2768 p_cap->halCipherTkipSupport = AH_TRUE; 2769 p_cap->halCipherAesCcmSupport = AH_TRUE; 2770 2771 p_cap->halMicCkipSupport = AH_FALSE; 2772 p_cap->halMicTkipSupport = AH_TRUE; 2773 p_cap->halMicAesCcmSupport = AH_TRUE; 2774 2775 p_cap->halChanSpreadSupport = AH_TRUE; 2776 p_cap->halSleepAfterBeaconBroken = AH_TRUE; 2777 2778 p_cap->halBurstSupport = AH_TRUE; 2779 p_cap->halChapTuningSupport = AH_TRUE; 2780 p_cap->halTurboPrimeSupport = AH_TRUE; 2781 p_cap->halFastFramesSupport = AH_TRUE; 2782 2783 p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G; 2784 2785// p_cap->hal_xr_support = AH_FALSE; 2786 2787 p_cap->halHTSupport = 2788 ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE; 2789 2790 p_cap->halGTTSupport = AH_TRUE; 2791 p_cap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 2792 p_cap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 2793 p_cap->halHTSGI20Support = AH_TRUE; 2794 p_cap->halVEOLSupport = AH_TRUE; 2795 p_cap->halBssIdMaskSupport = AH_TRUE; 2796 /* Bug 26802, fixed in later revs? */ 2797 p_cap->halMcastKeySrchSupport = AH_TRUE; 2798 p_cap->halTsfAddSupport = AH_TRUE; 2799 2800 if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) { 2801 p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU); 2802 } else { 2803 p_cap->halTotalQueues = HAL_NUM_TX_QUEUES; 2804 } 2805 2806 if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) { 2807 p_cap->halKeyCacheSize = 2808 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES); 2809 } else { 2810 p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE; 2811 } 2812 p_cap->halFastCCSupport = AH_TRUE; 2813// p_cap->hal_num_mr_retries = 4; 2814// ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD; 2815 2816 p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM; 2817 2818#if 0 2819 /* XXX Verify support in Osprey */ 2820 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2821 p_cap->halWowSupport = AH_TRUE; 2822 p_cap->hal_wow_match_pattern_exact = AH_TRUE; 2823 if (AR_SREV_MERLIN(ah)) { 2824 p_cap->hal_wow_pattern_match_dword = AH_TRUE; 2825 } 2826 } else { 2827 p_cap->halWowSupport = AH_FALSE; 2828 p_cap->hal_wow_match_pattern_exact = AH_FALSE; 2829 } 2830#endif 2831 p_cap->halWowSupport = AH_TRUE; 2832 p_cap->halWowMatchPatternExact = AH_TRUE; 2833 if (AR_SREV_POSEIDON(ah)) { 2834 p_cap->halWowMatchPatternExact = AH_TRUE; 2835 } 2836 2837 p_cap->halCSTSupport = AH_TRUE; 2838 2839 p_cap->halRifsRxSupport = AH_TRUE; 2840 p_cap->halRifsTxSupport = AH_TRUE; 2841 2842#define IEEE80211_AMPDU_LIMIT_MAX (65536) 2843 p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX; 2844#undef IEEE80211_AMPDU_LIMIT_MAX 2845 2846 p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support; 2847 2848 p_cap->halForcePpmSupport = AH_TRUE; 2849 p_cap->halHwBeaconProcSupport = AH_TRUE; 2850 2851 /* ar9300 - has the HW UAPSD trigger support, 2852 * but it has the following limitations 2853 * The power state change from the following 2854 * frames are not put in High priority queue. 2855 * i) Mgmt frames 2856 * ii) NoN QoS frames 2857 * iii) QoS frames form the access categories for which 2858 * UAPSD is not enabled. 2859 * so we can not enable this feature currently. 2860 * could be enabled, if these limitations are fixed 2861 * in later versions of ar9300 chips 2862 */ 2863 p_cap->halHasUapsdSupport = AH_FALSE; 2864 2865 /* Number of buffers that can be help in a single TxD */ 2866 p_cap->halNumTxMaps = 4; 2867 2868 p_cap->halTxDescLen = sizeof(struct ar9300_txc); 2869 p_cap->halTxStatusLen = sizeof(struct ar9300_txs); 2870 p_cap->halRxStatusLen = sizeof(struct ar9300_rxs); 2871 2872 p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH; 2873 p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH; 2874 2875 /* Enable extension channel DFS support */ 2876 p_cap->halUseCombinedRadarRssi = AH_TRUE; 2877 p_cap->halExtChanDfsSupport = AH_TRUE; 2878#if ATH_SUPPORT_SPECTRAL 2879 p_cap->halSpectralScanSupport = AH_TRUE; 2880#endif 2881 2882 ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT); 2883 if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) { 2884 ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 2885 ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY); 2886 2887 ath_hal_enable_rfkill(ah, AH_TRUE); 2888 p_cap->halRfSilentSupport = AH_TRUE; 2889 } 2890 2891 /* XXX */ 2892 p_cap->halWpsPushButtonSupport = AH_FALSE; 2893 2894#ifdef ATH_BT_COEX 2895 p_cap->halBtCoexSupport = AH_TRUE; 2896 p_cap->halBtCoexApsmWar = AH_FALSE; 2897#endif 2898 2899 p_cap->halGenTimerSupport = AH_TRUE; 2900 ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1); 2901 ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1; 2902 /* 2903 * According to Kyungwan, generic timer 0 and 8 are special 2904 * timers. Remove timer 8 from the available gen timer list. 2905 * Jupiter testing shows timer won't trigger with timer 8. 2906 */ 2907 ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED); 2908 2909 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2910#if ATH_SUPPORT_MCI 2911 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI) 2912 { 2913 p_cap->halMciSupport = AH_FALSE; 2914 } 2915 else 2916#endif 2917 { 2918 p_cap->halMciSupport = (ahp->ah_enterprise_mode & 2919 AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE; 2920 } 2921 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2922 "%s: (MCI) MCI support = %d\n", 2923 __func__, p_cap->halMciSupport); 2924 } 2925 else { 2926 p_cap->halMciSupport = AH_FALSE; 2927 } 2928 2929 /* XXX TODO: jupiter 2.1? */ 2930 if (AR_SREV_JUPITER_20(ah)) { 2931 p_cap->halRadioRetentionSupport = AH_TRUE; 2932 } else { 2933 p_cap->halRadioRetentionSupport = AH_FALSE; 2934 } 2935 2936 p_cap->halAutoSleepSupport = AH_TRUE; 2937 2938 p_cap->halMbssidAggrSupport = AH_TRUE; 2939// p_cap->hal_proxy_sta_support = AH_TRUE; 2940 2941 /* XXX Mark it true after it is verfied as fixed */ 2942 p_cap->hal4kbSplitTransSupport = AH_FALSE; 2943 2944 /* Read regulatory domain flag */ 2945 if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2946 /* 2947 * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND. 2948 */ 2949 p_cap->halRegCap = 2950 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2951 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2952 AR_EEPROM_EEREGCAP_EN_KK_U2 | 2953 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2954 } else { 2955 p_cap->halRegCap = 2956 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2957 } 2958 2959 /* For AR9300 and above, midband channels are always supported */ 2960 p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2961 2962 p_cap->halNumAntCfg5GHz = 2963 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); 2964 p_cap->halNumAntCfg2GHz = 2965 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); 2966 2967 /* STBC supported */ 2968 p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */ 2969 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2970 p_cap->halTxStbcSupport = 0; 2971 } else { 2972 p_cap->halTxStbcSupport = 1; 2973 } 2974 2975 p_cap->halEnhancedDmaSupport = AH_TRUE; 2976 p_cap->halEnhancedDfsSupport = AH_TRUE; 2977 2978 /* 2979 * EV61133 (missing interrupts due to AR_ISR_RAC). 2980 * Fixed in Osprey 2.0. 2981 */ 2982 p_cap->halIsrRacSupport = AH_TRUE; 2983 2984 /* XXX FreeBSD won't support TKIP and WEP aggregation */ 2985#if 0 2986 p_cap->hal_wep_tkip_aggr_support = AH_TRUE; 2987 p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */ 2988 p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */ 2989 p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */ 2990#endif 2991 2992 /* 2993 * XXX FreeBSD won't need these; but eventually add them 2994 * and add the WARs - AGGR extra delim WAR is useful to know 2995 * about. 2996 */ 2997#if 0 2998 p_cap->hal_cfend_fix_support = AH_FALSE; 2999 p_cap->hal_aggr_extra_delim_war = AH_FALSE; 3000#endif 3001 p_cap->halHasLongRxDescTsf = AH_TRUE; 3002// p_cap->hal_rx_desc_timestamp_bits = 32; 3003 p_cap->halRxTxAbortSupport = AH_TRUE; 3004 p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL; 3005 p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC; 3006 3007 /* Transmit Beamforming supported, fill capabilities */ 3008 p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED); 3009 p_cap->halChanHalfRate = 3010 !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE); 3011 p_cap->halChanQuarterRate = 3012 !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE); 3013 3014 if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 3015 /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */ 3016 p_cap->hal49GhzSupport = 1; 3017 } else { 3018 p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE); 3019 } 3020 3021 if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) { 3022 /* LDPC supported */ 3023 /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */ 3024 p_cap->halLDPCSupport = AH_FALSE; 3025 /* PCI_E LCR offset */ 3026 if (AR_SREV_POSEIDON(ah)) { 3027 p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/ 3028 } 3029 /*WAR method for APSM L0s with Poseidon 1.0*/ 3030 if (AR_SREV_POSEIDON_10(ah)) { 3031 p_cap->hal_pcie_lcr_extsync_en = AH_TRUE; 3032 } 3033 } else { 3034 p_cap->halLDPCSupport = AH_TRUE; 3035 } 3036 3037 /* XXX is this a flag, or a chainmask number? */ 3038 p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE); 3039#if ATH_ANT_DIV_COMB 3040 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 3041 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) { 3042 u_int8_t ant_div_control1 = 3043 ar9300_eeprom_get(ahp, EEP_ANTDIV_control); 3044 /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1, 3045 * we enable the diversity-combining algorithm. 3046 */ 3047 if ((ant_div_control1 >> 0x6) == 0x3) { 3048 p_cap->halAntDivCombSupport = AH_TRUE; 3049 } 3050 p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport; 3051 } 3052 } 3053#endif /* ATH_ANT_DIV_COMB */ 3054 3055 /* 3056 * FreeBSD: enable LNA mixing if the chip is Hornet or Poseidon. 3057 */ 3058 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3059 p_cap->halRxUsingLnaMixing = AH_TRUE; 3060 } 3061 3062 /* 3063 * AR5416 and later NICs support MYBEACON filtering. 3064 */ 3065 p_cap->halRxDoMyBeacon = AH_TRUE; 3066 3067#if ATH_WOW_OFFLOAD 3068 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 3069 p_cap->hal_wow_gtk_offload_support = AH_TRUE; 3070 p_cap->hal_wow_arp_offload_support = AH_TRUE; 3071 p_cap->hal_wow_ns_offload_support = AH_TRUE; 3072 p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE; 3073 p_cap->hal_wow_acer_magic_support = AH_TRUE; 3074 p_cap->hal_wow_acer_swka_support = AH_TRUE; 3075 } else { 3076 p_cap->hal_wow_gtk_offload_support = AH_FALSE; 3077 p_cap->hal_wow_arp_offload_support = AH_FALSE; 3078 p_cap->hal_wow_ns_offload_support = AH_FALSE; 3079 p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE; 3080 p_cap->hal_wow_acer_magic_support = AH_FALSE; 3081 p_cap->hal_wow_acer_swka_support = AH_FALSE; 3082 } 3083#endif /* ATH_WOW_OFFLOAD */ 3084 3085 3086 return AH_TRUE; 3087#undef AR_KEYTABLE_SIZE 3088} 3089 3090#if 0 3091static HAL_BOOL 3092ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, 3093 u_int32_t nchans) 3094{ 3095 struct ath_hal_9300 *ahp = AH9300(ah); 3096 3097 return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans); 3098} 3099#endif 3100/* XXX FreeBSD */ 3101 3102static HAL_BOOL 3103ar9300_get_chip_power_limits(struct ath_hal *ah, 3104 struct ieee80211_channel *chan) 3105{ 3106 3107 chan->ic_maxpower = AR9300_MAX_RATE_POWER; 3108 chan->ic_minpower = 0; 3109 3110 return AH_TRUE; 3111} 3112 3113/* 3114 * Disable PLL when in L0s as well as receiver clock when in L1. 3115 * This power saving option must be enabled through the Serdes. 3116 * 3117 * Programming the Serdes must go through the same 288 bit serial shift 3118 * register as the other analog registers. Hence the 9 writes. 3119 * 3120 * XXX Clean up the magic numbers. 3121 */ 3122void 3123ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off) 3124{ 3125 struct ath_hal_9300 *ahp = AH9300(ah); 3126 int i; 3127 3128 if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) { 3129 return; 3130 } 3131 3132 /* 3133 * Increase L1 Entry Latency. Some WB222 boards don't have 3134 * this change in eeprom/OTP. 3135 */ 3136 if (AR_SREV_JUPITER(ah)) { 3137 u_int32_t val = ah->ah_config.ath_hal_war70c; 3138 if ((val & 0xff000000) == 0x17000000) { 3139 val &= 0x00ffffff; 3140 val |= 0x27000000; 3141 OS_REG_WRITE(ah, 0x570c, val); 3142 } 3143 } 3144 3145 /* Do not touch SERDES registers */ 3146 if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) { 3147 return; 3148 } 3149 3150 /* Nothing to do on restore for 11N */ 3151 if (!restore) { 3152 /* set bit 19 to allow forcing of pcie core into L1 state */ 3153 OS_REG_SET_BIT(ah, 3154 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); 3155 3156 /* 3157 * Set PCIE workaround config only if requested, else use the reset 3158 * value of this register. 3159 */ 3160 if (ah->ah_config.ath_hal_pcie_waen) { 3161 OS_REG_WRITE(ah, 3162 AR_HOSTIF_REG(ah, AR_WA), 3163 ah->ah_config.ath_hal_pcie_waen); 3164 } else { 3165 /* Set Bits 17 and 14 in the AR_WA register. */ 3166 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 3167 } 3168 } 3169 3170 /* Configure PCIE after Ini init. SERDES values now come from ini file */ 3171 if (ah->ah_config.ath_hal_pcie_ser_des_write) { 3172 if (power_off) { 3173 for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) { 3174 OS_REG_WRITE(ah, 3175 INI_RA(&ahp->ah_ini_pcie_serdes, i, 0), 3176 INI_RA(&ahp->ah_ini_pcie_serdes, i, 1)); 3177 } 3178 } else { 3179 for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) { 3180 OS_REG_WRITE(ah, 3181 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0), 3182 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1)); 3183 } 3184 } 3185 } 3186 3187} 3188 3189/* 3190 * Recipe from charles to turn off PCIe PHY in PCI mode for power savings 3191 */ 3192void 3193ar9300_disable_pcie_phy(struct ath_hal *ah) 3194{ 3195 /* Osprey does not support PCI mode */ 3196} 3197 3198static inline HAL_STATUS 3199ar9300_init_mac_addr(struct ath_hal *ah) 3200{ 3201 u_int32_t sum; 3202 int i; 3203 u_int16_t eeval; 3204 struct ath_hal_9300 *ahp = AH9300(ah); 3205 u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 3206 3207 sum = 0; 3208 for (i = 0; i < 3; i++) { 3209 eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]); 3210 sum += eeval; 3211 ahp->ah_macaddr[2*i] = eeval >> 8; 3212 ahp->ah_macaddr[2*i + 1] = eeval & 0xff; 3213 } 3214 if (sum == 0 || sum == 0xffff*3) { 3215 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n", 3216 __func__, ath_hal_ether_sprintf(ahp->ah_macaddr)); 3217 return HAL_EEBADMAC; 3218 } 3219 3220 return HAL_OK; 3221} 3222 3223/* 3224 * Code for the "real" chip i.e. non-emulation. Review and revisit 3225 * when actual hardware is at hand. 3226 */ 3227static inline HAL_STATUS 3228ar9300_hw_attach(struct ath_hal *ah) 3229{ 3230 HAL_STATUS ecode; 3231 3232 if (!ar9300_chip_test(ah)) { 3233 HALDEBUG(ah, HAL_DEBUG_REGIO, 3234 "%s: hardware self-test failed\n", __func__); 3235 return HAL_ESELFTEST; 3236 } 3237 3238 ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__); 3239 ecode = ar9300_eeprom_attach(ah); 3240 ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode); 3241 if (ecode != HAL_OK) { 3242 return ecode; 3243 } 3244 if (!ar9300_rf_attach(ah, &ecode)) { 3245 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n", 3246 __func__, ecode); 3247 } 3248 3249 if (ecode != HAL_OK) { 3250 return ecode; 3251 } 3252 ar9300_ani_attach(ah); 3253 3254 return HAL_OK; 3255} 3256 3257static inline void 3258ar9300_hw_detach(struct ath_hal *ah) 3259{ 3260 /* XXX EEPROM allocated state */ 3261 ar9300_ani_detach(ah); 3262} 3263 3264static int16_t 3265ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 3266{ 3267 return 0; 3268} 3269 3270void 3271ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable) 3272{ 3273 struct ath_hal_9300 *ahp = AH9300(ah); 3274 u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0], 3275 m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1], 3276 m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2], 3277 m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3], 3278 m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4], 3279 m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5]; 3280 3281 if (ahp->ah_immunity_on == enable) { 3282 return; 3283 } 3284 3285 ahp->ah_immunity_on = enable; 3286 3287 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3288 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); 3289 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3290 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); 3291 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3292 AR_PHY_SFCORR_M1_THRESH, m1_thresh); 3293 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3294 AR_PHY_SFCORR_M2_THRESH, m2_thresh); 3295 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3296 AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr); 3297 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3298 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); 3299 3300 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3301 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low); 3302 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3303 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low); 3304 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3305 AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh); 3306 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3307 AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh); 3308 3309 if (!enable) { 3310 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 3311 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3312 } else { 3313 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 3314 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3315 } 3316} 3317 3318/* XXX FreeBSD: I'm not sure how to implement this.. */ 3319#if 0 3320int 3321ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 3322 HAL_CAL_QUERY query) 3323{ 3324#define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \ 3325 ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0) 3326#define AR9300_IS_RX_IQCAL_DISABLED(_ah) \ 3327 (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \ 3328 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE)) 3329/* Avoid comilation warnings. Variables are not used when EMULATION. */ 3330 struct ath_hal_9300 *ahp = AH9300(ah); 3331 u_int8_t rxchainmask = ahp->ah_rx_chainmask, i; 3332 int rx_iqcal_invalid = 0, num_chains = 0; 3333 static const u_int32_t offset_array[3] = { 3334 AR_PHY_RX_IQCAL_CORR_B0, 3335 AR_PHY_RX_IQCAL_CORR_B1, 3336 AR_PHY_RX_IQCAL_CORR_B2}; 3337 3338 *timerp = ar9300_cals; 3339 3340 switch (query) { 3341 case HAL_QUERY_CALS: 3342 return AR9300_NUM_CAL_TYPES; 3343 case HAL_QUERY_RERUN_CALS: 3344 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 3345 if (rxchainmask & (1 << i)) { 3346 num_chains++; 3347 } 3348 } 3349 for (i = 0; i < num_chains; i++) { 3350 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 3351 HALASSERT(num_chains == 0x1); 3352 } 3353 if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) { 3354 rx_iqcal_invalid = 1; 3355 } 3356 } 3357 if (AR9300_IS_RX_IQCAL_DISABLED(ah)) { 3358 rx_iqcal_invalid = 1; 3359 } 3360 3361 return rx_iqcal_invalid; 3362 default: 3363 HALASSERT(0); 3364 } 3365 return 0; 3366} 3367#endif 3368 3369#if ATH_TRAFFIC_FAST_RECOVER 3370#define PLL3 0x16188 3371#define PLL3_DO_MEAS_MASK 0x40000000 3372#define PLL4 0x1618c 3373#define PLL4_MEAS_DONE 0x8 3374#define SQSUM_DVC_MASK 0x007ffff8 3375unsigned long 3376ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah) 3377{ 3378 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 3379 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); 3380 OS_DELAY(100); 3381 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); 3382 3383 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 3384 OS_DELAY(100); 3385 } 3386 3387 return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); 3388 } else { 3389 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 3390 "%s: unable to get pll3_sqsum_dvc\n", 3391 __func__); 3392 return 0; 3393 } 3394} 3395#endif 3396 3397 3398#define RX_GAIN_TABLE_LENGTH 128 3399// this will be called if rfGainCAP is enabled and rfGainCAP setting is changed, 3400// or rxGainTable setting is changed 3401HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz) 3402{ 3403 int i, done = 0, i_rx_gain = 32; 3404 u_int32_t rf_gain_cap; 3405 u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped; 3406 static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2]; 3407 ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; 3408 struct ath_hal_9300 *ahp = AH9300(ah); 3409 3410 if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) ) 3411 return AH_FALSE; 3412 3413 if (is_2GHz) 3414 { 3415 rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap; 3416 } 3417 else 3418 { 3419 rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap; 3420 } 3421 3422 if (rf_gain_cap == 0) 3423 return AH_FALSE; 3424 3425 for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++) 3426 { 3427 if (AR_SREV_AR9580(ah)) 3428 { 3429 // BB_rx_ocgain2 3430 i_rx_gain = 128 + 32; 3431 switch (ar9300_rx_gain_index_get(ah)) 3432 { 3433 case 0: 3434 rx_gain_table[i][0] = 3435 ar9300_common_rx_gain_table_ar9580_1p0[i][0]; 3436 rx_gain_table[i][1] = 3437 ar9300_common_rx_gain_table_ar9580_1p0[i][1]; 3438 break; 3439 case 1: 3440 rx_gain_table[i][0] = 3441 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0]; 3442 rx_gain_table[i][1] = 3443 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1]; 3444 break; 3445 } 3446 } 3447 else if (AR_SREV_OSPREY_22(ah)) 3448 { 3449 i_rx_gain = 128 + 32; 3450 switch (ar9300_rx_gain_index_get(ah)) 3451 { 3452 case 0: 3453 rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0]; 3454 rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1]; 3455 break; 3456 case 1: 3457 rx_gain_table[i][0] = 3458 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0]; 3459 rx_gain_table[i][1] = 3460 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1]; 3461 break; 3462 } 3463 } 3464 else 3465 { 3466 return AH_FALSE; 3467 } 3468 } 3469 3470 while (1) 3471 { 3472 rx_gain_value = rx_gain_table[i_rx_gain][1]; 3473 rx_gain_value_caped = rx_gain_value; 3474 a_Byte = rx_gain_value & (0x000000FF); 3475 if (a_Byte>rf_gain_cap) 3476 { 3477 rx_gain_value_caped = (rx_gain_value_caped & 3478 (0xFFFFFF00)) + rf_gain_cap; 3479 } 3480 a_Byte = rx_gain_value & (0x0000FF00); 3481 if ( a_Byte > ( rf_gain_cap << 8 ) ) 3482 { 3483 rx_gain_value_caped = (rx_gain_value_caped & 3484 (0xFFFF00FF)) + (rf_gain_cap<<8); 3485 } 3486 a_Byte = rx_gain_value & (0x00FF0000); 3487 if ( a_Byte > ( rf_gain_cap << 16 ) ) 3488 { 3489 rx_gain_value_caped = (rx_gain_value_caped & 3490 (0xFF00FFFF)) + (rf_gain_cap<<16); 3491 } 3492 a_Byte = rx_gain_value & (0xFF000000); 3493 if ( a_Byte > ( rf_gain_cap << 24 ) ) 3494 { 3495 rx_gain_value_caped = (rx_gain_value_caped & 3496 (0x00FFFFFF)) + (rf_gain_cap<<24); 3497 } 3498 else 3499 { 3500 done = 1; 3501 } 3502 HALDEBUG(ah, HAL_DEBUG_RESET, 3503 "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n", 3504 __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped); 3505 if (rx_gain_value_caped != rx_gain_value) 3506 { 3507 rx_gain_table[i_rx_gain][1] = rx_gain_value_caped; 3508 } 3509 if (done == 1) 3510 break; 3511 i_rx_gain ++; 3512 } 3513 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2); 3514 return AH_TRUE; 3515} 3516 3517 3518void ar9300_rx_gain_table_apply(struct ath_hal *ah) 3519{ 3520 struct ath_hal_9300 *ahp = AH9300(ah); 3521//struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 3522 u_int32_t xlan_gpio_cfg; 3523 u_int8_t i; 3524 3525 if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah)) 3526 { 3527 // this will be called if rxGainTable setting is changed 3528 if (ar9300_rf_gain_cap_apply(ah, 1)) 3529 return; 3530 } 3531 3532 switch (ar9300_rx_gain_index_get(ah)) 3533 { 3534 case 2: 3535 if (AR_SREV_JUPITER_10(ah)) { 3536 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3537 ar9300_common_mixed_rx_gain_table_jupiter_1p0, 3538 ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2); 3539 break; 3540 } 3541 else if (AR_SREV_JUPITER_20(ah)) { 3542 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3543 ar9300Common_mixed_rx_gain_table_jupiter_2p0, 3544 ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2); 3545 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_core, 3546 ar9462_2p0_baseband_core_mix_rxgain, 3547 ARRAY_LENGTH(ar9462_2p0_baseband_core_mix_rxgain), 2); 3548 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_postamble, 3549 ar9462_2p0_baseband_postamble_mix_rxgain, 3550 ARRAY_LENGTH(ar9462_2p0_baseband_postamble_mix_rxgain), 2); 3551 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna, 3552 ar9462_2p0_baseband_postamble_5g_xlna, 3553 ARRAY_LENGTH(ar9462_2p0_baseband_postamble_5g_xlna), 2); 3554 break; 3555 } 3556 else if (AR_SREV_JUPITER_21(ah)) { 3557 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3558 ar9462_2p1_common_mixed_rx_gain, 3559 ARRAY_LENGTH(ar9462_2p1_common_mixed_rx_gain), 2); 3560 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_core, 3561 ar9462_2p1_baseband_core_mix_rxgain, 3562 ARRAY_LENGTH(ar9462_2p1_baseband_core_mix_rxgain), 2); 3563 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bb_postamble, 3564 ar9462_2p1_baseband_postamble_mix_rxgain, 3565 ARRAY_LENGTH(ar9462_2p1_baseband_postamble_mix_rxgain), 2); 3566 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna, 3567 ar9462_2p1_baseband_postamble_5g_xlna, 3568 ARRAY_LENGTH(ar9462_2p1_baseband_postamble_5g_xlna), 2); 3569 3570 break; 3571 } 3572 case 3: 3573 if (AR_SREV_JUPITER_21(ah)) { 3574 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3575 ar9462_2p1_common_5g_xlna_only_rxgain, 3576 ARRAY_LENGTH(ar9462_2p1_common_5g_xlna_only_rxgain), 2); 3577 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna, 3578 ar9462_2p1_baseband_postamble_5g_xlna, 3579 ARRAY_LENGTH(ar9462_2p1_baseband_postamble_5g_xlna), 2); 3580 } else if (AR_SREV_JUPITER_20(ah)) { 3581 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3582 ar9462_2p0_common_5g_xlna_only_rxgain, 3583 ARRAY_LENGTH(ar9462_2p0_common_5g_xlna_only_rxgain), 2); 3584 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_xlna, 3585 ar9462_2p0_baseband_postamble_5g_xlna, 3586 ARRAY_LENGTH(ar9462_2p0_baseband_postamble_5g_xlna), 2); 3587 } 3588 break; 3589 case 0: 3590 default: 3591 if (AR_SREV_HORNET_12(ah)) { 3592 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3593 ar9331_common_rx_gain_hornet1_2, 3594 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 3595 } else if (AR_SREV_HORNET_11(ah)) { 3596 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3597 ar9331_common_rx_gain_hornet1_1, 3598 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 3599 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3600 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3601 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3602 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3603 /* XXX FreeBSD: this needs to be revisited!! */ 3604 xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio; 3605 if (xlan_gpio_cfg) { 3606 for (i = 0; i < 32; i++) { 3607 if (xlan_gpio_cfg & (1 << i)) { 3608 /* 3609 * XXX FreeBSD: definitely make sure this 3610 * results in the correct value being written 3611 * to the hardware, or weird crap is very likely 3612 * to occur! 3613 */ 3614 ath_hal_gpioCfgOutput(ah, i, 3615 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED); 3616 } 3617 } 3618 } 3619 3620 } else if (AR_SREV_POSEIDON(ah)) { 3621 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3622 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3623 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3624 } else if (AR_SREV_JUPITER_10(ah)) { 3625 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3626 ar9300_common_rx_gain_table_jupiter_1p0, 3627 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 3628 } else if (AR_SREV_JUPITER_20(ah)) { 3629 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3630 ar9300Common_rx_gain_table_jupiter_2p0, 3631 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 3632 } else if (AR_SREV_JUPITER_21(ah)) { 3633 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3634 ar9462_2p1_common_rx_gain, 3635 ARRAY_LENGTH(ar9462_2p1_common_rx_gain), 2); 3636 } else if (AR_SREV_AR9580(ah)) { 3637 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3638 ar9300_common_rx_gain_table_ar9580_1p0, 3639 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 3640 } else if (AR_SREV_WASP(ah)) { 3641 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3642 ar9340Common_rx_gain_table_wasp_1p0, 3643 ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2); 3644 } else if (AR_SREV_SCORPION(ah)) { 3645 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3646 ar955xCommon_rx_gain_table_scorpion_1p0, 3647 ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2); 3648 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3649 ar955xCommon_rx_gain_bounds_scorpion_1p0, 3650 ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5); 3651 } else if (AR_SREV_HONEYBEE(ah)) { 3652 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3653 qca953xCommon_rx_gain_table_honeybee_1p0, 3654 ARRAY_LENGTH(qca953xCommon_rx_gain_table_honeybee_1p0), 2); 3655 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3656 qca953xCommon_rx_gain_bounds_honeybee_1p0, 3657 ARRAY_LENGTH(qca953xCommon_rx_gain_bounds_honeybee_1p0), 5); 3658 } else { 3659 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3660 ar9300_common_rx_gain_table_osprey_2p2, 3661 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 3662 } 3663 break; 3664 case 1: 3665 if (AR_SREV_HORNET_12(ah)) { 3666 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3667 ar9331_common_wo_xlna_rx_gain_hornet1_2, 3668 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2); 3669 } else if (AR_SREV_HORNET_11(ah)) { 3670 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3671 ar9331_common_wo_xlna_rx_gain_hornet1_1, 3672 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2); 3673 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3674 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3675 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3676 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3677 } else if (AR_SREV_POSEIDON(ah)) { 3678 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3679 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3680 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3681 } else if (AR_SREV_JUPITER_10(ah)) { 3682 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3683 ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0, 3684 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0), 3685 2); 3686 } else if (AR_SREV_JUPITER_20(ah)) { 3687 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3688 ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0, 3689 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0), 3690 2); 3691 } else if (AR_SREV_JUPITER_21(ah)) { 3692 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3693 ar9462_2p1_common_wo_xlna_rx_gain, 3694 ARRAY_LENGTH(ar9462_2p1_common_wo_xlna_rx_gain), 3695 2); 3696 } else if (AR_SREV_APHRODITE(ah)) { 3697 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3698 ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0, 3699 ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0), 3700 2); 3701 } else if (AR_SREV_AR9580(ah)) { 3702 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3703 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0, 3704 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2); 3705 } else if (AR_SREV_WASP(ah)) { 3706 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3707 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 3708 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 3709 } else if (AR_SREV_SCORPION(ah)) { 3710 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3711 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 3712 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 3713 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3714 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 3715 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 3716 } else if (AR_SREV_HONEYBEE(ah)) { 3717 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3718 qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0, 3719 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0), 2); 3720 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3721 qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0, 3722 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0), 5); 3723 } else { 3724 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3725 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2, 3726 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2); 3727 } 3728 break; 3729 } 3730} 3731 3732void ar9300_tx_gain_table_apply(struct ath_hal *ah) 3733{ 3734 struct ath_hal_9300 *ahp = AH9300(ah); 3735 3736 switch (ar9300_tx_gain_index_get(ah)) 3737 { 3738 case 0: 3739 default: 3740 if (AR_SREV_HORNET_12(ah)) { 3741 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3742 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 3743 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 3744 } else if (AR_SREV_HORNET_11(ah)) { 3745 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3746 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 3747 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 3748 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3749 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3750 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 3751 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 3752 } else if (AR_SREV_POSEIDON(ah)) { 3753 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3754 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 3755 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 3756 } else if (AR_SREV_AR9580(ah)) { 3757 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3758 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 3759 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 3760 5); 3761 } else if (AR_SREV_WASP(ah)) { 3762 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3763 ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0, 3764 ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0), 3765 5); 3766 } else if (AR_SREV_SCORPION(ah)) { 3767 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3768 ar955xModes_xpa_tx_gain_table_scorpion_1p0, 3769 ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0), 3770 9); 3771 } else if (AR_SREV_JUPITER_10(ah)) { 3772 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3773 ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0, 3774 ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0), 3775 5); 3776 } else if (AR_SREV_JUPITER_20(ah)) { 3777 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3778 ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0, 3779 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0), 3780 5); 3781 } else if (AR_SREV_JUPITER_21(ah)) { 3782 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3783 ar9462_2p1_modes_low_ob_db_tx_gain, 3784 ARRAY_LENGTH(ar9462_2p1_modes_low_ob_db_tx_gain), 3785 5); 3786 } else if (AR_SREV_HONEYBEE(ah)) { 3787 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3788 qca953xModes_xpa_tx_gain_table_honeybee_1p0, 3789 ARRAY_LENGTH(qca953xModes_xpa_tx_gain_table_honeybee_1p0), 3790 2); 3791 } else if (AR_SREV_APHRODITE(ah)) { 3792 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3793 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3794 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 3795 5); 3796 } else { 3797 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3798 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 3799 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 3800 5); 3801 } 3802 break; 3803 case 1: 3804 if (AR_SREV_HORNET_12(ah)) { 3805 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3806 ar9331_modes_high_ob_db_tx_gain_hornet1_2, 3807 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5); 3808 } else if (AR_SREV_HORNET_11(ah)) { 3809 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3810 ar9331_modes_high_ob_db_tx_gain_hornet1_1, 3811 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5); 3812 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3813 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3814 ar9485_modes_high_ob_db_tx_gain_poseidon1_1, 3815 ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5); 3816 } else if (AR_SREV_POSEIDON(ah)) { 3817 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3818 ar9485Modes_high_ob_db_tx_gain_poseidon1_0, 3819 ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5); 3820 } else if (AR_SREV_AR9580(ah)) { 3821 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3822 ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0, 3823 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0), 3824 5); 3825 } else if (AR_SREV_WASP(ah)) { 3826 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3827 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 3828 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 3829 } else if (AR_SREV_SCORPION(ah)) { 3830 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3831 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 3832 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9); 3833 } else if (AR_SREV_JUPITER_10(ah)) { 3834 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3835 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0, 3836 ARRAY_LENGTH( 3837 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5); 3838 } else if (AR_SREV_JUPITER_20(ah)) { 3839 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3840 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0, 3841 ARRAY_LENGTH( 3842 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5); 3843 } else if (AR_SREV_JUPITER_21(ah)) { 3844 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3845 ar9462_2p1_modes_high_ob_db_tx_gain, 3846 ARRAY_LENGTH( 3847 ar9462_2p1_modes_high_ob_db_tx_gain), 5); 3848 } else if (AR_SREV_APHRODITE(ah)) { 3849 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3850 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0, 3851 ARRAY_LENGTH( 3852 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5); 3853 } else if (AR_SREV_HONEYBEE(ah)) { 3854 if (AR_SREV_HONEYBEE_11(ah)) { 3855 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3856 qca953xModes_no_xpa_tx_gain_table_honeybee_1p1, 3857 ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p1), 2); 3858 } else { 3859 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3860 qca953xModes_no_xpa_tx_gain_table_honeybee_1p0, 3861 ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p0), 2); 3862 } 3863 } else { 3864 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3865 ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2, 3866 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2), 3867 5); 3868 } 3869 break; 3870 case 2: 3871 if (AR_SREV_HORNET_12(ah)) { 3872 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3873 ar9331_modes_low_ob_db_tx_gain_hornet1_2, 3874 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5); 3875 } else if (AR_SREV_HORNET_11(ah)) { 3876 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3877 ar9331_modes_low_ob_db_tx_gain_hornet1_1, 3878 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5); 3879 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3880 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3881 ar9485_modes_low_ob_db_tx_gain_poseidon1_1, 3882 ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5); 3883 } else if (AR_SREV_POSEIDON(ah)) { 3884 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3885 ar9485Modes_low_ob_db_tx_gain_poseidon1_0, 3886 ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5); 3887 } else if (AR_SREV_AR9580(ah)) { 3888 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3889 ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0, 3890 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0), 3891 5); 3892 } else if (AR_SREV_WASP(ah)) { 3893 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3894 ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0, 3895 ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5); 3896 } else if (AR_SREV_APHRODITE(ah)) { 3897 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3898 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3899 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); 3900 } else { 3901 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3902 ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2, 3903 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2), 3904 5); 3905 } 3906 break; 3907 case 3: 3908 if (AR_SREV_HORNET_12(ah)) { 3909 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3910 ar9331_modes_high_power_tx_gain_hornet1_2, 3911 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5); 3912 } else if (AR_SREV_HORNET_11(ah)) { 3913 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3914 ar9331_modes_high_power_tx_gain_hornet1_1, 3915 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5); 3916 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3917 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3918 ar9485_modes_high_power_tx_gain_poseidon1_1, 3919 ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5); 3920 } else if (AR_SREV_POSEIDON(ah)) { 3921 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3922 ar9485Modes_high_power_tx_gain_poseidon1_0, 3923 ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5); 3924 } else if (AR_SREV_AR9580(ah)) { 3925 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3926 ar9300Modes_high_power_tx_gain_table_ar9580_1p0, 3927 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0), 3928 5); 3929 } else if (AR_SREV_WASP(ah)) { 3930 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3931 ar9340Modes_high_power_tx_gain_table_wasp_1p0, 3932 ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0), 3933 5); 3934 } else if (AR_SREV_APHRODITE(ah)) { 3935 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3936 ar956XModes_high_power_tx_gain_table_aphrodite_1p0, 3937 ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5); 3938 } else { 3939 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3940 ar9300Modes_high_power_tx_gain_table_osprey_2p2, 3941 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2), 3942 5); 3943 } 3944 break; 3945 case 4: 3946 if (AR_SREV_WASP(ah)) { 3947 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3948 ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0, 3949 ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0), 3950 5); 3951 } else if (AR_SREV_AR9580(ah)) { 3952 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3953 ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0, 3954 ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0), 3955 5); 3956 } else { 3957 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3958 ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2, 3959 ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2), 3960 5); 3961 } 3962 break; 3963 case 5: 3964 /* HW Green TX */ 3965 if (AR_SREV_POSEIDON(ah)) { 3966 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3967 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3968 ar9485_modes_green_ob_db_tx_gain_poseidon1_1, 3969 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) / 3970 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5); 3971 } else { 3972 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3973 ar9485_modes_green_ob_db_tx_gain_poseidon1_0, 3974 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) / 3975 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5); 3976 } 3977 ahp->ah_hw_green_tx_enable = 1; 3978 } 3979 else if (AR_SREV_WASP(ah)) { 3980 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3981 ar9340_modes_ub124_tx_gain_table_wasp_1p0, 3982 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) / 3983 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5); 3984 } 3985 else if (AR_SREV_AR9580(ah)) { 3986 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3987 ar9300_modes_type5_tx_gain_table_ar9580_1p0, 3988 ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0), 3989 5); 3990 } 3991 else if (AR_SREV_OSPREY_22(ah)) { 3992 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3993 ar9300_modes_number_5_tx_gain_table_osprey_2p2, 3994 ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2), 3995 5); 3996 } 3997 break; 3998 case 6: 3999 if (AR_SREV_WASP(ah)) { 4000 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 4001 ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0, 4002 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) / 4003 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5); 4004 } 4005 /* HW Green TX */ 4006 else if (AR_SREV_POSEIDON(ah)) { 4007 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 4008 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 4009 ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1, 4010 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) / 4011 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]), 4012 5); 4013 } 4014 ahp->ah_hw_green_tx_enable = 1; 4015 } 4016 else if (AR_SREV_AR9580(ah)) { 4017 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 4018 ar9300_modes_type6_tx_gain_table_ar9580_1p0, 4019 ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0), 4020 5); 4021 } 4022 break; 4023 case 7: 4024 if (AR_SREV_WASP(ah)) { 4025 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 4026 ar9340Modes_cus227_tx_gain_table_wasp_1p0, 4027 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) / 4028 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5); 4029 } 4030 break; 4031 } 4032} 4033 4034#if ATH_ANT_DIV_COMB 4035void 4036ar9300_ant_div_comb_get_config(struct ath_hal *ah, 4037 HAL_ANT_COMB_CONFIG *div_comb_conf) 4038{ 4039 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 4040 div_comb_conf->main_lna_conf = 4041 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val); 4042 div_comb_conf->alt_lna_conf = 4043 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val); 4044 div_comb_conf->fast_div_bias = 4045 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val); 4046 if (AR_SREV_HORNET_11(ah)) { 4047 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1; 4048 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 4049 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2; 4050 } else { 4051 div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP; 4052 } 4053 4054 /* 4055 * XXX TODO: allow the HAL to override the rssithres and fast_div_bias 4056 * values (eg CUS198.) 4057 */ 4058} 4059 4060void 4061ar9300_ant_div_comb_set_config(struct ath_hal *ah, 4062 HAL_ANT_COMB_CONFIG *div_comb_conf) 4063{ 4064 u_int32_t reg_val; 4065 struct ath_hal_9300 *ahp = AH9300(ah); 4066 4067 /* DO NOTHING when set to fixed antenna for manufacturing purpose */ 4068 if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A 4069 || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) { 4070 return; 4071 } 4072 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 4073 reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | 4074 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | 4075 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | 4076 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | 4077 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); 4078 reg_val |= 4079 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE( 4080 div_comb_conf->main_gaintb); 4081 reg_val |= 4082 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE( 4083 div_comb_conf->alt_gaintb); 4084 reg_val |= 4085 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE( 4086 div_comb_conf->main_lna_conf); 4087 reg_val |= 4088 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE( 4089 div_comb_conf->alt_lna_conf); 4090 reg_val |= 4091 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE( 4092 div_comb_conf->fast_div_bias); 4093 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); 4094 4095} 4096#endif /* ATH_ANT_DIV_COMB */ 4097 4098static void 4099ar9300_init_hostif_offsets(struct ath_hal *ah) 4100{ 4101 AR_HOSTIF_REG(ah, AR_RC) = 4102 AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 4103 AR_HOSTIF_REG(ah, AR_WA) = 4104 AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 4105 AR_HOSTIF_REG(ah, AR_PM_STATE) = 4106 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE); 4107 AR_HOSTIF_REG(ah, AR_H_INFOL) = 4108 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL); 4109 AR_HOSTIF_REG(ah, AR_H_INFOH) = 4110 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH); 4111 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 4112 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 4113 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 4114 AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 4115 AR_HOSTIF_REG(ah, AR_EEPROM) = 4116 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL); 4117 AR_HOSTIF_REG(ah, AR_SREV) = 4118 AR9300_HOSTIF_OFFSET(HOST_INTF_SREV); 4119 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 4120 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4121 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 4122 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4123 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 4124 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 4125 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 4126 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 4127 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 4128 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 4129 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 4130 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4131 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 4132 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4133 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 4134 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4135 AR_HOSTIF_REG(ah, AR_PCIE_SERDES) = 4136 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW); 4137 AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) = 4138 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD); 4139 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4140 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4141 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4142 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4143 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4144 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4145 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4146 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4147 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4148 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4149 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4150 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4151 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4152 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4153 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4154 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4155 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4156 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4157 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4158 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4159 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4160 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4161 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4162 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4163 AR_HOSTIF_REG(ah, AR_SPARE) = 4164 AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE); 4165 AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) = 4166 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN); 4167 AR_HOSTIF_REG(ah, AR_CLKRUN) = 4168 AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4169 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4170 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4171 AR_HOSTIF_REG(ah, AR_OBS) = 4172 AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4173 AR_HOSTIF_REG(ah, AR_RFSILENT) = 4174 AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4175 AR_HOSTIF_REG(ah, AR_GPIO_PDPU) = 4176 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU); 4177 AR_HOSTIF_REG(ah, AR_GPIO_DS) = 4178 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS); 4179 AR_HOSTIF_REG(ah, AR_MISC) = 4180 AR9300_HOSTIF_OFFSET(HOST_INTF_MISC); 4181 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4182 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4183#if 0 /* Offsets are not defined in reg_map structure */ 4184 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) = 4185 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE); 4186 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) = 4187 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY); 4188 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) = 4189 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL); 4190#endif 4191 AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) = 4192 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ); 4193 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4194 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4195 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4196 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4197 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4198 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4199 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4200 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4201 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4202 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4203 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4204 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4205 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4206 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4207 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4208 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4209 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4210 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4211} 4212 4213static void 4214ar9340_init_hostif_offsets(struct ath_hal *ah) 4215{ 4216 AR_HOSTIF_REG(ah, AR_RC) = 4217 AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 4218 AR_HOSTIF_REG(ah, AR_WA) = 4219 AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 4220 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 4221 AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 4222 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 4223 AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 4224 AR_HOSTIF_REG(ah, AR_SREV) = 4225 AR9340_HOSTIF_OFFSET(HOST_INTF_SREV); 4226 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 4227 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4228 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 4229 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4230 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 4231 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 4232 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 4233 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 4234 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 4235 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 4236 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 4237 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4238 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 4239 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4240 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 4241 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4242 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4243 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4244 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4245 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4246 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4247 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4248 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4249 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4250 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4251 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4252 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4253 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4254 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4255 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4256 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4257 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4258 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4259 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4260 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4261 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4262 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4263 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4264 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4265 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4266 AR_HOSTIF_REG(ah, AR_CLKRUN) = 4267 AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4268 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4269 AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4270 AR_HOSTIF_REG(ah, AR_OBS) = 4271 AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4272 AR_HOSTIF_REG(ah, AR_RFSILENT) = 4273 AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4274 AR_HOSTIF_REG(ah, AR_MISC) = 4275 AR9340_HOSTIF_OFFSET(HOST_INTF_MISC); 4276 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4277 AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4278 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4279 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4280 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4281 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4282 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4283 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4284 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4285 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4286 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4287 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4288 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4289 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4290 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4291 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4292 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4293 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4294 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4295 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4296} 4297 4298/* 4299 * Host interface register offsets are different for Osprey and Wasp 4300 * and hence store the offsets in hal structure 4301 */ 4302static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid) 4303{ 4304 if (devid == AR9300_DEVID_AR9340) { 4305 ar9340_init_hostif_offsets(ah); 4306 } else { 4307 ar9300_init_hostif_offsets(ah); 4308 } 4309 return 0; 4310} 4311 4312 4313static const char* 4314ar9300_probe(uint16_t vendorid, uint16_t devid) 4315{ 4316 if (vendorid != ATHEROS_VENDOR_ID) 4317 return AH_NULL; 4318 4319 switch (devid) { 4320 case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */ 4321 return "Atheros AR938x"; 4322 case AR9300_DEVID_AR9340: /* Wasp */ 4323 return "Atheros AR934x"; 4324 case AR9300_DEVID_AR9485_PCIE: /* Poseidon */ 4325 return "Atheros AR9485"; 4326 case AR9300_DEVID_AR9580_PCIE: /* Peacock */ 4327 return "Atheros AR9580"; 4328 case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */ 4329 return "Atheros AR946x/AR948x"; 4330 case AR9300_DEVID_AR9330: /* Hornet */ 4331 return "Atheros AR933x"; 4332 case AR9300_DEVID_QCA955X: /* Scorpion */ 4333 return "Qualcomm Atheros QCA955x"; 4334 case AR9300_DEVID_QCA9565: /* Aphrodite */ 4335 return "Qualcomm Atheros AR9565"; 4336 case AR9300_DEVID_QCA953X: /* Honeybee */ 4337 return "Qualcomm Atheros QCA953x"; 4338 case AR9300_DEVID_AR1111_PCIE: 4339 return "Atheros AR1111"; 4340 default: 4341 return AH_NULL; 4342 } 4343 4344 return AH_NULL; 4345} 4346 4347AH_CHIP(AR9300, ar9300_probe, ar9300_attach); 4348 4349