Searched refs:sel (Results 1 - 25 of 55) sorted by relevance

123

/u-boot/drivers/net/
H A Dmdio_mux_sandbox.c17 int sel; member in struct:mdio_mux_sandbox_priv
20 static int mdio_mux_sandbox_mark_selection(struct udevice *dev, int sel) argument
33 SANDBOX_PHY_REG_CNT - 1, (u16)sel);
36 static int mdio_mux_sandbox_select(struct udevice *dev, int cur, int sel) argument
43 if (cur != priv->sel)
46 priv->sel = sel;
47 mdio_mux_sandbox_mark_selection(dev, priv->sel);
52 static int mdio_mux_sandbox_deselect(struct udevice *dev, int sel) argument
59 if (sel !
[all...]
H A Dmdio_mux_mmioreg.c23 static int mdio_mux_mmioreg_select(struct udevice *mux, int cur, int sel) argument
27 debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel);
30 if (cur == sel)
38 y = (x & ~priv->mask) | (u32)sel;
40 iowrite8((x & ~priv->mask) | sel, (void *)priv->phys);
50 y = (x & ~priv->mask) | (u32)sel;
52 iowrite16((x & ~priv->mask) | sel, (void *)priv->phys);
62 y = (x & ~priv->mask) | (u32)sel;
64 iowrite32((x & ~priv->mask) | sel, (void *)priv->phys);
H A Dmdio_mux_i2creg.c25 static int mdio_mux_i2creg_select(struct udevice *mux, int cur, int sel) argument
31 if (cur == sel)
35 val = (val_old & ~priv->mask) | (sel & priv->mask);
H A Dmdio_mux_meson_gxl.c91 static int mdio_mux_meson_gxl_select(struct udevice *mux, int cur, int sel) argument
95 debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel);
98 if (cur == sel)
101 switch (sel) {
/u-boot/drivers/video/nexell/soc/
H A Ds5pxx18_soc_disptop.c58 void nx_disp_top_set_resconvmux(int benb, u32 sel) argument
64 regvalue = (benb << 31) | (sel << 0);
68 void nx_disp_top_set_hdmimux(int benb, u32 sel) argument
74 regvalue = (benb << 31) | (sel << 0);
78 void nx_disp_top_set_mipimux(int benb, u32 sel) argument
84 regvalue = (benb << 31) | (sel << 0);
88 void nx_disp_top_set_lvdsmux(int benb, u32 sel) argument
94 regvalue = (benb << 31) | (sel << 0);
98 void nx_disp_top_set_primary_mux(u32 sel) argument
103 writel((u32)sel,
106 nx_disp_top_hdmi_set_vsync_start(u32 sel) argument
122 nx_disp_top_hdmi_set_hactive_start(u32 sel) argument
130 nx_disp_top_hdmi_set_hactive_end(u32 sel) argument
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H A Ds5pxx18_soc_disptop.h354 void nx_disp_top_set_resconvmux(int benb, u32 sel);
355 void nx_disp_top_set_hdmimux(int benb, u32 sel);
356 void nx_disp_top_set_mipimux(int benb, u32 sel);
357 void nx_disp_top_set_lvdsmux(int benb, u32 sel);
358 void nx_disp_top_set_primary_mux(u32 sel);
359 void nx_disp_top_hdmi_set_vsync_start(u32 sel);
361 void nx_disp_top_hdmi_set_hactive_start(u32 sel);
362 void nx_disp_top_hdmi_set_hactive_end(u32 sel);
/u-boot/drivers/clk/rockchip/
H A Dclk_rk3588.c136 u32 con, sel, rate;
141 sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >>
143 if (sel == ACLK_CENTER_ROOT_SEL_700M)
145 else if (sel == ACLK_CENTER_ROOT_SEL_400M)
147 else if (sel == ACLK_CENTER_ROOT_SEL_200M)
154 sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >>
156 if (sel == ACLK_CENTER_LOW_ROOT_SEL_500M)
158 else if (sel == ACLK_CENTER_LOW_ROOT_SEL_250M)
160 else if (sel == ACLK_CENTER_LOW_ROOT_SEL_100M)
167 sel
126 u32 con, sel, rate; local
258 u32 con, sel, div, rate, prate; local
355 u32 sel, con; local
464 u32 sel, con; local
549 u32 sel, con; local
628 u32 div, sel, con, prate; local
719 u32 sel, con, div, prate; local
922 u32 div, sel, con, parent; local
1036 u32 div, sel, con, parent; local
1088 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; local
1822 u32 sel; local
2050 u32 con, div, sel, parent; local
2082 u32 div, sel; local
[all...]
H A Dclk_rk3568.c268 u32 div, sel, con, parent; local
273 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;
275 if (sel == CLK_PWM0_SEL_XIN24M)
320 u32 div, con, sel, parent; local
323 sel = (con & PCLK_PDPMU_SEL_MASK) >> PCLK_PDPMU_SEL_SHIFT;
325 if (sel)
716 u32 con, sel, rate; local
721 sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT;
722 if (sel == ACLK_BUS_SEL_200M)
724 else if (sel
797 u32 con, sel, rate; local
876 u32 con, sel, rate; local
1005 u32 sel, con; local
1064 u32 sel, con; local
1141 u32 sel, con; local
1208 u32 div, sel, con, prate; local
1284 u32 sel, con; local
1405 u32 sel, con; local
1503 u32 sel, con; local
1555 u32 sel, con; local
1605 u32 sel, con; local
1669 u32 sel, con; local
1715 u32 div, sel, con, parent; local
1756 u32 conid, div, sel, con, parent; local
1797 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; local
1875 u32 sel, con; local
1925 u32 sel, con; local
1978 u32 sel, con; local
2031 u32 con, sel, div_sel; local
[all...]
H A Dclk_rv1126.c240 u32 div, sel, con; local
245 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;
247 if (sel == CLK_PWM0_SEL_XIN24M)
252 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
254 if (sel == CLK_PWM1_SEL_XIN24M)
594 u32 con, div, sel, parent; local
600 sel = (con & ACLK_PDBUS_SEL_MASK) >> ACLK_PDBUS_SEL_SHIFT;
601 if (sel == ACLK_PDBUS_SEL_GPLL)
603 else if (sel == ACLK_PDBUS_SEL_CPLL)
611 sel
854 u32 div, sel, con; local
913 u32 div, sel, con, parent; local
998 u32 div, sel, con, con_id; local
1079 u32 div, sel, con, parent; local
1111 u32 div, sel, con, parent; local
1143 u32 div, sel, con, parent; local
1176 u32 div, sel, con, parent; local
1239 u32 div, sel, con, parent; local
1272 u32 div, sel, con, parent; local
1305 u32 div, sel, con, parent; local
1338 u32 con, sel, div_sel; local
1380 u32 div, sel, con, parent; local
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/u-boot/include/power/
H A Dstpmic1.h35 #define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT)
50 #define STPMIC1_LDO_VOUT(sel) (sel << STPMIC1_LDO12356_VOUT_SHIFT)
/u-boot/drivers/video/nexell/
H A Ds5pxx18_dp_rgb.c20 int rsc = 0, sel = 0; local
24 sel = mpu ? 1 : 0;
27 sel = rsc ? 3 : 2;
34 nx_disp_top_set_primary_mux(sel);
/u-boot/net/
H A Dmdio-mux-uclass.c44 * @sel: Selection value used by the MDIO MUX to access this child MDIO bus
47 int sel; member in struct:mdio_mux_ch_data
58 static int mmux_change_sel(struct udevice *ch, bool sel) argument
66 if (sel) {
67 err = ops->select(mux, priv->selected, ch_data->sel);
71 priv->selected = ch_data->sel;
74 ops->deselect(mux, ch_data->sel);
144 ch_data->sel = dev_read_u32_default(ch, "reg", MDIO_MUX_SELECT_NONE);
146 if (ch_data->sel == MDIO_MUX_SELECT_NONE)
/u-boot/drivers/power/regulator/
H A Daxp_regulator.c32 int mV, sel; local
37 sel = pmic_reg_read(dev->parent, plat->volt_reg);
38 if (sel < 0)
39 return sel;
41 sel &= plat->volt_mask;
42 sel >>= ffs(plat->volt_mask) - 1;
45 mV = plat->table[sel];
47 if (sel > plat->split)
48 sel = plat->split + (sel
59 uint sel, shift; local
[all...]
H A Dstpmic1.c45 static int stpmic1_output_find_uv(int sel, argument
53 if (sel >= range->min_sel && sel <= range->max_sel)
55 (sel - range->min_sel) * range->step;
142 int sel; local
144 sel = pmic_reg_read(dev, STPMIC1_BUCKX_MAIN_CR(buck));
145 if (sel < 0)
146 return sel;
148 sel &= STPMIC1_BUCK_VOUT_MASK;
149 sel >>
161 int sel, buck = dev->driver_data - 1; local
314 int sel, ldo = dev->driver_data - 1; local
336 int sel, ldo = dev->driver_data - 1; local
[all...]
H A Dpca9450.c143 static int vrange_find_value(struct pca9450_vrange *r, unsigned int sel, argument
146 if (!val || sel < r->min_sel || sel > r->max_sel)
149 *val = r->min_volt + r->step * (sel - r->min_sel);
154 unsigned int *sel)
162 *sel = r->min_sel + ((val - r->min_volt) / r->step);
165 *sel = r->min_sel;
244 unsigned int sel; local
250 found = !vrange_find_selector(r, uvolt, &sel);
258 found = !vrange_find_value(r, sel,
153 vrange_find_selector(struct pca9450_vrange *r, int val, unsigned int *sel) argument
[all...]
H A Dbd71837.c72 #define BD_DATA(_name, enreg, enmask, vreg, vmask, _range, rmask, _dvs, sel) \
77 .sel_mask = (sel) \
246 static int vrange_find_value(struct bd71837_vrange *r, unsigned int sel, argument
249 if (!val || sel < r->min_sel || sel > r->max_sel)
252 *val = r->min_volt + r->step * (sel - r->min_sel);
257 unsigned int *sel)
265 *sel = r->min_sel + ((val - r->min_volt) / r->step);
268 *sel = r->min_sel;
353 unsigned int sel; local
256 vrange_find_selector(struct bd71837_vrange *r, int val, unsigned int *sel) argument
[all...]
H A Dtps65910_regulator.c144 int sel, val, vout; local
151 sel = (val & TPS65910_SEL_MASK) >> 2;
152 vout = (vin >= *(rgp->vin_min + sel)) ? *(rgp->vout + sel) : 0;
197 int sel = 0; local
202 if (uV == *(ldo->vout + sel))
204 } while (++sel < VOUT_CHOICE_COUNT);
205 if (sel == VOUT_CHOICE_COUNT)
207 if (pdata->supply < *(ldo->vin_min + sel))
214 val |= sel <<
[all...]
H A Danatop_regulator.c102 u32 sel; local
113 sel = val - anatop_reg->min_bit_val;
115 return sel * ANATOP_REGULATOR_STEP + anatop_reg->min_voltage;
122 u32 sel; local
134 sel = DIV_ROUND_UP(uV - anatop_reg->min_voltage,
136 if (sel * ANATOP_REGULATOR_STEP + anatop_reg->min_voltage >
139 val = anatop_reg->min_bit_val + sel;
/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c91 clk_get_rate(c); /* Make sure rate and sel are filled in */
97 debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
98 __func__, c->name, c->rate, c->div, c->sel,
122 if (selector_exists(&cd->sel)) {
123 reg = readl(base + cd->sel.offset);
124 bitfield_replace(reg, cd->sel.shift, cd->sel.width,
125 c->sel);
126 writel(reg, base + cd->sel.offset);
193 c->sel
[all...]
/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c91 clk_get_rate(c); /* Make sure rate and sel are filled in */
97 debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
98 __func__, c->name, c->rate, c->div, c->sel,
122 if (selector_exists(&cd->sel)) {
123 reg = readl(base + cd->sel.offset);
124 bitfield_replace(reg, cd->sel.shift, cd->sel.width,
125 c->sel);
126 writel(reg, base + cd->sel.offset);
193 c->sel
[all...]
/u-boot/drivers/net/phy/
H A Datheros.c197 int sel; local
253 sel = AR803x_CLK_25M_25MHZ_XTAL;
256 sel = AR803x_CLK_25M_50MHZ_PLL;
259 sel = AR803x_CLK_25M_62_5MHZ_PLL;
262 sel = AR803x_CLK_25M_125MHZ_PLL;
272 priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_MASK, sel);
288 sel = AR803x_CLK_25M_DR_FULL;
291 sel = AR803x_CLK_25M_DR_HALF;
294 sel = AR803x_CLK_25M_DR_QUARTER;
303 priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_DR_MASK, sel);
[all...]
/u-boot/arch/arm/mach-exynos/
H A Dclock.c642 unsigned int sel; local
650 sel = readl(&clk->src_peril0);
651 sel = (sel >> 24) & 0xf;
653 if (sel == 0x6)
655 else if (sel == 0x7)
657 else if (sel == 0x8)
699 unsigned int sel; local
711 sel = readl(&clk->src_peril0);
712 sel
746 unsigned int sel; local
790 unsigned int sel, ratio, pre_ratio; local
919 unsigned int sel; local
961 unsigned int sel; local
1002 unsigned int sel; local
1036 unsigned int sel; local
[all...]
/u-boot/arch/arm/mach-imx/
H A Dcmd_mfgprot.c33 char *pubk, *sign, *sel; local
39 sel = argv[1];
50 if (strcmp(sel, pubk) == 0) {
68 } else if (strcmp(sel, sign) == 0) {
/u-boot/arch/arm/mach-kirkwood/
H A Dmpp.c55 unsigned int sel = MPP_SEL(*mpp_list); local
79 mpp_ctrl[num / 8] |= sel << shift;
/u-boot/arch/mips/include/asm/
H A Dmipsregs.h1270 * disassembler these will look like an access to sel 0 or 1.
1315 #define ___read_32bit_c0_register(source, sel, vol) \
1317 if (sel == 0) \
1325 "mfc0\t%0, " #source ", " #sel "\n\t" \
1331 #define ___read_64bit_c0_register(source, sel, vol) \
1334 __res = __read_64bit_c0_split(source, sel, vol); \
1335 else if (sel == 0) \
1346 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1352 #define __read_32bit_c0_register(source, sel) \
1353 ___read_32bit_c0_register(source, sel, __volatile_
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