1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. 5 * Author: Finley Xiao <finley.xiao@rock-chips.com> 6 */ 7 8#include <common.h> 9#include <bitfield.h> 10#include <clk-uclass.h> 11#include <dm.h> 12#include <errno.h> 13#include <syscon.h> 14#include <asm/arch-rockchip/clock.h> 15#include <asm/arch-rockchip/cru_rv1126.h> 16#include <asm/arch-rockchip/grf_rv1126.h> 17#include <asm/arch-rockchip/hardware.h> 18#include <dm/device-internal.h> 19#include <dm/lists.h> 20#include <dt-bindings/clock/rockchip,rv1126-cru.h> 21 22DECLARE_GLOBAL_DATA_PTR; 23 24#define RV1126_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ 25{ \ 26 .rate = _rate##U, \ 27 .aclk_div = _aclk_div, \ 28 .pclk_div = _pclk_div, \ 29} 30 31#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 32 33static struct rockchip_cpu_rate_table rv1126_cpu_rates[] = { 34 RV1126_CPUCLK_RATE(1200000000, 1, 5), 35 RV1126_CPUCLK_RATE(1008000000, 1, 5), 36 RV1126_CPUCLK_RATE(816000000, 1, 3), 37 RV1126_CPUCLK_RATE(600000000, 1, 3), 38 RV1126_CPUCLK_RATE(408000000, 1, 1), 39}; 40 41static struct rockchip_pll_rate_table rv1126_pll_rates[] = { 42 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 43 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), 45 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), 46 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), 47 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), 48 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 49 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), 50 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 51 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), 52 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), 53 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), 54 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), 55 RK3036_PLL_RATE(200000000, 1, 100, 6, 2, 1, 0), 56 RK3036_PLL_RATE(100000000, 1, 100, 6, 4, 1, 0), 57 { /* sentinel */ }, 58}; 59 60static struct rockchip_pll_clock rv1126_pll_clks[] = { 61 [APLL] = PLL(pll_rk3328, PLL_APLL, RV1126_PLL_CON(0), 62 RV1126_MODE_CON, 0, 10, 0, rv1126_pll_rates), 63 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1126_PLL_CON(8), 64 RV1126_MODE_CON, 2, 10, 0, NULL), 65 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126_PLL_CON(16), 66 RV1126_MODE_CON, 4, 10, 0, rv1126_pll_rates), 67 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RV1126_PLL_CON(24), 68 RV1126_MODE_CON, 6, 10, 0, rv1126_pll_rates), 69 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126_PMU_PLL_CON(0), 70 RV1126_PMU_MODE, 0, 10, 0, rv1126_pll_rates), 71}; 72 73static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv, 74 struct rv1126_pmuclk_priv *pmu_priv, 75 ulong rate); 76/* 77 * 78 * rational_best_approximation(31415, 10000, 79 * (1 << 8) - 1, (1 << 5) - 1, &n, &d); 80 * 81 * you may look at given_numerator as a fixed point number, 82 * with the fractional part size described in given_denominator. 83 * 84 * for theoretical background, see: 85 * http://en.wikipedia.org/wiki/Continued_fraction 86 */ 87static void rational_best_approximation(unsigned long given_numerator, 88 unsigned long given_denominator, 89 unsigned long max_numerator, 90 unsigned long max_denominator, 91 unsigned long *best_numerator, 92 unsigned long *best_denominator) 93{ 94 unsigned long n, d, n0, d0, n1, d1; 95 96 n = given_numerator; 97 d = given_denominator; 98 n0 = 0; 99 d1 = 0; 100 n1 = 1; 101 d0 = 1; 102 for (;;) { 103 unsigned long t, a; 104 105 if (n1 > max_numerator || d1 > max_denominator) { 106 n1 = n0; 107 d1 = d0; 108 break; 109 } 110 if (d == 0) 111 break; 112 t = d; 113 a = n / d; 114 d = n % d; 115 n = t; 116 t = n0 + a * n1; 117 n0 = n1; 118 n1 = t; 119 t = d0 + a * d1; 120 d0 = d1; 121 d1 = t; 122 } 123 *best_numerator = n1; 124 *best_denominator = d1; 125} 126 127static ulong rv1126_gpll_get_pmuclk(struct rv1126_pmuclk_priv *priv) 128{ 129 return rockchip_pll_get_rate(&rv1126_pll_clks[GPLL], 130 priv->pmucru, GPLL); 131} 132 133static ulong rv1126_gpll_set_pmuclk(struct rv1126_pmuclk_priv *pmu_priv, ulong rate) 134{ 135 struct udevice *cru_dev; 136 struct rv1126_clk_priv *priv; 137 int ret; 138 139 ret = uclass_get_device_by_driver(UCLASS_CLK, 140 DM_DRIVER_GET(rockchip_rv1126_cru), 141 &cru_dev); 142 if (ret) { 143 printf("%s: could not find cru device\n", __func__); 144 return ret; 145 } 146 priv = dev_get_priv(cru_dev); 147 148 if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) { 149 printf("%s: failed to set gpll rate %lu\n", __func__, rate); 150 return -EINVAL; 151 } 152 return 0; 153} 154 155static ulong rv1126_rtc32k_get_pmuclk(struct rv1126_pmuclk_priv *priv) 156{ 157 struct rv1126_pmucru *pmucru = priv->pmucru; 158 unsigned long m, n; 159 u32 fracdiv; 160 161 fracdiv = readl(&pmucru->pmu_clksel_con[13]); 162 m = fracdiv & CLK_RTC32K_FRAC_NUMERATOR_MASK; 163 m >>= CLK_RTC32K_FRAC_NUMERATOR_SHIFT; 164 n = fracdiv & CLK_RTC32K_FRAC_DENOMINATOR_MASK; 165 n >>= CLK_RTC32K_FRAC_DENOMINATOR_SHIFT; 166 167 return OSC_HZ * m / n; 168} 169 170static ulong rv1126_rtc32k_set_pmuclk(struct rv1126_pmuclk_priv *priv, 171 ulong rate) 172{ 173 struct rv1126_pmucru *pmucru = priv->pmucru; 174 unsigned long m, n, val; 175 176 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, 177 RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT); 178 179 rational_best_approximation(rate, OSC_HZ, 180 GENMASK(16 - 1, 0), 181 GENMASK(16 - 1, 0), 182 &m, &n); 183 val = m << CLK_RTC32K_FRAC_NUMERATOR_SHIFT | n; 184 writel(val, &pmucru->pmu_clksel_con[13]); 185 186 return rv1126_rtc32k_get_pmuclk(priv); 187} 188 189static ulong rv1126_i2c_get_pmuclk(struct rv1126_pmuclk_priv *priv, 190 ulong clk_id) 191{ 192 struct rv1126_pmucru *pmucru = priv->pmucru; 193 u32 div, con; 194 195 switch (clk_id) { 196 case CLK_I2C0: 197 con = readl(&pmucru->pmu_clksel_con[2]); 198 div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT; 199 break; 200 case CLK_I2C2: 201 con = readl(&pmucru->pmu_clksel_con[3]); 202 div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; 203 break; 204 default: 205 return -ENOENT; 206 } 207 208 return DIV_TO_RATE(priv->gpll_hz, div); 209} 210 211static ulong rv1126_i2c_set_pmuclk(struct rv1126_pmuclk_priv *priv, 212 ulong clk_id, ulong rate) 213{ 214 struct rv1126_pmucru *pmucru = priv->pmucru; 215 int src_clk_div; 216 217 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 218 assert(src_clk_div - 1 <= 127); 219 220 switch (clk_id) { 221 case CLK_I2C0: 222 rk_clrsetreg(&pmucru->pmu_clksel_con[2], CLK_I2C0_DIV_MASK, 223 (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT); 224 break; 225 case CLK_I2C2: 226 rk_clrsetreg(&pmucru->pmu_clksel_con[3], CLK_I2C2_DIV_MASK, 227 (src_clk_div - 1) << CLK_I2C2_DIV_SHIFT); 228 break; 229 default: 230 return -ENOENT; 231 } 232 233 return rv1126_i2c_get_pmuclk(priv, clk_id); 234} 235 236static ulong rv1126_pwm_get_pmuclk(struct rv1126_pmuclk_priv *priv, 237 ulong clk_id) 238{ 239 struct rv1126_pmucru *pmucru = priv->pmucru; 240 u32 div, sel, con; 241 242 switch (clk_id) { 243 case CLK_PWM0: 244 con = readl(&pmucru->pmu_clksel_con[6]); 245 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; 246 div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; 247 if (sel == CLK_PWM0_SEL_XIN24M) 248 return OSC_HZ; 249 break; 250 case CLK_PWM1: 251 con = readl(&pmucru->pmu_clksel_con[6]); 252 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; 253 div = (con & CLK_PWM1_DIV_MASK) >> CLK_PWM1_DIV_SHIFT; 254 if (sel == CLK_PWM1_SEL_XIN24M) 255 return OSC_HZ; 256 break; 257 default: 258 return -ENOENT; 259 } 260 261 return DIV_TO_RATE(priv->gpll_hz, div); 262} 263 264static ulong rv1126_pwm_set_pmuclk(struct rv1126_pmuclk_priv *priv, 265 ulong clk_id, ulong rate) 266{ 267 struct rv1126_pmucru *pmucru = priv->pmucru; 268 int src_clk_div; 269 270 switch (clk_id) { 271 case CLK_PWM0: 272 if (rate == OSC_HZ) { 273 rk_clrsetreg(&pmucru->pmu_clksel_con[6], 274 CLK_PWM0_SEL_MASK, 275 CLK_PWM0_SEL_XIN24M << CLK_PWM0_SEL_SHIFT); 276 rk_clrsetreg(&pmucru->pmu_clksel_con[6], 277 CLK_PWM0_DIV_MASK, 0); 278 } else { 279 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 280 assert(src_clk_div - 1 <= 127); 281 rk_clrsetreg(&pmucru->pmu_clksel_con[6], 282 CLK_PWM0_DIV_MASK, 283 (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT); 284 rk_clrsetreg(&pmucru->pmu_clksel_con[6], 285 CLK_PWM0_SEL_MASK, 286 CLK_PWM0_SEL_GPLL << CLK_PWM0_SEL_SHIFT); 287 } 288 break; 289 case CLK_PWM1: 290 if (rate == OSC_HZ) { 291 rk_clrsetreg(&pmucru->pmu_clksel_con[6], 292 CLK_PWM1_SEL_MASK, 293 CLK_PWM1_SEL_XIN24M << CLK_PWM1_SEL_SHIFT); 294 rk_clrsetreg(&pmucru->pmu_clksel_con[6], 295 CLK_PWM1_DIV_MASK, 0); 296 } else { 297 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 298 assert(src_clk_div - 1 <= 127); 299 rk_clrsetreg(&pmucru->pmu_clksel_con[6], 300 CLK_PWM1_DIV_MASK, 301 (src_clk_div - 1) << CLK_PWM1_DIV_SHIFT); 302 rk_clrsetreg(&pmucru->pmu_clksel_con[6], 303 CLK_PWM1_SEL_MASK, 304 CLK_PWM1_SEL_GPLL << CLK_PWM1_SEL_SHIFT); 305 } 306 break; 307 default: 308 return -ENOENT; 309 } 310 311 return rv1126_pwm_get_pmuclk(priv, clk_id); 312} 313 314static ulong rv1126_spi_get_pmuclk(struct rv1126_pmuclk_priv *priv) 315{ 316 struct rv1126_pmucru *pmucru = priv->pmucru; 317 u32 div, con; 318 319 con = readl(&pmucru->pmu_clksel_con[9]); 320 div = (con & CLK_SPI0_DIV_MASK) >> CLK_SPI0_DIV_SHIFT; 321 322 return DIV_TO_RATE(priv->gpll_hz, div); 323} 324 325static ulong rv1126_spi_set_pmuclk(struct rv1126_pmuclk_priv *priv, 326 ulong rate) 327{ 328 struct rv1126_pmucru *pmucru = priv->pmucru; 329 int src_clk_div; 330 331 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 332 assert(src_clk_div - 1 <= 127); 333 334 rk_clrsetreg(&pmucru->pmu_clksel_con[9], 335 CLK_SPI0_SEL_MASK | CLK_SPI0_DIV_MASK, 336 CLK_SPI0_SEL_GPLL << CLK_SPI0_SEL_SHIFT | 337 (src_clk_div - 1) << CLK_SPI0_DIV_SHIFT); 338 339 return rv1126_spi_get_pmuclk(priv); 340} 341 342static ulong rv1126_pdpmu_get_pmuclk(struct rv1126_pmuclk_priv *priv) 343{ 344 struct rv1126_pmucru *pmucru = priv->pmucru; 345 u32 div, con; 346 347 con = readl(&pmucru->pmu_clksel_con[1]); 348 div = (con & PCLK_PDPMU_DIV_MASK) >> PCLK_PDPMU_DIV_SHIFT; 349 350 return DIV_TO_RATE(priv->gpll_hz, div); 351} 352 353static ulong rv1126_pdpmu_set_pmuclk(struct rv1126_pmuclk_priv *priv, 354 ulong rate) 355{ 356 struct rv1126_pmucru *pmucru = priv->pmucru; 357 int src_clk_div; 358 359 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 360 assert(src_clk_div - 1 <= 31); 361 362 rk_clrsetreg(&pmucru->pmu_clksel_con[1], 363 PCLK_PDPMU_DIV_MASK, 364 (src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT); 365 366 return rv1126_pdpmu_get_pmuclk(priv); 367} 368 369static ulong rv1126_pmuclk_get_rate(struct clk *clk) 370{ 371 struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); 372 ulong rate = 0; 373 374 if (!priv->gpll_hz) { 375 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 376 return -ENOENT; 377 } 378 379 debug("%s %ld\n", __func__, clk->id); 380 switch (clk->id) { 381 case PLL_GPLL: 382 rate = rv1126_gpll_get_pmuclk(priv); 383 break; 384 case CLK_RTC32K: 385 rate = rv1126_rtc32k_get_pmuclk(priv); 386 break; 387 case CLK_I2C0: 388 case CLK_I2C2: 389 rate = rv1126_i2c_get_pmuclk(priv, clk->id); 390 break; 391 case CLK_PWM0: 392 case CLK_PWM1: 393 rate = rv1126_pwm_get_pmuclk(priv, clk->id); 394 break; 395 case CLK_SPI0: 396 rate = rv1126_spi_get_pmuclk(priv); 397 break; 398 case PCLK_PDPMU: 399 rate = rv1126_pdpmu_get_pmuclk(priv); 400 break; 401 default: 402 debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); 403 return -ENOENT; 404 } 405 406 return rate; 407} 408 409static ulong rv1126_pmuclk_set_rate(struct clk *clk, ulong rate) 410{ 411 struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); 412 ulong ret = 0; 413 414 if (!priv->gpll_hz) { 415 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 416 return -ENOENT; 417 } 418 419 debug("%s %ld %ld\n", __func__, clk->id, rate); 420 switch (clk->id) { 421 case PLL_GPLL: 422 ret = rv1126_gpll_set_pmuclk(priv, rate); 423 break; 424 case CLK_RTC32K: 425 ret = rv1126_rtc32k_set_pmuclk(priv, rate); 426 break; 427 case CLK_I2C0: 428 case CLK_I2C2: 429 ret = rv1126_i2c_set_pmuclk(priv, clk->id, rate); 430 break; 431 case CLK_PWM0: 432 case CLK_PWM1: 433 ret = rv1126_pwm_set_pmuclk(priv, clk->id, rate); 434 break; 435 case CLK_SPI0: 436 ret = rv1126_spi_set_pmuclk(priv, rate); 437 break; 438 case PCLK_PDPMU: 439 ret = rv1126_pdpmu_set_pmuclk(priv, rate); 440 break; 441 default: 442 debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); 443 return -ENOENT; 444 } 445 446 return ret; 447} 448 449static int rv1126_rtc32k_set_parent(struct clk *clk, struct clk *parent) 450{ 451 struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); 452 struct rv1126_pmucru *pmucru = priv->pmucru; 453 454 if (parent->id == CLK_OSC0_DIV32K) 455 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, 456 RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT); 457 else 458 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, 459 RTC32K_SEL_OSC1_32K << RTC32K_SEL_SHIFT); 460 461 return 0; 462} 463 464static int rv1126_pmuclk_set_parent(struct clk *clk, struct clk *parent) 465{ 466 switch (clk->id) { 467 case CLK_RTC32K: 468 return rv1126_rtc32k_set_parent(clk, parent); 469 default: 470 debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); 471 return -ENOENT; 472 } 473} 474 475static struct clk_ops rv1126_pmuclk_ops = { 476 .get_rate = rv1126_pmuclk_get_rate, 477 .set_rate = rv1126_pmuclk_set_rate, 478 .set_parent = rv1126_pmuclk_set_parent, 479}; 480 481static int rv1126_pmuclk_probe(struct udevice *dev) 482{ 483 struct rv1126_pmuclk_priv *priv = dev_get_priv(dev); 484 485 priv->gpll_hz = rv1126_gpll_get_pmuclk(priv); 486 487 return 0; 488} 489 490static int rv1126_pmuclk_of_to_plat(struct udevice *dev) 491{ 492 struct rv1126_pmuclk_priv *priv = dev_get_priv(dev); 493 494 priv->pmucru = dev_read_addr_ptr(dev); 495 496 return 0; 497} 498 499static int rv1126_pmuclk_bind(struct udevice *dev) 500{ 501#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) 502 int ret; 503 504 ret = offsetof(struct rv1126_pmucru, pmu_softrst_con[0]); 505 ret = rockchip_reset_bind(dev, ret, 2); 506 if (ret) 507 debug("Warning: software reset driver bind failed\n"); 508#endif 509 return 0; 510} 511 512static const struct udevice_id rv1126_pmuclk_ids[] = { 513 { .compatible = "rockchip,rv1126-pmucru" }, 514 { } 515}; 516 517U_BOOT_DRIVER(rockchip_rv1126_pmucru) = { 518 .name = "rockchip_rv1126_pmucru", 519 .id = UCLASS_CLK, 520 .of_match = rv1126_pmuclk_ids, 521 .priv_auto = sizeof(struct rv1126_pmuclk_priv), 522 .of_to_plat = rv1126_pmuclk_of_to_plat, 523 .ops = &rv1126_pmuclk_ops, 524 .bind = rv1126_pmuclk_bind, 525 .probe = rv1126_pmuclk_probe, 526}; 527 528static int rv1126_armclk_set_clk(struct rv1126_clk_priv *priv, ulong hz) 529{ 530 struct rv1126_cru *cru = priv->cru; 531 const struct rockchip_cpu_rate_table *rate; 532 ulong old_rate; 533 534 rate = rockchip_get_cpu_settings(rv1126_cpu_rates, hz); 535 if (!rate) { 536 printf("%s unsupported rate\n", __func__); 537 return -EINVAL; 538 } 539 540 /* 541 * set up dependent divisors for DBG and ACLK clocks. 542 */ 543 old_rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], 544 priv->cru, APLL); 545 if (old_rate > hz) { 546 if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL], 547 priv->cru, APLL, hz)) 548 return -EINVAL; 549 rk_clrsetreg(&cru->clksel_con[1], 550 CORE_DBG_DIV_MASK | CORE_ACLK_DIV_MASK, 551 rate->pclk_div << CORE_DBG_DIV_SHIFT | 552 rate->aclk_div << CORE_ACLK_DIV_SHIFT); 553 } else if (old_rate < hz) { 554 rk_clrsetreg(&cru->clksel_con[1], 555 CORE_DBG_DIV_MASK | CORE_ACLK_DIV_MASK, 556 rate->pclk_div << CORE_DBG_DIV_SHIFT | 557 rate->aclk_div << CORE_ACLK_DIV_SHIFT); 558 if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL], 559 priv->cru, APLL, hz)) 560 return -EINVAL; 561 } 562 563 return 0; 564} 565 566static ulong rv1126_pdcore_get_clk(struct rv1126_clk_priv *priv) 567{ 568 struct rv1126_cru *cru = priv->cru; 569 u32 con, div; 570 571 con = readl(&cru->clksel_con[0]); 572 div = (con & CORE_HCLK_DIV_MASK) >> CORE_HCLK_DIV_SHIFT; 573 574 return DIV_TO_RATE(priv->gpll_hz, div); 575} 576 577static ulong rv1126_pdcore_set_clk(struct rv1126_clk_priv *priv, ulong rate) 578{ 579 struct rv1126_cru *cru = priv->cru; 580 int src_clk_div; 581 582 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 583 assert(src_clk_div - 1 <= 31); 584 585 rk_clrsetreg(&cru->clksel_con[0], CORE_HCLK_DIV_MASK, 586 (src_clk_div - 1) << CORE_HCLK_DIV_SHIFT); 587 588 return rv1126_pdcore_get_clk(priv); 589} 590 591static ulong rv1126_pdbus_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) 592{ 593 struct rv1126_cru *cru = priv->cru; 594 u32 con, div, sel, parent; 595 596 switch (clk_id) { 597 case ACLK_PDBUS: 598 con = readl(&cru->clksel_con[2]); 599 div = (con & ACLK_PDBUS_DIV_MASK) >> ACLK_PDBUS_DIV_SHIFT; 600 sel = (con & ACLK_PDBUS_SEL_MASK) >> ACLK_PDBUS_SEL_SHIFT; 601 if (sel == ACLK_PDBUS_SEL_GPLL) 602 parent = priv->gpll_hz; 603 else if (sel == ACLK_PDBUS_SEL_CPLL) 604 parent = priv->cpll_hz; 605 else 606 return -ENOENT; 607 break; 608 case HCLK_PDBUS: 609 con = readl(&cru->clksel_con[2]); 610 div = (con & HCLK_PDBUS_DIV_MASK) >> HCLK_PDBUS_DIV_SHIFT; 611 sel = (con & HCLK_PDBUS_SEL_MASK) >> HCLK_PDBUS_SEL_SHIFT; 612 if (sel == HCLK_PDBUS_SEL_GPLL) 613 parent = priv->gpll_hz; 614 else if (sel == HCLK_PDBUS_SEL_CPLL) 615 parent = priv->cpll_hz; 616 else 617 return -ENOENT; 618 break; 619 case PCLK_PDBUS: 620 case PCLK_WDT: 621 con = readl(&cru->clksel_con[3]); 622 div = (con & PCLK_PDBUS_DIV_MASK) >> PCLK_PDBUS_DIV_SHIFT; 623 sel = (con & PCLK_PDBUS_SEL_MASK) >> PCLK_PDBUS_SEL_SHIFT; 624 if (sel == PCLK_PDBUS_SEL_GPLL) 625 parent = priv->gpll_hz; 626 else if (sel == PCLK_PDBUS_SEL_CPLL) 627 parent = priv->cpll_hz; 628 else 629 return -ENOENT; 630 break; 631 default: 632 return -ENOENT; 633 } 634 635 return DIV_TO_RATE(parent, div); 636} 637 638static ulong rv1126_pdbus_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, 639 ulong rate) 640{ 641 struct rv1126_cru *cru = priv->cru; 642 int src_clk_div, clk_sel; 643 644 switch (clk_id) { 645 case ACLK_PDBUS: 646 if (CPLL_HZ % rate) { 647 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 648 clk_sel = ACLK_PDBUS_SEL_GPLL; 649 } else { 650 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); 651 clk_sel = ACLK_PDBUS_SEL_CPLL; 652 } 653 assert(src_clk_div - 1 <= 31); 654 rk_clrsetreg(&cru->clksel_con[2], 655 ACLK_PDBUS_SEL_MASK | ACLK_PDBUS_DIV_MASK, 656 clk_sel << ACLK_PDBUS_SEL_SHIFT | 657 (src_clk_div - 1) << ACLK_PDBUS_DIV_SHIFT); 658 break; 659 case HCLK_PDBUS: 660 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 661 assert(src_clk_div - 1 <= 31); 662 rk_clrsetreg(&cru->clksel_con[2], 663 HCLK_PDBUS_SEL_MASK | HCLK_PDBUS_DIV_MASK, 664 HCLK_PDBUS_SEL_GPLL << HCLK_PDBUS_SEL_SHIFT | 665 (src_clk_div - 1) << HCLK_PDBUS_DIV_SHIFT); 666 break; 667 case PCLK_PDBUS: 668 case PCLK_WDT: 669 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 670 assert(src_clk_div - 1 <= 31); 671 rk_clrsetreg(&cru->clksel_con[3], 672 PCLK_PDBUS_SEL_MASK | PCLK_PDBUS_DIV_MASK, 673 PCLK_PDBUS_SEL_GPLL << PCLK_PDBUS_SEL_SHIFT | 674 (src_clk_div - 1) << PCLK_PDBUS_DIV_SHIFT); 675 break; 676 677 default: 678 printf("do not support this pdbus freq\n"); 679 return -EINVAL; 680 } 681 682 return rv1126_pdbus_get_clk(priv, clk_id); 683} 684 685static ulong rv1126_pdphp_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) 686{ 687 struct rv1126_cru *cru = priv->cru; 688 u32 con, div, parent; 689 690 switch (clk_id) { 691 case ACLK_PDPHP: 692 con = readl(&cru->clksel_con[53]); 693 div = (con & ACLK_PDPHP_DIV_MASK) >> ACLK_PDPHP_DIV_SHIFT; 694 parent = priv->gpll_hz; 695 break; 696 case HCLK_PDPHP: 697 con = readl(&cru->clksel_con[53]); 698 div = (con & HCLK_PDPHP_DIV_MASK) >> HCLK_PDPHP_DIV_SHIFT; 699 parent = priv->gpll_hz; 700 break; 701 default: 702 return -ENOENT; 703 } 704 705 return DIV_TO_RATE(parent, div); 706} 707 708static ulong rv1126_pdphp_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, 709 ulong rate) 710{ 711 struct rv1126_cru *cru = priv->cru; 712 int src_clk_div; 713 714 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 715 assert(src_clk_div - 1 <= 31); 716 717 switch (clk_id) { 718 case ACLK_PDPHP: 719 rk_clrsetreg(&cru->clksel_con[53], 720 ACLK_PDPHP_SEL_MASK | ACLK_PDPHP_DIV_MASK, 721 ACLK_PDPHP_SEL_GPLL << ACLK_PDPHP_SEL_SHIFT | 722 (src_clk_div - 1) << ACLK_PDPHP_DIV_SHIFT); 723 break; 724 case HCLK_PDPHP: 725 rk_clrsetreg(&cru->clksel_con[53], 726 HCLK_PDPHP_DIV_MASK, 727 (src_clk_div - 1) << HCLK_PDPHP_DIV_SHIFT); 728 break; 729 default: 730 printf("do not support this pdphp freq\n"); 731 return -EINVAL; 732 } 733 734 return rv1126_pdphp_get_clk(priv, clk_id); 735} 736 737static ulong rv1126_pdaudio_get_clk(struct rv1126_clk_priv *priv) 738{ 739 struct rv1126_cru *cru = priv->cru; 740 u32 con, div; 741 742 con = readl(&cru->clksel_con[26]); 743 div = (con & HCLK_PDAUDIO_DIV_MASK) >> HCLK_PDAUDIO_DIV_SHIFT; 744 745 return DIV_TO_RATE(priv->gpll_hz, div); 746} 747 748static ulong rv1126_pdaudio_set_clk(struct rv1126_clk_priv *priv, ulong rate) 749{ 750 struct rv1126_cru *cru = priv->cru; 751 int src_clk_div; 752 753 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 754 assert(src_clk_div - 1 <= 31); 755 756 rk_clrsetreg(&cru->clksel_con[26], HCLK_PDAUDIO_DIV_MASK, 757 (src_clk_div - 1) << HCLK_PDAUDIO_DIV_SHIFT); 758 759 return rv1126_pdaudio_get_clk(priv); 760} 761 762static ulong rv1126_i2c_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) 763{ 764 struct rv1126_cru *cru = priv->cru; 765 u32 div, con; 766 767 switch (clk_id) { 768 case CLK_I2C1: 769 con = readl(&cru->clksel_con[5]); 770 div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; 771 break; 772 case CLK_I2C3: 773 con = readl(&cru->clksel_con[5]); 774 div = (con & CLK_I2C3_DIV_MASK) >> CLK_I2C3_DIV_SHIFT; 775 break; 776 case CLK_I2C4: 777 con = readl(&cru->clksel_con[6]); 778 div = (con & CLK_I2C4_DIV_MASK) >> CLK_I2C4_DIV_SHIFT; 779 break; 780 case CLK_I2C5: 781 con = readl(&cru->clksel_con[6]); 782 div = (con & CLK_I2C5_DIV_MASK) >> CLK_I2C5_DIV_SHIFT; 783 break; 784 default: 785 return -ENOENT; 786 } 787 788 return DIV_TO_RATE(priv->gpll_hz, div); 789} 790 791static ulong rv1126_i2c_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, 792 ulong rate) 793{ 794 struct rv1126_cru *cru = priv->cru; 795 int src_clk_div; 796 797 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 798 assert(src_clk_div - 1 <= 127); 799 800 switch (clk_id) { 801 case CLK_I2C1: 802 rk_clrsetreg(&cru->clksel_con[5], CLK_I2C1_DIV_MASK, 803 (src_clk_div - 1) << CLK_I2C1_DIV_SHIFT); 804 break; 805 case CLK_I2C3: 806 rk_clrsetreg(&cru->clksel_con[5], CLK_I2C3_DIV_MASK, 807 (src_clk_div - 1) << CLK_I2C3_DIV_SHIFT); 808 break; 809 case CLK_I2C4: 810 rk_clrsetreg(&cru->clksel_con[6], CLK_I2C4_DIV_MASK, 811 (src_clk_div - 1) << CLK_I2C4_DIV_SHIFT); 812 break; 813 case CLK_I2C5: 814 rk_clrsetreg(&cru->clksel_con[6], CLK_I2C5_DIV_MASK, 815 (src_clk_div - 1) << CLK_I2C5_DIV_SHIFT); 816 break; 817 default: 818 return -ENOENT; 819 } 820 821 return rv1126_i2c_get_clk(priv, clk_id); 822} 823 824static ulong rv1126_spi_get_clk(struct rv1126_clk_priv *priv) 825{ 826 struct rv1126_cru *cru = priv->cru; 827 u32 div, con; 828 829 con = readl(&cru->clksel_con[8]); 830 div = (con & CLK_SPI1_DIV_MASK) >> CLK_SPI1_DIV_SHIFT; 831 832 return DIV_TO_RATE(priv->gpll_hz, div); 833} 834 835static ulong rv1126_spi_set_clk(struct rv1126_clk_priv *priv, ulong rate) 836{ 837 struct rv1126_cru *cru = priv->cru; 838 int src_clk_div; 839 840 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 841 assert(src_clk_div - 1 <= 127); 842 843 rk_clrsetreg(&cru->clksel_con[8], 844 CLK_SPI1_SEL_MASK | CLK_SPI1_DIV_MASK, 845 CLK_SPI1_SEL_GPLL << CLK_SPI1_SEL_SHIFT | 846 (src_clk_div - 1) << CLK_SPI1_DIV_SHIFT); 847 848 return rv1126_spi_get_clk(priv); 849} 850 851static ulong rv1126_pwm_get_clk(struct rv1126_clk_priv *priv) 852{ 853 struct rv1126_cru *cru = priv->cru; 854 u32 div, sel, con; 855 856 con = readl(&cru->clksel_con[9]); 857 sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; 858 div = (con & CLK_PWM2_DIV_MASK) >> CLK_PWM2_DIV_SHIFT; 859 if (sel == CLK_PWM2_SEL_XIN24M) 860 return OSC_HZ; 861 862 return DIV_TO_RATE(priv->gpll_hz, div); 863} 864 865static ulong rv1126_pwm_set_clk(struct rv1126_clk_priv *priv, ulong rate) 866{ 867 struct rv1126_cru *cru = priv->cru; 868 int src_clk_div; 869 870 if (rate == OSC_HZ) { 871 rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_SEL_MASK, 872 CLK_PWM2_SEL_XIN24M << CLK_PWM2_SEL_SHIFT); 873 rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_DIV_MASK, 0); 874 } else { 875 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 876 assert(src_clk_div - 1 <= 127); 877 rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_DIV_MASK, 878 (src_clk_div - 1) << CLK_PWM2_DIV_SHIFT); 879 rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_SEL_MASK, 880 CLK_PWM2_SEL_GPLL << CLK_PWM2_SEL_SHIFT); 881 } 882 883 return rv1126_pwm_get_clk(priv); 884} 885 886static ulong rv1126_saradc_get_clk(struct rv1126_clk_priv *priv) 887{ 888 struct rv1126_cru *cru = priv->cru; 889 u32 div, con; 890 891 con = readl(&cru->clksel_con[20]); 892 div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; 893 894 return DIV_TO_RATE(OSC_HZ, div); 895} 896 897static ulong rv1126_saradc_set_clk(struct rv1126_clk_priv *priv, ulong rate) 898{ 899 struct rv1126_cru *cru = priv->cru; 900 int src_clk_div; 901 902 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); 903 assert(src_clk_div - 1 <= 2047); 904 rk_clrsetreg(&cru->clksel_con[20], CLK_SARADC_DIV_MASK, 905 (src_clk_div - 1) << CLK_SARADC_DIV_SHIFT); 906 907 return rv1126_saradc_get_clk(priv); 908} 909 910static ulong rv1126_crypto_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) 911{ 912 struct rv1126_cru *cru = priv->cru; 913 u32 div, sel, con, parent; 914 915 switch (clk_id) { 916 case CLK_CRYPTO_CORE: 917 con = readl(&cru->clksel_con[7]); 918 div = (con & CLK_CRYPTO_CORE_DIV_MASK) >> CLK_CRYPTO_CORE_DIV_SHIFT; 919 sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >> CLK_CRYPTO_CORE_SEL_SHIFT; 920 if (sel == CLK_CRYPTO_CORE_SEL_GPLL) 921 parent = priv->gpll_hz; 922 else if (sel == CLK_CRYPTO_CORE_SEL_CPLL) 923 parent = priv->cpll_hz; 924 else 925 return -ENOENT; 926 break; 927 case CLK_CRYPTO_PKA: 928 con = readl(&cru->clksel_con[7]); 929 div = (con & CLK_CRYPTO_PKA_DIV_MASK) >> CLK_CRYPTO_PKA_DIV_SHIFT; 930 sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >> CLK_CRYPTO_PKA_SEL_SHIFT; 931 if (sel == CLK_CRYPTO_PKA_SEL_GPLL) 932 parent = priv->gpll_hz; 933 else if (sel == CLK_CRYPTO_PKA_SEL_CPLL) 934 parent = priv->cpll_hz; 935 else 936 return -ENOENT; 937 break; 938 case ACLK_CRYPTO: 939 con = readl(&cru->clksel_con[4]); 940 div = (con & ACLK_CRYPTO_DIV_MASK) >> ACLK_CRYPTO_DIV_SHIFT; 941 sel = (con & ACLK_CRYPTO_SEL_MASK) >> ACLK_CRYPTO_SEL_SHIFT; 942 if (sel == ACLK_CRYPTO_SEL_GPLL) 943 parent = priv->gpll_hz; 944 else if (sel == ACLK_CRYPTO_SEL_CPLL) 945 parent = priv->cpll_hz; 946 else 947 return -ENOENT; 948 break; 949 default: 950 return -ENOENT; 951 } 952 953 return DIV_TO_RATE(parent, div); 954} 955 956static ulong rv1126_crypto_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, 957 ulong rate) 958{ 959 struct rv1126_cru *cru = priv->cru; 960 int src_clk_div; 961 962 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 963 assert(src_clk_div - 1 <= 31); 964 965 switch (clk_id) { 966 case CLK_CRYPTO_CORE: 967 rk_clrsetreg(&cru->clksel_con[7], 968 CLK_CRYPTO_CORE_SEL_MASK | 969 CLK_CRYPTO_CORE_DIV_MASK, 970 CLK_CRYPTO_CORE_SEL_GPLL << 971 CLK_CRYPTO_CORE_SEL_SHIFT | 972 (src_clk_div - 1) << CLK_CRYPTO_CORE_DIV_SHIFT); 973 break; 974 case CLK_CRYPTO_PKA: 975 rk_clrsetreg(&cru->clksel_con[7], 976 CLK_CRYPTO_PKA_SEL_MASK | 977 CLK_CRYPTO_PKA_DIV_MASK, 978 CLK_CRYPTO_PKA_SEL_GPLL << 979 CLK_CRYPTO_PKA_SEL_SHIFT | 980 (src_clk_div - 1) << CLK_CRYPTO_PKA_DIV_SHIFT); 981 break; 982 case ACLK_CRYPTO: 983 rk_clrsetreg(&cru->clksel_con[4], 984 ACLK_CRYPTO_SEL_MASK | ACLK_CRYPTO_DIV_MASK, 985 ACLK_CRYPTO_SEL_GPLL << ACLK_CRYPTO_SEL_SHIFT | 986 (src_clk_div - 1) << ACLK_CRYPTO_DIV_SHIFT); 987 break; 988 default: 989 return -ENOENT; 990 } 991 992 return rv1126_crypto_get_clk(priv, clk_id); 993} 994 995static ulong rv1126_mmc_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) 996{ 997 struct rv1126_cru *cru = priv->cru; 998 u32 div, sel, con, con_id; 999 1000 switch (clk_id) { 1001 case HCLK_SDMMC: 1002 case CLK_SDMMC: 1003 con_id = 55; 1004 break; 1005 case HCLK_SDIO: 1006 case CLK_SDIO: 1007 con_id = 56; 1008 break; 1009 case HCLK_EMMC: 1010 case CLK_EMMC: 1011 case SCLK_EMMC_SAMPLE: 1012 con_id = 57; 1013 break; 1014 default: 1015 return -ENOENT; 1016 } 1017 1018 con = readl(&cru->clksel_con[con_id]); 1019 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 1020 sel = (con & EMMC_SEL_MASK) >> EMMC_SEL_SHIFT; 1021 if (sel == EMMC_SEL_GPLL) 1022 return DIV_TO_RATE(priv->gpll_hz, div) / 2; 1023 else if (sel == EMMC_SEL_CPLL) 1024 return DIV_TO_RATE(priv->cpll_hz, div) / 2; 1025 else if (sel == EMMC_SEL_XIN24M) 1026 return DIV_TO_RATE(OSC_HZ, div) / 2; 1027 1028 return -ENOENT; 1029} 1030 1031static ulong rv1126_mmc_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, 1032 ulong rate) 1033{ 1034 struct rv1126_cru *cru = priv->cru; 1035 int src_clk_div; 1036 u32 con_id; 1037 1038 switch (clk_id) { 1039 case HCLK_SDMMC: 1040 case CLK_SDMMC: 1041 con_id = 55; 1042 break; 1043 case HCLK_SDIO: 1044 case CLK_SDIO: 1045 con_id = 56; 1046 break; 1047 case HCLK_EMMC: 1048 case CLK_EMMC: 1049 con_id = 57; 1050 break; 1051 default: 1052 return -ENOENT; 1053 } 1054 1055 /* Select clk_sdmmc/emmc source from GPLL by default */ 1056 /* mmc clock defaulg div 2 internal, need provide double in cru */ 1057 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, rate); 1058 1059 if (src_clk_div > 127) { 1060 /* use 24MHz source for 400KHz clock */ 1061 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, rate); 1062 rk_clrsetreg(&cru->clksel_con[con_id], 1063 EMMC_SEL_MASK | EMMC_DIV_MASK, 1064 EMMC_SEL_XIN24M << EMMC_SEL_SHIFT | 1065 (src_clk_div - 1) << EMMC_DIV_SHIFT); 1066 } else { 1067 rk_clrsetreg(&cru->clksel_con[con_id], 1068 EMMC_SEL_MASK | EMMC_DIV_MASK, 1069 EMMC_SEL_GPLL << EMMC_SEL_SHIFT | 1070 (src_clk_div - 1) << EMMC_DIV_SHIFT); 1071 } 1072 1073 return rv1126_mmc_get_clk(priv, clk_id); 1074} 1075 1076static ulong rv1126_sfc_get_clk(struct rv1126_clk_priv *priv) 1077{ 1078 struct rv1126_cru *cru = priv->cru; 1079 u32 div, sel, con, parent; 1080 1081 con = readl(&cru->clksel_con[58]); 1082 div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT; 1083 sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT; 1084 if (sel == SCLK_SFC_SEL_GPLL) 1085 parent = priv->gpll_hz; 1086 else if (sel == SCLK_SFC_SEL_CPLL) 1087 parent = priv->cpll_hz; 1088 else 1089 return -ENOENT; 1090 1091 return DIV_TO_RATE(parent, div); 1092} 1093 1094static ulong rv1126_sfc_set_clk(struct rv1126_clk_priv *priv, ulong rate) 1095{ 1096 struct rv1126_cru *cru = priv->cru; 1097 int src_clk_div; 1098 1099 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 1100 rk_clrsetreg(&cru->clksel_con[58], 1101 SCLK_SFC_SEL_MASK | SCLK_SFC_DIV_MASK, 1102 SCLK_SFC_SEL_GPLL << SCLK_SFC_SEL_SHIFT | 1103 (src_clk_div - 1) << SCLK_SFC_DIV_SHIFT); 1104 1105 return rv1126_sfc_get_clk(priv); 1106} 1107 1108static ulong rv1126_nand_get_clk(struct rv1126_clk_priv *priv) 1109{ 1110 struct rv1126_cru *cru = priv->cru; 1111 u32 div, sel, con, parent; 1112 1113 con = readl(&cru->clksel_con[59]); 1114 div = (con & CLK_NANDC_DIV_MASK) >> CLK_NANDC_DIV_SHIFT; 1115 sel = (con & CLK_NANDC_SEL_MASK) >> CLK_NANDC_SEL_SHIFT; 1116 if (sel == CLK_NANDC_SEL_GPLL) 1117 parent = priv->gpll_hz; 1118 else if (sel == CLK_NANDC_SEL_CPLL) 1119 parent = priv->cpll_hz; 1120 else 1121 return -ENOENT; 1122 1123 return DIV_TO_RATE(parent, div); 1124} 1125 1126static ulong rv1126_nand_set_clk(struct rv1126_clk_priv *priv, ulong rate) 1127{ 1128 struct rv1126_cru *cru = priv->cru; 1129 int src_clk_div; 1130 1131 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 1132 rk_clrsetreg(&cru->clksel_con[59], 1133 CLK_NANDC_SEL_MASK | CLK_NANDC_DIV_MASK, 1134 CLK_NANDC_SEL_GPLL << CLK_NANDC_SEL_SHIFT | 1135 (src_clk_div - 1) << CLK_NANDC_DIV_SHIFT); 1136 1137 return rv1126_nand_get_clk(priv); 1138} 1139 1140static ulong rv1126_aclk_vop_get_clk(struct rv1126_clk_priv *priv) 1141{ 1142 struct rv1126_cru *cru = priv->cru; 1143 u32 div, sel, con, parent; 1144 1145 con = readl(&cru->clksel_con[45]); 1146 div = (con & ACLK_PDVO_DIV_MASK) >> ACLK_PDVO_DIV_SHIFT; 1147 sel = (con & ACLK_PDVO_SEL_MASK) >> ACLK_PDVO_SEL_SHIFT; 1148 if (sel == ACLK_PDVO_SEL_GPLL) 1149 parent = priv->gpll_hz; 1150 else if (sel == ACLK_PDVO_SEL_CPLL) 1151 parent = priv->cpll_hz; 1152 else 1153 return -ENOENT; 1154 1155 return DIV_TO_RATE(parent, div); 1156} 1157 1158static ulong rv1126_aclk_vop_set_clk(struct rv1126_clk_priv *priv, ulong rate) 1159{ 1160 struct rv1126_cru *cru = priv->cru; 1161 int src_clk_div; 1162 1163 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 1164 assert(src_clk_div - 1 <= 31); 1165 rk_clrsetreg(&cru->clksel_con[45], 1166 ACLK_PDVO_SEL_MASK | ACLK_PDVO_DIV_MASK, 1167 ACLK_PDVO_SEL_GPLL << ACLK_PDVO_SEL_SHIFT | 1168 (src_clk_div - 1) << ACLK_PDVO_DIV_SHIFT); 1169 1170 return rv1126_aclk_vop_get_clk(priv); 1171} 1172 1173static ulong rv1126_dclk_vop_get_clk(struct rv1126_clk_priv *priv) 1174{ 1175 struct rv1126_cru *cru = priv->cru; 1176 u32 div, sel, con, parent; 1177 1178 con = readl(&cru->clksel_con[47]); 1179 div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT; 1180 sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT; 1181 if (sel == DCLK_VOP_SEL_GPLL) 1182 parent = priv->gpll_hz; 1183 else if (sel == DCLK_VOP_SEL_CPLL) 1184 parent = priv->cpll_hz; 1185 else 1186 return -ENOENT; 1187 1188 return DIV_TO_RATE(parent, div); 1189} 1190 1191static ulong rv1126_dclk_vop_set_clk(struct rv1126_clk_priv *priv, ulong rate) 1192{ 1193 struct rv1126_cru *cru = priv->cru; 1194 ulong pll_rate, now, best_rate = 0; 1195 u32 i, div, best_div = 0, best_sel = 0; 1196 1197 for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) { 1198 switch (i) { 1199 case DCLK_VOP_SEL_GPLL: 1200 pll_rate = priv->gpll_hz; 1201 break; 1202 case DCLK_VOP_SEL_CPLL: 1203 pll_rate = priv->cpll_hz; 1204 break; 1205 default: 1206 printf("do not support this vop pll sel\n"); 1207 return -EINVAL; 1208 } 1209 1210 div = DIV_ROUND_UP(pll_rate, rate); 1211 if (div > 255) 1212 continue; 1213 now = pll_rate / div; 1214 if (abs(rate - now) < abs(rate - best_rate)) { 1215 best_rate = now; 1216 best_div = div; 1217 best_sel = i; 1218 } 1219 debug("pll_rate=%lu, best_rate=%lu, best_div=%u, best_sel=%u\n", 1220 pll_rate, best_rate, best_div, best_sel); 1221 } 1222 1223 if (best_rate) { 1224 rk_clrsetreg(&cru->clksel_con[47], 1225 DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK, 1226 best_sel << DCLK_VOP_SEL_SHIFT | 1227 (best_div - 1) << DCLK_VOP_DIV_SHIFT); 1228 } else { 1229 printf("do not support this vop freq %lu\n", rate); 1230 return -EINVAL; 1231 } 1232 1233 return rv1126_dclk_vop_get_clk(priv); 1234} 1235 1236static ulong rv1126_scr1_get_clk(struct rv1126_clk_priv *priv) 1237{ 1238 struct rv1126_cru *cru = priv->cru; 1239 u32 div, sel, con, parent; 1240 1241 con = readl(&cru->clksel_con[3]); 1242 div = (con & CLK_SCR1_DIV_MASK) >> CLK_SCR1_DIV_SHIFT; 1243 sel = (con & CLK_SCR1_SEL_MASK) >> CLK_SCR1_SEL_SHIFT; 1244 if (sel == CLK_SCR1_SEL_GPLL) 1245 parent = priv->gpll_hz; 1246 else if (sel == CLK_SCR1_SEL_CPLL) 1247 parent = priv->cpll_hz; 1248 else 1249 return -ENOENT; 1250 1251 return DIV_TO_RATE(parent, div); 1252} 1253 1254static ulong rv1126_scr1_set_clk(struct rv1126_clk_priv *priv, ulong rate) 1255{ 1256 struct rv1126_cru *cru = priv->cru; 1257 int src_clk_div; 1258 1259 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 1260 assert(src_clk_div - 1 <= 31); 1261 rk_clrsetreg(&cru->clksel_con[3], 1262 CLK_SCR1_SEL_MASK | CLK_SCR1_DIV_MASK, 1263 CLK_SCR1_SEL_GPLL << CLK_SCR1_SEL_SHIFT | 1264 (src_clk_div - 1) << CLK_SCR1_DIV_SHIFT); 1265 1266 return rv1126_scr1_get_clk(priv); 1267} 1268 1269static ulong rv1126_gmac_src_get_clk(struct rv1126_clk_priv *priv) 1270{ 1271 struct rv1126_cru *cru = priv->cru; 1272 u32 div, sel, con, parent; 1273 1274 con = readl(&cru->clksel_con[63]); 1275 div = (con & CLK_GMAC_SRC_DIV_MASK) >> CLK_GMAC_SRC_DIV_SHIFT; 1276 sel = (con & CLK_GMAC_SRC_SEL_MASK) >> CLK_GMAC_SRC_SEL_SHIFT; 1277 if (sel == CLK_GMAC_SRC_SEL_CPLL) 1278 parent = priv->cpll_hz; 1279 else if (sel == CLK_GMAC_SRC_SEL_GPLL) 1280 parent = priv->gpll_hz; 1281 else 1282 return -ENOENT; 1283 1284 return DIV_TO_RATE(parent, div); 1285} 1286 1287static ulong rv1126_gmac_src_set_clk(struct rv1126_clk_priv *priv, ulong rate) 1288{ 1289 struct rv1126_cru *cru = priv->cru; 1290 int src_clk_div; 1291 1292 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); 1293 assert(src_clk_div - 1 <= 31); 1294 rk_clrsetreg(&cru->clksel_con[63], 1295 CLK_GMAC_SRC_SEL_MASK | CLK_GMAC_SRC_DIV_MASK, 1296 CLK_GMAC_SRC_SEL_CPLL << CLK_GMAC_SRC_SEL_SHIFT | 1297 (src_clk_div - 1) << CLK_GMAC_SRC_DIV_SHIFT); 1298 1299 return rv1126_gmac_src_get_clk(priv); 1300} 1301 1302static ulong rv1126_gmac_out_get_clk(struct rv1126_clk_priv *priv) 1303{ 1304 struct rv1126_cru *cru = priv->cru; 1305 u32 div, sel, con, parent; 1306 1307 con = readl(&cru->clksel_con[61]); 1308 div = (con & CLK_GMAC_OUT_DIV_MASK) >> CLK_GMAC_OUT_DIV_SHIFT; 1309 sel = (con & CLK_GMAC_OUT_SEL_MASK) >> CLK_GMAC_OUT_SEL_SHIFT; 1310 if (sel == CLK_GMAC_OUT_SEL_CPLL) 1311 parent = priv->cpll_hz; 1312 else if (sel == CLK_GMAC_OUT_SEL_GPLL) 1313 parent = priv->gpll_hz; 1314 else 1315 return -ENOENT; 1316 1317 return DIV_TO_RATE(parent, div); 1318} 1319 1320static ulong rv1126_gmac_out_set_clk(struct rv1126_clk_priv *priv, ulong rate) 1321{ 1322 struct rv1126_cru *cru = priv->cru; 1323 int src_clk_div; 1324 1325 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); 1326 assert(src_clk_div - 1 <= 31); 1327 rk_clrsetreg(&cru->clksel_con[61], 1328 CLK_GMAC_OUT_SEL_MASK | CLK_GMAC_OUT_DIV_MASK, 1329 CLK_GMAC_OUT_SEL_CPLL << CLK_GMAC_OUT_SEL_SHIFT | 1330 (src_clk_div - 1) << CLK_GMAC_OUT_DIV_SHIFT); 1331 1332 return rv1126_gmac_out_get_clk(priv); 1333} 1334 1335static ulong rv1126_gmac_tx_rx_set_clk(struct rv1126_clk_priv *priv, ulong rate) 1336{ 1337 struct rv1126_cru *cru = priv->cru; 1338 u32 con, sel, div_sel; 1339 1340 con = readl(&cru->gmac_con); 1341 sel = (con & GMAC_MODE_SEL_MASK) >> GMAC_MODE_SEL_SHIFT; 1342 1343 if (sel == GMAC_RGMII_MODE) { 1344 if (rate == 2500000) 1345 div_sel = RGMII_CLK_DIV50; 1346 else if (rate == 25000000) 1347 div_sel = RGMII_CLK_DIV5; 1348 else 1349 div_sel = RGMII_CLK_DIV0; 1350 rk_clrsetreg(&cru->gmac_con, RGMII_CLK_SEL_MASK, 1351 div_sel << RGMII_CLK_SEL_SHIFT); 1352 } else if (sel == GMAC_RMII_MODE) { 1353 if (rate == 2500000) 1354 div_sel = RMII_CLK_DIV20; 1355 else 1356 div_sel = RMII_CLK_DIV2; 1357 rk_clrsetreg(&cru->gmac_con, RMII_CLK_SEL_MASK, 1358 div_sel << RMII_CLK_SEL_SHIFT); 1359 } 1360 1361 return 0; 1362} 1363 1364static ulong rv1126_pclk_gmac_get_clk(struct rv1126_clk_priv *priv) 1365{ 1366 struct rv1126_cru *cru = priv->cru; 1367 u32 div, con, parent; 1368 1369 parent = rv1126_pdphp_get_clk(priv, ACLK_PDPHP); 1370 1371 con = readl(&cru->clksel_con[63]); 1372 div = (con & PCLK_GMAC_DIV_MASK) >> PCLK_GMAC_DIV_SHIFT; 1373 1374 return DIV_TO_RATE(parent, div); 1375} 1376 1377static ulong rv1126_dclk_decom_get_clk(struct rv1126_clk_priv *priv) 1378{ 1379 struct rv1126_cru *cru = priv->cru; 1380 u32 div, sel, con, parent; 1381 1382 con = readl(&cru->clksel_con[25]); 1383 div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT; 1384 sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT; 1385 if (sel == DCLK_DECOM_SEL_GPLL) 1386 parent = priv->gpll_hz; 1387 else if (sel == DCLK_DECOM_SEL_CPLL) 1388 parent = priv->cpll_hz; 1389 else 1390 return -ENOENT; 1391 1392 return DIV_TO_RATE(parent, div); 1393} 1394 1395static ulong rv1126_dclk_decom_set_clk(struct rv1126_clk_priv *priv, ulong rate) 1396{ 1397 struct rv1126_cru *cru = priv->cru; 1398 u32 src_clk_div; 1399 1400 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); 1401 assert(src_clk_div - 1 <= 127); 1402 rk_clrsetreg(&cru->clksel_con[25], 1403 DCLK_DECOM_SEL_MASK | DCLK_DECOM_DIV_MASK, 1404 DCLK_DECOM_SEL_GPLL << DCLK_DECOM_SEL_SHIFT | 1405 (src_clk_div - 1) << DCLK_DECOM_DIV_SHIFT); 1406 1407 return rv1126_dclk_decom_get_clk(priv); 1408} 1409 1410static ulong rv1126_clk_get_rate(struct clk *clk) 1411{ 1412 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); 1413 ulong rate = 0; 1414 1415 if (!priv->gpll_hz) { 1416 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1417 return -ENOENT; 1418 } 1419 1420 switch (clk->id) { 1421 case PLL_APLL: 1422 case ARMCLK: 1423 rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], priv->cru, 1424 APLL); 1425 break; 1426 case PLL_CPLL: 1427 rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru, 1428 CPLL); 1429 break; 1430 case PLL_HPLL: 1431 rate = rockchip_pll_get_rate(&rv1126_pll_clks[HPLL], priv->cru, 1432 HPLL); 1433 break; 1434 case PLL_DPLL: 1435 rate = rockchip_pll_get_rate(&rv1126_pll_clks[DPLL], priv->cru, 1436 DPLL); 1437 break; 1438 case HCLK_PDCORE_NIU: 1439 rate = rv1126_pdcore_get_clk(priv); 1440 break; 1441 case ACLK_PDBUS: 1442 case HCLK_PDBUS: 1443 case PCLK_PDBUS: 1444 case PCLK_WDT: 1445 rate = rv1126_pdbus_get_clk(priv, clk->id); 1446 break; 1447 case ACLK_PDPHP: 1448 case HCLK_PDPHP: 1449 rate = rv1126_pdphp_get_clk(priv, clk->id); 1450 break; 1451 case HCLK_PDAUDIO: 1452 rate = rv1126_pdaudio_get_clk(priv); 1453 break; 1454 case CLK_I2C1: 1455 case CLK_I2C3: 1456 case CLK_I2C4: 1457 case CLK_I2C5: 1458 rate = rv1126_i2c_get_clk(priv, clk->id); 1459 break; 1460 case CLK_SPI1: 1461 rate = rv1126_spi_get_clk(priv); 1462 break; 1463 case CLK_PWM2: 1464 rate = rv1126_pwm_get_clk(priv); 1465 break; 1466 case CLK_SARADC: 1467 rate = rv1126_saradc_get_clk(priv); 1468 break; 1469 case CLK_CRYPTO_CORE: 1470 case CLK_CRYPTO_PKA: 1471 case ACLK_CRYPTO: 1472 rate = rv1126_crypto_get_clk(priv, clk->id); 1473 break; 1474 case CLK_SDMMC: 1475 case HCLK_SDMMC: 1476 case CLK_SDIO: 1477 case HCLK_SDIO: 1478 case CLK_EMMC: 1479 case HCLK_EMMC: 1480 case SCLK_EMMC_SAMPLE: 1481 rate = rv1126_mmc_get_clk(priv, clk->id); 1482 break; 1483 case SCLK_SFC: 1484 rate = rv1126_sfc_get_clk(priv); 1485 break; 1486 case CLK_NANDC: 1487 rate = rv1126_nand_get_clk(priv); 1488 break; 1489 case ACLK_PDVO: 1490 case ACLK_VOP: 1491 rate = rv1126_aclk_vop_get_clk(priv); 1492 break; 1493 case DCLK_VOP: 1494 rate = rv1126_dclk_vop_get_clk(priv); 1495 break; 1496 case CLK_SCR1_CORE: 1497 rate = rv1126_scr1_get_clk(priv); 1498 break; 1499 case CLK_GMAC_SRC: 1500 rate = rv1126_gmac_src_get_clk(priv); 1501 break; 1502 case CLK_GMAC_ETHERNET_OUT: 1503 rate = rv1126_gmac_out_get_clk(priv); 1504 break; 1505 case PCLK_GMAC: 1506 rate = rv1126_pclk_gmac_get_clk(priv); 1507 break; 1508 case DCLK_DECOM: 1509 rate = rv1126_dclk_decom_get_clk(priv); 1510 break; 1511 default: 1512 debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); 1513 return -ENOENT; 1514 } 1515 1516 return rate; 1517}; 1518 1519static ulong rv1126_clk_set_rate(struct clk *clk, ulong rate) 1520{ 1521 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); 1522 ulong ret = 0; 1523 1524 if (!priv->gpll_hz) { 1525 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1526 return -ENOENT; 1527 } 1528 1529 switch (clk->id) { 1530 case PLL_APLL: 1531 case ARMCLK: 1532 if (priv->armclk_hz) 1533 rv1126_armclk_set_clk(priv, rate); 1534 priv->armclk_hz = rate; 1535 break; 1536 case PLL_CPLL: 1537 ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, 1538 CPLL, rate); 1539 break; 1540 case PLL_HPLL: 1541 ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru, 1542 HPLL, rate); 1543 break; 1544 case ACLK_PDBUS: 1545 case HCLK_PDBUS: 1546 case PCLK_PDBUS: 1547 case PCLK_WDT: 1548 ret = rv1126_pdbus_set_clk(priv, clk->id, rate); 1549 break; 1550 case ACLK_PDPHP: 1551 case HCLK_PDPHP: 1552 ret = rv1126_pdphp_set_clk(priv, clk->id, rate); 1553 break; 1554 case HCLK_PDCORE_NIU: 1555 ret = rv1126_pdcore_set_clk(priv, rate); 1556 break; 1557 case HCLK_PDAUDIO: 1558 ret = rv1126_pdaudio_set_clk(priv, rate); 1559 break; 1560 case CLK_I2C1: 1561 case CLK_I2C3: 1562 case CLK_I2C4: 1563 case CLK_I2C5: 1564 ret = rv1126_i2c_set_clk(priv, clk->id, rate); 1565 break; 1566 case CLK_SPI1: 1567 ret = rv1126_spi_set_clk(priv, rate); 1568 break; 1569 case CLK_PWM2: 1570 ret = rv1126_pwm_set_clk(priv, rate); 1571 break; 1572 case CLK_SARADC: 1573 ret = rv1126_saradc_set_clk(priv, rate); 1574 break; 1575 case CLK_CRYPTO_CORE: 1576 case CLK_CRYPTO_PKA: 1577 case ACLK_CRYPTO: 1578 ret = rv1126_crypto_set_clk(priv, clk->id, rate); 1579 break; 1580 case CLK_SDMMC: 1581 case HCLK_SDMMC: 1582 case CLK_SDIO: 1583 case HCLK_SDIO: 1584 case CLK_EMMC: 1585 case HCLK_EMMC: 1586 ret = rv1126_mmc_set_clk(priv, clk->id, rate); 1587 break; 1588 case SCLK_SFC: 1589 ret = rv1126_sfc_set_clk(priv, rate); 1590 break; 1591 case CLK_NANDC: 1592 ret = rv1126_nand_set_clk(priv, rate); 1593 break; 1594 case ACLK_PDVO: 1595 case ACLK_VOP: 1596 ret = rv1126_aclk_vop_set_clk(priv, rate); 1597 break; 1598 case DCLK_VOP: 1599 ret = rv1126_dclk_vop_set_clk(priv, rate); 1600 break; 1601 case CLK_SCR1_CORE: 1602 ret = rv1126_scr1_set_clk(priv, rate); 1603 break; 1604 case CLK_GMAC_SRC: 1605 ret = rv1126_gmac_src_set_clk(priv, rate); 1606 break; 1607 case CLK_GMAC_ETHERNET_OUT: 1608 ret = rv1126_gmac_out_set_clk(priv, rate); 1609 break; 1610 case CLK_GMAC_TX_RX: 1611 ret = rv1126_gmac_tx_rx_set_clk(priv, rate); 1612 break; 1613 case DCLK_DECOM: 1614 ret = rv1126_dclk_decom_set_clk(priv, rate); 1615 break; 1616 default: 1617 debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); 1618 return -ENOENT; 1619 } 1620 1621 return ret; 1622}; 1623 1624#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1625static int rv1126_gmac_src_set_parent(struct clk *clk, struct clk *parent) 1626{ 1627 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); 1628 struct rv1126_grf *grf = priv->grf; 1629 1630 if (parent->id == CLK_GMAC_SRC_M0) 1631 rk_clrsetreg(&grf->iofunc_con1, GMAC_SRC_SEL_MASK, 1632 GMAC_SRC_SEL_M0 << GMAC_SRC_SEL_SHIFT); 1633 else if (parent->id == CLK_GMAC_SRC_M1) 1634 rk_clrsetreg(&grf->iofunc_con1, GMAC_SRC_SEL_MASK, 1635 GMAC_SRC_SEL_M1 << GMAC_SRC_SEL_SHIFT); 1636 1637 return 0; 1638} 1639 1640static int rv1126_gmac_src_m0_set_parent(struct clk *clk, struct clk *parent) 1641{ 1642 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); 1643 struct rv1126_cru *cru = priv->cru; 1644 1645 if (parent->id == CLK_GMAC_DIV) 1646 rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M0_SEL_MASK, 1647 GMAC_SRC_M0_SEL_INT << GMAC_SRC_M0_SEL_SHIFT); 1648 else 1649 rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M0_SEL_MASK, 1650 GMAC_SRC_M0_SEL_EXT << GMAC_SRC_M0_SEL_SHIFT); 1651 1652 return 0; 1653} 1654 1655static int rv1126_gmac_src_m1_set_parent(struct clk *clk, struct clk *parent) 1656{ 1657 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); 1658 struct rv1126_cru *cru = priv->cru; 1659 1660 if (parent->id == CLK_GMAC_DIV) 1661 rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M1_SEL_MASK, 1662 GMAC_SRC_M1_SEL_INT << GMAC_SRC_M1_SEL_SHIFT); 1663 else 1664 rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M1_SEL_MASK, 1665 GMAC_SRC_M1_SEL_EXT << GMAC_SRC_M1_SEL_SHIFT); 1666 1667 return 0; 1668} 1669 1670static int rv1126_gmac_tx_rx_set_parent(struct clk *clk, struct clk *parent) 1671{ 1672 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); 1673 struct rv1126_cru *cru = priv->cru; 1674 1675 if (parent->id == RGMII_MODE_CLK) 1676 rk_clrsetreg(&cru->gmac_con, GMAC_MODE_SEL_MASK, 1677 GMAC_RGMII_MODE << GMAC_MODE_SEL_SHIFT); 1678 else 1679 rk_clrsetreg(&cru->gmac_con, GMAC_MODE_SEL_MASK, 1680 GMAC_RMII_MODE << GMAC_MODE_SEL_SHIFT); 1681 1682 return 0; 1683} 1684 1685static int rv1126_clk_set_parent(struct clk *clk, struct clk *parent) 1686{ 1687 switch (clk->id) { 1688 case CLK_GMAC_SRC: 1689 return rv1126_gmac_src_set_parent(clk, parent); 1690 case CLK_GMAC_SRC_M0: 1691 return rv1126_gmac_src_m0_set_parent(clk, parent); 1692 case CLK_GMAC_SRC_M1: 1693 return rv1126_gmac_src_m1_set_parent(clk, parent); 1694 case CLK_GMAC_TX_RX: 1695 return rv1126_gmac_tx_rx_set_parent(clk, parent); 1696 default: 1697 return -ENOENT; 1698 } 1699 1700 return 0; 1701} 1702#endif 1703 1704static struct clk_ops rv1126_clk_ops = { 1705 .get_rate = rv1126_clk_get_rate, 1706 .set_rate = rv1126_clk_set_rate, 1707#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1708 .set_parent = rv1126_clk_set_parent, 1709#endif 1710}; 1711 1712static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv, 1713 struct rv1126_pmuclk_priv *pmu_priv, 1714 ulong rate) 1715{ 1716 ulong emmc_rate, sfc_rate, nandc_rate; 1717 bool restore = false; 1718 1719 if (priv->gpll_hz != OSC_HZ) { 1720 emmc_rate = rv1126_mmc_get_clk(priv, CLK_EMMC); 1721 sfc_rate = rv1126_sfc_get_clk(priv); 1722 nandc_rate = rv1126_nand_get_clk(priv); 1723 debug("%s emmc=%lu, sfc=%lu, nandc=%lu\n", __func__, 1724 emmc_rate, sfc_rate, nandc_rate); 1725 restore = true; 1726 } 1727 1728 /* 1729 * the child div is big enough for gpll 1188MHz, 1730 * even maskrom has change some clocks. 1731 */ 1732 if (rockchip_pll_set_rate(&rv1126_pll_clks[GPLL], 1733 pmu_priv->pmucru, GPLL, rate)) 1734 return -EINVAL; 1735 pmu_priv->gpll_hz = rate; 1736 priv->gpll_hz = rate; 1737 1738 if (restore) { 1739 rv1126_mmc_set_clk(priv, CLK_EMMC, emmc_rate); 1740 rv1126_sfc_set_clk(priv, sfc_rate); 1741 rv1126_nand_set_clk(priv, nandc_rate); 1742 } 1743 1744 return 0; 1745} 1746 1747static int rv1126_gpll_set_clk(struct rv1126_clk_priv *priv, ulong rate) 1748{ 1749 struct udevice *pmucru_dev; 1750 struct rv1126_pmuclk_priv *pmu_priv; 1751 int ret; 1752 1753 ret = uclass_get_device_by_driver(UCLASS_CLK, 1754 DM_DRIVER_GET(rockchip_rv1126_pmucru), 1755 &pmucru_dev); 1756 if (ret) { 1757 printf("%s: could not find pmucru device\n", __func__); 1758 return ret; 1759 } 1760 pmu_priv = dev_get_priv(pmucru_dev); 1761 priv->gpll_hz = pmu_priv->gpll_hz; 1762 1763 if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) { 1764 printf("%s: failed to set gpll rate %lu\n", __func__, rate); 1765 return -EINVAL; 1766 } 1767 1768 rv1126_pdpmu_set_pmuclk(pmu_priv, PCLK_PDPMU_HZ); 1769 rv1126_rtc32k_set_pmuclk(pmu_priv, CLK_OSC0_DIV_HZ); 1770 1771 return 0; 1772} 1773 1774static void rv1126_clk_init(struct rv1126_clk_priv *priv) 1775{ 1776 int ret; 1777 1778 priv->sync_kernel = false; 1779 if (!priv->armclk_enter_hz) { 1780 priv->armclk_enter_hz = 1781 rockchip_pll_get_rate(&rv1126_pll_clks[APLL], 1782 priv->cru, APLL); 1783 priv->armclk_init_hz = priv->armclk_enter_hz; 1784 } 1785 1786 if (priv->armclk_init_hz != APLL_HZ) { 1787 ret = rv1126_armclk_set_clk(priv, APLL_HZ); 1788 if (!ret) 1789 priv->armclk_init_hz = APLL_HZ; 1790 } 1791 if (priv->cpll_hz != CPLL_HZ) { 1792 ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, 1793 CPLL, CPLL_HZ); 1794 if (!ret) 1795 priv->cpll_hz = CPLL_HZ; 1796 } 1797 if (priv->hpll_hz != HPLL_HZ) { 1798 ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru, 1799 HPLL, HPLL_HZ); 1800 if (!ret) 1801 priv->hpll_hz = HPLL_HZ; 1802 } 1803 if (priv->gpll_hz != GPLL_HZ) 1804 rv1126_gpll_set_clk(priv, GPLL_HZ); 1805 1806 rv1126_pdbus_set_clk(priv, ACLK_PDBUS, ACLK_PDBUS_HZ); 1807 rv1126_pdbus_set_clk(priv, HCLK_PDBUS, HCLK_PDBUS_HZ); 1808 rv1126_pdbus_set_clk(priv, PCLK_PDBUS, PCLK_PDBUS_HZ); 1809 rv1126_pdphp_set_clk(priv, ACLK_PDPHP, ACLK_PDPHP_HZ); 1810 rv1126_pdphp_set_clk(priv, HCLK_PDPHP, HCLK_PDPHP_HZ); 1811 rv1126_pdcore_set_clk(priv, HCLK_PDCORE_HZ); 1812 rv1126_pdaudio_set_clk(priv, HCLK_PDAUDIO_HZ); 1813} 1814 1815static int rv1126_clk_probe(struct udevice *dev) 1816{ 1817 struct rv1126_clk_priv *priv = dev_get_priv(dev); 1818 int ret; 1819 1820 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1821 if (IS_ERR(priv->grf)) 1822 return PTR_ERR(priv->grf); 1823 1824 rv1126_clk_init(priv); 1825 1826 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1827 ret = clk_set_defaults(dev, 1); 1828 if (ret) 1829 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1830 else 1831 priv->sync_kernel = true; 1832 1833 return 0; 1834} 1835 1836static int rv1126_clk_of_to_plat(struct udevice *dev) 1837{ 1838 struct rv1126_clk_priv *priv = dev_get_priv(dev); 1839 1840 priv->cru = dev_read_addr_ptr(dev); 1841 1842 return 0; 1843} 1844 1845static int rv1126_clk_bind(struct udevice *dev) 1846{ 1847 int ret; 1848 struct udevice *sys_child; 1849 struct sysreset_reg *priv; 1850 1851 /* The reset driver does not have a device node, so bind it here */ 1852 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1853 &sys_child); 1854 if (ret) { 1855 debug("Warning: No sysreset driver: ret=%d\n", ret); 1856 } else { 1857 priv = malloc(sizeof(struct sysreset_reg)); 1858 priv->glb_srst_fst_value = offsetof(struct rv1126_cru, 1859 glb_srst_fst); 1860 priv->glb_srst_snd_value = offsetof(struct rv1126_cru, 1861 glb_srst_snd); 1862 dev_set_priv(sys_child, priv); 1863 } 1864 1865#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) 1866 ret = offsetof(struct rv1126_cru, softrst_con[0]); 1867 ret = rockchip_reset_bind(dev, ret, 15); 1868 if (ret) 1869 debug("Warning: software reset driver bind failed\n"); 1870#endif 1871 return 0; 1872} 1873 1874static const struct udevice_id rv1126_clk_ids[] = { 1875 { .compatible = "rockchip,rv1126-cru" }, 1876 { } 1877}; 1878 1879U_BOOT_DRIVER(rockchip_rv1126_cru) = { 1880 .name = "rockchip_rv1126_cru", 1881 .id = UCLASS_CLK, 1882 .of_match = rv1126_clk_ids, 1883 .priv_auto = sizeof(struct rv1126_clk_priv), 1884 .of_to_plat = rv1126_clk_of_to_plat, 1885 .ops = &rv1126_clk_ops, 1886 .bind = rv1126_clk_bind, 1887 .probe = rv1126_clk_probe, 1888}; 1889