#
d678a59d |
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18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
0e407c74 |
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01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
fba31ab9 |
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19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: atheros: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC) |
#
36af92ba |
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27-Nov-2022 |
Tom Rini <trini@konsulko.com> |
net: phy: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5faf161d |
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23-Feb-2022 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: phy: atheros: avoid error in ar803x_of_init() when PHY has no OF node A DM_ETH driver may use phy_connect() towards a PHY address on an MDIO bus which is not specified in the device tree, as evidenced by: pfe_eth_probe -> pfe_phy_configure -> phy_connect When this happens, the PHY will have an invalid OF node. When ar803x_config() runs, it silently fails at ar803x_of_init(), and therefore, fails to run the rest of the initialization. This makes MII_BMCR contain what it had after BMCR_RESET (0x8000) has been written into it by phy_reset(). Since BMCR_RESET is volatile and self-clearing, the MII_BMCR ends up having a value of 0x0. The further configuration of this register, which is supposed to be handled by genphy_config_aneg() lower in ar803x_config(), never gets a chance to run due to this early error from ar803x_of_init(). As a result of having MII_BMCR as 0, the following symptom appears: => setenv ethact pfe_eth0 => setenv ipaddr 10.0.0.1 => ping 10.0.0.2 pfe_eth0 Waiting for PHY auto negotiation to complete......... TIMEOUT ! Could not initialize PHY pfe_eth0 Manually writing 0x1140 into register 0 of the PHY makes the connection work, but it is rather desirable that the port works without any manual intervention. Fixes: fe6293a80959 ("phy: atheros: add device tree bindings and config") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
338d9b03 |
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18-Jun-2020 |
Fabio Estevam <festevam@gmail.com> |
phy: atheros: ar8035: Fix clock output calculation The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel <o.rempel@pengutronix.de> Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8737c65f |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: consolidate {ar8031|ar8035}_config() The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6333cbb3 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
fe6293a8 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: add device tree bindings and config Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2b772155 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: move delay config to common function Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
f6ae47be |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: introduce debug read and write functions Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
30e31931 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: use defines for PHY IDs Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
f4d48f43 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: fix AR8021 PHY ID mask The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
4d4e4cf7 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the intention of ar8021_config Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
13114f38 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
a234ae86 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the configuration of the CLK_25M output pin Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
29602f9c |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Use common functions for RGMII internal delays Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
4346df33 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
05b60ac5 |
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24-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
net: phy: Clean up includes of common.h We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
1e2d2597 |
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13-Dec-2017 |
Zhao Qiang <qiang.zhao@nxp.com> |
phy: atheros: set auto-negotiation for AR8021 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
ce412b79 |
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13-Oct-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2ec4d10b |
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26-May-2016 |
Andrea Merello <andrea.merello@gmail.com> |
phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
903d384d |
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19-Feb-2016 |
Alison Wang <b18965@freescale.com> |
net: phy: atheros: Fix problem with phy_reset() clearing BMCR In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d584c68c |
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05-Jan-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
02aa4c53 |
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11-Apr-2014 |
Xiaobo Xie <X.Xie@freescale.com> |
AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
#
08ad9b06 |
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20-Apr-2014 |
Zhao Qiang <B45475@freescale.com> |
ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
dc116bd6 |
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04-Mar-2014 |
Haijun.Zhang <Haijun.Zhang@freescale.com> |
net/phy: Correct AR8021 phy_mask There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> |
#
a7e8c15f |
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24-Feb-2014 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
|
#
e0d80964 |
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23-Dec-2013 |
Zhao Qiang <B45475@freescale.com> |
ar8031/8033/phy:enable autonegotiation for ar8031/8033 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9137d19b |
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30-Jan-2014 |
Heiko Schocher <hs@denx.de> |
net, phy: atheros ar803x bug commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
f66e3ded |
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03-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix the masks for AR8031/8035 Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640 |
#
e003ba5b |
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02-Nov-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix masks for AR8035 and AR8021 The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018 |
#
31774578 |
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01-Nov-2013 |
Chunhe Lan <Chunhe.Lan@freescale.com> |
net/phy: Fix the phy id mask of AR8031 The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748 |
#
dfcaa61c |
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22-Sep-2013 |
Heiko Schocher <hs@denx.de> |
net, phy: fix AR8031 phy_mask AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944 |
#
626ee1e3 |
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08-Aug-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
433a2c53 |
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04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
phylib: add atheros ar803x phy add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
6027384a |
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10-Apr-2013 |
Xie Xiaobo <X.Xie@freescale.com> |
phylib: Add Atheros AR8035 GETH PHY support Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
#
06370590 |
|
29-Oct-2012 |
Kim Phillips <kim.phillips@freescale.com> |
net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
9082eeac |
|
07-Apr-2011 |
Andy Fleming <afleming@freescale.com> |
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de> |
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
fba31ab9 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: atheros: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC) |
#
36af92ba |
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27-Nov-2022 |
Tom Rini <trini@konsulko.com> |
net: phy: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5faf161d |
|
23-Feb-2022 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: phy: atheros: avoid error in ar803x_of_init() when PHY has no OF node A DM_ETH driver may use phy_connect() towards a PHY address on an MDIO bus which is not specified in the device tree, as evidenced by: pfe_eth_probe -> pfe_phy_configure -> phy_connect When this happens, the PHY will have an invalid OF node. When ar803x_config() runs, it silently fails at ar803x_of_init(), and therefore, fails to run the rest of the initialization. This makes MII_BMCR contain what it had after BMCR_RESET (0x8000) has been written into it by phy_reset(). Since BMCR_RESET is volatile and self-clearing, the MII_BMCR ends up having a value of 0x0. The further configuration of this register, which is supposed to be handled by genphy_config_aneg() lower in ar803x_config(), never gets a chance to run due to this early error from ar803x_of_init(). As a result of having MII_BMCR as 0, the following symptom appears: => setenv ethact pfe_eth0 => setenv ipaddr 10.0.0.1 => ping 10.0.0.2 pfe_eth0 Waiting for PHY auto negotiation to complete......... TIMEOUT ! Could not initialize PHY pfe_eth0 Manually writing 0x1140 into register 0 of the PHY makes the connection work, but it is rather desirable that the port works without any manual intervention. Fixes: fe6293a80959 ("phy: atheros: add device tree bindings and config") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
338d9b03 |
|
18-Jun-2020 |
Fabio Estevam <festevam@gmail.com> |
phy: atheros: ar8035: Fix clock output calculation The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel <o.rempel@pengutronix.de> Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8737c65f |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: consolidate {ar8031|ar8035}_config() The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6333cbb3 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
fe6293a8 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: add device tree bindings and config Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2b772155 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: move delay config to common function Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
f6ae47be |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: introduce debug read and write functions Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
30e31931 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: use defines for PHY IDs Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
f4d48f43 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: fix AR8021 PHY ID mask The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
4d4e4cf7 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the intention of ar8021_config Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
13114f38 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
a234ae86 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the configuration of the CLK_25M output pin Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
29602f9c |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Use common functions for RGMII internal delays Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
4346df33 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
05b60ac5 |
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24-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
net: phy: Clean up includes of common.h We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
1e2d2597 |
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13-Dec-2017 |
Zhao Qiang <qiang.zhao@nxp.com> |
phy: atheros: set auto-negotiation for AR8021 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
ce412b79 |
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13-Oct-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2ec4d10b |
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26-May-2016 |
Andrea Merello <andrea.merello@gmail.com> |
phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
903d384d |
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19-Feb-2016 |
Alison Wang <b18965@freescale.com> |
net: phy: atheros: Fix problem with phy_reset() clearing BMCR In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d584c68c |
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05-Jan-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
02aa4c53 |
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11-Apr-2014 |
Xiaobo Xie <X.Xie@freescale.com> |
AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
#
08ad9b06 |
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20-Apr-2014 |
Zhao Qiang <B45475@freescale.com> |
ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
dc116bd6 |
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04-Mar-2014 |
Haijun.Zhang <Haijun.Zhang@freescale.com> |
net/phy: Correct AR8021 phy_mask There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> |
#
a7e8c15f |
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24-Feb-2014 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
|
#
e0d80964 |
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23-Dec-2013 |
Zhao Qiang <B45475@freescale.com> |
ar8031/8033/phy:enable autonegotiation for ar8031/8033 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9137d19b |
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30-Jan-2014 |
Heiko Schocher <hs@denx.de> |
net, phy: atheros ar803x bug commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
f66e3ded |
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03-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix the masks for AR8031/8035 Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640 |
#
e003ba5b |
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02-Nov-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix masks for AR8035 and AR8021 The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018 |
#
31774578 |
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01-Nov-2013 |
Chunhe Lan <Chunhe.Lan@freescale.com> |
net/phy: Fix the phy id mask of AR8031 The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748 |
#
dfcaa61c |
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22-Sep-2013 |
Heiko Schocher <hs@denx.de> |
net, phy: fix AR8031 phy_mask AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944 |
#
626ee1e3 |
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08-Aug-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
433a2c53 |
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04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
phylib: add atheros ar803x phy add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
6027384a |
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10-Apr-2013 |
Xie Xiaobo <X.Xie@freescale.com> |
phylib: Add Atheros AR8035 GETH PHY support Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
#
06370590 |
|
29-Oct-2012 |
Kim Phillips <kim.phillips@freescale.com> |
net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
9082eeac |
|
07-Apr-2011 |
Andy Fleming <afleming@freescale.com> |
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de> |
#
fba31ab9 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: atheros: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC) |
#
36af92ba |
|
27-Nov-2022 |
Tom Rini <trini@konsulko.com> |
net: phy: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5faf161d |
|
23-Feb-2022 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: phy: atheros: avoid error in ar803x_of_init() when PHY has no OF node A DM_ETH driver may use phy_connect() towards a PHY address on an MDIO bus which is not specified in the device tree, as evidenced by: pfe_eth_probe -> pfe_phy_configure -> phy_connect When this happens, the PHY will have an invalid OF node. When ar803x_config() runs, it silently fails at ar803x_of_init(), and therefore, fails to run the rest of the initialization. This makes MII_BMCR contain what it had after BMCR_RESET (0x8000) has been written into it by phy_reset(). Since BMCR_RESET is volatile and self-clearing, the MII_BMCR ends up having a value of 0x0. The further configuration of this register, which is supposed to be handled by genphy_config_aneg() lower in ar803x_config(), never gets a chance to run due to this early error from ar803x_of_init(). As a result of having MII_BMCR as 0, the following symptom appears: => setenv ethact pfe_eth0 => setenv ipaddr 10.0.0.1 => ping 10.0.0.2 pfe_eth0 Waiting for PHY auto negotiation to complete......... TIMEOUT ! Could not initialize PHY pfe_eth0 Manually writing 0x1140 into register 0 of the PHY makes the connection work, but it is rather desirable that the port works without any manual intervention. Fixes: fe6293a80959 ("phy: atheros: add device tree bindings and config") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
338d9b03 |
|
18-Jun-2020 |
Fabio Estevam <festevam@gmail.com> |
phy: atheros: ar8035: Fix clock output calculation The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel <o.rempel@pengutronix.de> Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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8737c65f |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: consolidate {ar8031|ar8035}_config() The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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6333cbb3 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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fe6293a8 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: add device tree bindings and config Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2b772155 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: move delay config to common function Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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f6ae47be |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: introduce debug read and write functions Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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30e31931 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: use defines for PHY IDs Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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f4d48f43 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: fix AR8021 PHY ID mask The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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4d4e4cf7 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the intention of ar8021_config Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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13114f38 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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a234ae86 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the configuration of the CLK_25M output pin Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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29602f9c |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Use common functions for RGMII internal delays Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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4346df33 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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05b60ac5 |
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24-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
net: phy: Clean up includes of common.h We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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1e2d2597 |
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13-Dec-2017 |
Zhao Qiang <qiang.zhao@nxp.com> |
phy: atheros: set auto-negotiation for AR8021 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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ce412b79 |
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13-Oct-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2ec4d10b |
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26-May-2016 |
Andrea Merello <andrea.merello@gmail.com> |
phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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903d384d |
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19-Feb-2016 |
Alison Wang <b18965@freescale.com> |
net: phy: atheros: Fix problem with phy_reset() clearing BMCR In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d584c68c |
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05-Jan-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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02aa4c53 |
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11-Apr-2014 |
Xiaobo Xie <X.Xie@freescale.com> |
AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
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08ad9b06 |
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20-Apr-2014 |
Zhao Qiang <B45475@freescale.com> |
ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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dc116bd6 |
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04-Mar-2014 |
Haijun.Zhang <Haijun.Zhang@freescale.com> |
net/phy: Correct AR8021 phy_mask There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> |
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a7e8c15f |
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24-Feb-2014 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
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#
e0d80964 |
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23-Dec-2013 |
Zhao Qiang <B45475@freescale.com> |
ar8031/8033/phy:enable autonegotiation for ar8031/8033 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9137d19b |
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30-Jan-2014 |
Heiko Schocher <hs@denx.de> |
net, phy: atheros ar803x bug commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
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f66e3ded |
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03-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix the masks for AR8031/8035 Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640 |
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e003ba5b |
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02-Nov-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix masks for AR8035 and AR8021 The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018 |
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31774578 |
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01-Nov-2013 |
Chunhe Lan <Chunhe.Lan@freescale.com> |
net/phy: Fix the phy id mask of AR8031 The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748 |
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dfcaa61c |
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22-Sep-2013 |
Heiko Schocher <hs@denx.de> |
net, phy: fix AR8031 phy_mask AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944 |
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626ee1e3 |
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08-Aug-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
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1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
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433a2c53 |
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04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
phylib: add atheros ar803x phy add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
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6027384a |
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10-Apr-2013 |
Xie Xiaobo <X.Xie@freescale.com> |
phylib: Add Atheros AR8035 GETH PHY support Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
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06370590 |
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29-Oct-2012 |
Kim Phillips <kim.phillips@freescale.com> |
net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
9082eeac |
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07-Apr-2011 |
Andy Fleming <afleming@freescale.com> |
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de> |
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36af92ba |
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27-Nov-2022 |
Tom Rini <trini@konsulko.com> |
net: phy: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini <trini@konsulko.com> |
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5faf161d |
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23-Feb-2022 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: phy: atheros: avoid error in ar803x_of_init() when PHY has no OF node A DM_ETH driver may use phy_connect() towards a PHY address on an MDIO bus which is not specified in the device tree, as evidenced by: pfe_eth_probe -> pfe_phy_configure -> phy_connect When this happens, the PHY will have an invalid OF node. When ar803x_config() runs, it silently fails at ar803x_of_init(), and therefore, fails to run the rest of the initialization. This makes MII_BMCR contain what it had after BMCR_RESET (0x8000) has been written into it by phy_reset(). Since BMCR_RESET is volatile and self-clearing, the MII_BMCR ends up having a value of 0x0. The further configuration of this register, which is supposed to be handled by genphy_config_aneg() lower in ar803x_config(), never gets a chance to run due to this early error from ar803x_of_init(). As a result of having MII_BMCR as 0, the following symptom appears: => setenv ethact pfe_eth0 => setenv ipaddr 10.0.0.1 => ping 10.0.0.2 pfe_eth0 Waiting for PHY auto negotiation to complete......... TIMEOUT ! Could not initialize PHY pfe_eth0 Manually writing 0x1140 into register 0 of the PHY makes the connection work, but it is rather desirable that the port works without any manual intervention. Fixes: fe6293a80959 ("phy: atheros: add device tree bindings and config") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
338d9b03 |
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18-Jun-2020 |
Fabio Estevam <festevam@gmail.com> |
phy: atheros: ar8035: Fix clock output calculation The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel <o.rempel@pengutronix.de> Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8737c65f |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: consolidate {ar8031|ar8035}_config() The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6333cbb3 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
fe6293a8 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: add device tree bindings and config Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2b772155 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: move delay config to common function Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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f6ae47be |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: introduce debug read and write functions Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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30e31931 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: use defines for PHY IDs Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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f4d48f43 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: fix AR8021 PHY ID mask The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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4d4e4cf7 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the intention of ar8021_config Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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13114f38 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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a234ae86 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the configuration of the CLK_25M output pin Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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29602f9c |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Use common functions for RGMII internal delays Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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4346df33 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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05b60ac5 |
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24-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
net: phy: Clean up includes of common.h We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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1e2d2597 |
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13-Dec-2017 |
Zhao Qiang <qiang.zhao@nxp.com> |
phy: atheros: set auto-negotiation for AR8021 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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ce412b79 |
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13-Oct-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2ec4d10b |
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26-May-2016 |
Andrea Merello <andrea.merello@gmail.com> |
phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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903d384d |
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19-Feb-2016 |
Alison Wang <b18965@freescale.com> |
net: phy: atheros: Fix problem with phy_reset() clearing BMCR In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d584c68c |
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05-Jan-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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02aa4c53 |
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11-Apr-2014 |
Xiaobo Xie <X.Xie@freescale.com> |
AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
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08ad9b06 |
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20-Apr-2014 |
Zhao Qiang <B45475@freescale.com> |
ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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dc116bd6 |
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04-Mar-2014 |
Haijun.Zhang <Haijun.Zhang@freescale.com> |
net/phy: Correct AR8021 phy_mask There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> |
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a7e8c15f |
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24-Feb-2014 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
|
#
e0d80964 |
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23-Dec-2013 |
Zhao Qiang <B45475@freescale.com> |
ar8031/8033/phy:enable autonegotiation for ar8031/8033 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9137d19b |
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30-Jan-2014 |
Heiko Schocher <hs@denx.de> |
net, phy: atheros ar803x bug commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
f66e3ded |
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03-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix the masks for AR8031/8035 Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640 |
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e003ba5b |
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02-Nov-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix masks for AR8035 and AR8021 The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018 |
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31774578 |
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01-Nov-2013 |
Chunhe Lan <Chunhe.Lan@freescale.com> |
net/phy: Fix the phy id mask of AR8031 The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748 |
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dfcaa61c |
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22-Sep-2013 |
Heiko Schocher <hs@denx.de> |
net, phy: fix AR8031 phy_mask AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944 |
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626ee1e3 |
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08-Aug-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
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1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
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433a2c53 |
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04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
phylib: add atheros ar803x phy add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
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6027384a |
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10-Apr-2013 |
Xie Xiaobo <X.Xie@freescale.com> |
phylib: Add Atheros AR8035 GETH PHY support Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
#
06370590 |
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29-Oct-2012 |
Kim Phillips <kim.phillips@freescale.com> |
net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
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9082eeac |
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07-Apr-2011 |
Andy Fleming <afleming@freescale.com> |
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de> |
#
5faf161d |
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23-Feb-2022 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: phy: atheros: avoid error in ar803x_of_init() when PHY has no OF node A DM_ETH driver may use phy_connect() towards a PHY address on an MDIO bus which is not specified in the device tree, as evidenced by: pfe_eth_probe -> pfe_phy_configure -> phy_connect When this happens, the PHY will have an invalid OF node. When ar803x_config() runs, it silently fails at ar803x_of_init(), and therefore, fails to run the rest of the initialization. This makes MII_BMCR contain what it had after BMCR_RESET (0x8000) has been written into it by phy_reset(). Since BMCR_RESET is volatile and self-clearing, the MII_BMCR ends up having a value of 0x0. The further configuration of this register, which is supposed to be handled by genphy_config_aneg() lower in ar803x_config(), never gets a chance to run due to this early error from ar803x_of_init(). As a result of having MII_BMCR as 0, the following symptom appears: => setenv ethact pfe_eth0 => setenv ipaddr 10.0.0.1 => ping 10.0.0.2 pfe_eth0 Waiting for PHY auto negotiation to complete......... TIMEOUT ! Could not initialize PHY pfe_eth0 Manually writing 0x1140 into register 0 of the PHY makes the connection work, but it is rather desirable that the port works without any manual intervention. Fixes: fe6293a80959 ("phy: atheros: add device tree bindings and config") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
338d9b03 |
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18-Jun-2020 |
Fabio Estevam <festevam@gmail.com> |
phy: atheros: ar8035: Fix clock output calculation The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel <o.rempel@pengutronix.de> Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8737c65f |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: consolidate {ar8031|ar8035}_config() The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6333cbb3 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
fe6293a8 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: add device tree bindings and config Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2b772155 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: move delay config to common function Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
f6ae47be |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: introduce debug read and write functions Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
30e31931 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: use defines for PHY IDs Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
f4d48f43 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: fix AR8021 PHY ID mask The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
4d4e4cf7 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the intention of ar8021_config Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
13114f38 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
a234ae86 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the configuration of the CLK_25M output pin Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
29602f9c |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Use common functions for RGMII internal delays Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
4346df33 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
05b60ac5 |
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24-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
net: phy: Clean up includes of common.h We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
1e2d2597 |
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13-Dec-2017 |
Zhao Qiang <qiang.zhao@nxp.com> |
phy: atheros: set auto-negotiation for AR8021 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
ce412b79 |
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13-Oct-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2ec4d10b |
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26-May-2016 |
Andrea Merello <andrea.merello@gmail.com> |
phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
903d384d |
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19-Feb-2016 |
Alison Wang <b18965@freescale.com> |
net: phy: atheros: Fix problem with phy_reset() clearing BMCR In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d584c68c |
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05-Jan-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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02aa4c53 |
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11-Apr-2014 |
Xiaobo Xie <X.Xie@freescale.com> |
AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
#
08ad9b06 |
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20-Apr-2014 |
Zhao Qiang <B45475@freescale.com> |
ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
dc116bd6 |
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04-Mar-2014 |
Haijun.Zhang <Haijun.Zhang@freescale.com> |
net/phy: Correct AR8021 phy_mask There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> |
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a7e8c15f |
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24-Feb-2014 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
|
#
e0d80964 |
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23-Dec-2013 |
Zhao Qiang <B45475@freescale.com> |
ar8031/8033/phy:enable autonegotiation for ar8031/8033 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9137d19b |
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30-Jan-2014 |
Heiko Schocher <hs@denx.de> |
net, phy: atheros ar803x bug commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
f66e3ded |
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03-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix the masks for AR8031/8035 Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640 |
#
e003ba5b |
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02-Nov-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix masks for AR8035 and AR8021 The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018 |
#
31774578 |
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01-Nov-2013 |
Chunhe Lan <Chunhe.Lan@freescale.com> |
net/phy: Fix the phy id mask of AR8031 The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748 |
#
dfcaa61c |
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22-Sep-2013 |
Heiko Schocher <hs@denx.de> |
net, phy: fix AR8031 phy_mask AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944 |
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626ee1e3 |
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08-Aug-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
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1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
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433a2c53 |
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04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
phylib: add atheros ar803x phy add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
6027384a |
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10-Apr-2013 |
Xie Xiaobo <X.Xie@freescale.com> |
phylib: Add Atheros AR8035 GETH PHY support Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
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06370590 |
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29-Oct-2012 |
Kim Phillips <kim.phillips@freescale.com> |
net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
9082eeac |
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07-Apr-2011 |
Andy Fleming <afleming@freescale.com> |
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de> |
#
338d9b03 |
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18-Jun-2020 |
Fabio Estevam <festevam@gmail.com> |
phy: atheros: ar8035: Fix clock output calculation The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel <o.rempel@pengutronix.de> Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8737c65f |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: consolidate {ar8031|ar8035}_config() The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6333cbb3 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
fe6293a8 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: add device tree bindings and config Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2b772155 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: move delay config to common function Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
f6ae47be |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: introduce debug read and write functions Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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30e31931 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: use defines for PHY IDs Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
f4d48f43 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: fix AR8021 PHY ID mask The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
4d4e4cf7 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the intention of ar8021_config Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
13114f38 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
a234ae86 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the configuration of the CLK_25M output pin Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
29602f9c |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Use common functions for RGMII internal delays Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
4346df33 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
05b60ac5 |
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24-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
net: phy: Clean up includes of common.h We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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1e2d2597 |
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13-Dec-2017 |
Zhao Qiang <qiang.zhao@nxp.com> |
phy: atheros: set auto-negotiation for AR8021 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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ce412b79 |
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13-Oct-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2ec4d10b |
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26-May-2016 |
Andrea Merello <andrea.merello@gmail.com> |
phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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903d384d |
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19-Feb-2016 |
Alison Wang <b18965@freescale.com> |
net: phy: atheros: Fix problem with phy_reset() clearing BMCR In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d584c68c |
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05-Jan-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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02aa4c53 |
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11-Apr-2014 |
Xiaobo Xie <X.Xie@freescale.com> |
AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
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08ad9b06 |
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20-Apr-2014 |
Zhao Qiang <B45475@freescale.com> |
ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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dc116bd6 |
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04-Mar-2014 |
Haijun.Zhang <Haijun.Zhang@freescale.com> |
net/phy: Correct AR8021 phy_mask There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> |
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a7e8c15f |
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24-Feb-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
|
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e0d80964 |
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23-Dec-2013 |
Zhao Qiang <B45475@freescale.com> |
ar8031/8033/phy:enable autonegotiation for ar8031/8033 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9137d19b |
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30-Jan-2014 |
Heiko Schocher <hs@denx.de> |
net, phy: atheros ar803x bug commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
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f66e3ded |
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03-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix the masks for AR8031/8035 Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640 |
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e003ba5b |
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02-Nov-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix masks for AR8035 and AR8021 The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018 |
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31774578 |
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01-Nov-2013 |
Chunhe Lan <Chunhe.Lan@freescale.com> |
net/phy: Fix the phy id mask of AR8031 The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748 |
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dfcaa61c |
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22-Sep-2013 |
Heiko Schocher <hs@denx.de> |
net, phy: fix AR8031 phy_mask AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944 |
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626ee1e3 |
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08-Aug-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
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1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
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433a2c53 |
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04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
phylib: add atheros ar803x phy add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
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6027384a |
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10-Apr-2013 |
Xie Xiaobo <X.Xie@freescale.com> |
phylib: Add Atheros AR8035 GETH PHY support Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
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06370590 |
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29-Oct-2012 |
Kim Phillips <kim.phillips@freescale.com> |
net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
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9082eeac |
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07-Apr-2011 |
Andy Fleming <afleming@freescale.com> |
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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8737c65f |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: consolidate {ar8031|ar8035}_config() The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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6333cbb3 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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fe6293a8 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: add device tree bindings and config Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2b772155 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: move delay config to common function Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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f6ae47be |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: introduce debug read and write functions Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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30e31931 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: use defines for PHY IDs Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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f4d48f43 |
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06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: fix AR8021 PHY ID mask The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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4d4e4cf7 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the intention of ar8021_config Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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13114f38 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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a234ae86 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the configuration of the CLK_25M output pin Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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29602f9c |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Use common functions for RGMII internal delays Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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4346df33 |
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06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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05b60ac5 |
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24-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
net: phy: Clean up includes of common.h We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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1e2d2597 |
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13-Dec-2017 |
Zhao Qiang <qiang.zhao@nxp.com> |
phy: atheros: set auto-negotiation for AR8021 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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ce412b79 |
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13-Oct-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2ec4d10b |
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26-May-2016 |
Andrea Merello <andrea.merello@gmail.com> |
phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
903d384d |
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19-Feb-2016 |
Alison Wang <b18965@freescale.com> |
net: phy: atheros: Fix problem with phy_reset() clearing BMCR In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d584c68c |
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05-Jan-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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02aa4c53 |
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11-Apr-2014 |
Xiaobo Xie <X.Xie@freescale.com> |
AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
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08ad9b06 |
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20-Apr-2014 |
Zhao Qiang <B45475@freescale.com> |
ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
dc116bd6 |
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04-Mar-2014 |
Haijun.Zhang <Haijun.Zhang@freescale.com> |
net/phy: Correct AR8021 phy_mask There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> |
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a7e8c15f |
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24-Feb-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
|
#
e0d80964 |
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23-Dec-2013 |
Zhao Qiang <B45475@freescale.com> |
ar8031/8033/phy:enable autonegotiation for ar8031/8033 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9137d19b |
|
30-Jan-2014 |
Heiko Schocher <hs@denx.de> |
net, phy: atheros ar803x bug commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
f66e3ded |
|
03-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix the masks for AR8031/8035 Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640 |
#
e003ba5b |
|
02-Nov-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix masks for AR8035 and AR8021 The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018 |
#
31774578 |
|
01-Nov-2013 |
Chunhe Lan <Chunhe.Lan@freescale.com> |
net/phy: Fix the phy id mask of AR8031 The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748 |
#
dfcaa61c |
|
22-Sep-2013 |
Heiko Schocher <hs@denx.de> |
net, phy: fix AR8031 phy_mask AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944 |
#
626ee1e3 |
|
08-Aug-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
433a2c53 |
|
04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
phylib: add atheros ar803x phy add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
6027384a |
|
10-Apr-2013 |
Xie Xiaobo <X.Xie@freescale.com> |
phylib: Add Atheros AR8035 GETH PHY support Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
#
06370590 |
|
29-Oct-2012 |
Kim Phillips <kim.phillips@freescale.com> |
net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
9082eeac |
|
07-Apr-2011 |
Andy Fleming <afleming@freescale.com> |
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de> |
#
8737c65f |
|
06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: consolidate {ar8031|ar8035}_config() The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6333cbb3 |
|
06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
fe6293a8 |
|
06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: add device tree bindings and config Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2b772155 |
|
06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: move delay config to common function Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
f6ae47be |
|
06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: introduce debug read and write functions Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
30e31931 |
|
06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: use defines for PHY IDs Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
f4d48f43 |
|
06-May-2020 |
Michael Walle <michael@walle.cc> |
phy: atheros: fix AR8021 PHY ID mask The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
4d4e4cf7 |
|
06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the intention of ar8021_config Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
13114f38 |
|
06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
a234ae86 |
|
06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Clarify the configuration of the CLK_25M output pin Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
29602f9c |
|
06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Use common functions for RGMII internal delays Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
4346df33 |
|
06-May-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
phy: atheros: Make RGMII Tx delays actually configurable for AR8035 Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
05b60ac5 |
|
24-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
net: phy: Clean up includes of common.h We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
1e2d2597 |
|
13-Dec-2017 |
Zhao Qiang <qiang.zhao@nxp.com> |
phy: atheros: set auto-negotiation for AR8021 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
ce412b79 |
|
13-Oct-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2ec4d10b |
|
26-May-2016 |
Andrea Merello <andrea.merello@gmail.com> |
phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
903d384d |
|
19-Feb-2016 |
Alison Wang <b18965@freescale.com> |
net: phy: atheros: Fix problem with phy_reset() clearing BMCR In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d584c68c |
|
05-Jan-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
02aa4c53 |
|
11-Apr-2014 |
Xiaobo Xie <X.Xie@freescale.com> |
AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
#
08ad9b06 |
|
20-Apr-2014 |
Zhao Qiang <B45475@freescale.com> |
ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
dc116bd6 |
|
04-Mar-2014 |
Haijun.Zhang <Haijun.Zhang@freescale.com> |
net/phy: Correct AR8021 phy_mask There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> |
#
a7e8c15f |
|
24-Feb-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
|
#
e0d80964 |
|
23-Dec-2013 |
Zhao Qiang <B45475@freescale.com> |
ar8031/8033/phy:enable autonegotiation for ar8031/8033 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9137d19b |
|
30-Jan-2014 |
Heiko Schocher <hs@denx.de> |
net, phy: atheros ar803x bug commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
f66e3ded |
|
03-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix the masks for AR8031/8035 Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640 |
#
e003ba5b |
|
02-Nov-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix masks for AR8035 and AR8021 The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018 |
#
31774578 |
|
01-Nov-2013 |
Chunhe Lan <Chunhe.Lan@freescale.com> |
net/phy: Fix the phy id mask of AR8031 The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748 |
#
dfcaa61c |
|
22-Sep-2013 |
Heiko Schocher <hs@denx.de> |
net, phy: fix AR8031 phy_mask AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944 |
#
626ee1e3 |
|
08-Aug-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
433a2c53 |
|
04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
phylib: add atheros ar803x phy add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> |
#
6027384a |
|
10-Apr-2013 |
Xie Xiaobo <X.Xie@freescale.com> |
phylib: Add Atheros AR8035 GETH PHY support Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> |
#
06370590 |
|
29-Oct-2012 |
Kim Phillips <kim.phillips@freescale.com> |
net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
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9082eeac |
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07-Apr-2011 |
Andy Fleming <afleming@freescale.com> |
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de> |
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05b60ac5 |
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24-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
net: phy: Clean up includes of common.h We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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1e2d2597 |
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13-Dec-2017 |
Zhao Qiang <qiang.zhao@nxp.com> |
phy: atheros: set auto-negotiation for AR8021 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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ce412b79 |
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13-Oct-2016 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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2ec4d10b |
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26-May-2016 |
Andrea Merello <andrea.merello@gmail.com> |
phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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903d384d |
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19-Feb-2016 |
Alison Wang <b18965@freescale.com> |
net: phy: atheros: Fix problem with phy_reset() clearing BMCR In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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d584c68c |
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05-Jan-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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02aa4c53 |
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11-Apr-2014 |
Xiaobo Xie <X.Xie@freescale.com> |
AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
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08ad9b06 |
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20-Apr-2014 |
Zhao Qiang <B45475@freescale.com> |
ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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dc116bd6 |
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04-Mar-2014 |
Haijun.Zhang <Haijun.Zhang@freescale.com> |
net/phy: Correct AR8021 phy_mask There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
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e0d80964 |
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23-Dec-2013 |
Zhao Qiang <B45475@freescale.com> |
ar8031/8033/phy:enable autonegotiation for ar8031/8033 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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9137d19b |
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30-Jan-2014 |
Heiko Schocher <hs@denx.de> |
net, phy: atheros ar803x bug commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
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f66e3ded |
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03-Jan-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix the masks for AR8031/8035 Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640
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e003ba5b |
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02-Nov-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
net: phy: atheros: Fix masks for AR8035 and AR8021 The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018
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31774578 |
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01-Nov-2013 |
Chunhe Lan <Chunhe.Lan@freescale.com> |
net/phy: Fix the phy id mask of AR8031 The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748
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dfcaa61c |
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22-Sep-2013 |
Heiko Schocher <hs@denx.de> |
net, phy: fix AR8031 phy_mask AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944
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626ee1e3 |
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08-Aug-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
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433a2c53 |
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04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
phylib: add atheros ar803x phy add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
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6027384a |
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10-Apr-2013 |
Xie Xiaobo <X.Xie@freescale.com> |
phylib: Add Atheros AR8035 GETH PHY support Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
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06370590 |
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29-Oct-2012 |
Kim Phillips <kim.phillips@freescale.com> |
net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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#
9082eeac |
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07-Apr-2011 |
Andy Fleming <afleming@freescale.com> |
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
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