1179895Sdelphij// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2179895Sdelphij/* 3199553Syongari * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4179895Sdelphij * Author: Christophe Kerello <christophe.kerello@st.com> 5179895Sdelphij */ 6199553Syongari 7179895Sdelphij#include <common.h> 8179895Sdelphij#include <dm.h> 9179895Sdelphij#include <errno.h> 10199553Syongari#include <linux/delay.h> 11179895Sdelphij#include <power/pmic.h> 12179895Sdelphij#include <power/regulator.h> 13179895Sdelphij#include <power/stpmic1.h> 14179895Sdelphij 15179895Sdelphijstruct stpmic1_range { 16179895Sdelphij int min_uv; 17179895Sdelphij int min_sel; 18179895Sdelphij int max_sel; 19179895Sdelphij int step; 20199553Syongari}; 21179895Sdelphij 22179895Sdelphijstruct stpmic1_output { 23179895Sdelphij const struct stpmic1_range *ranges; 24179895Sdelphij int nbranges; 25179895Sdelphij}; 26179895Sdelphij 27179895Sdelphij#define STPMIC1_MODE(_id, _val, _name) { \ 28179895Sdelphij .id = _id, \ 29179895Sdelphij .register_value = _val, \ 30179895Sdelphij .name = _name, \ 31179895Sdelphij} 32179895Sdelphij 33199553Syongari#define STPMIC1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \ 34179895Sdelphij .min_uv = _min_uv, \ 35179895Sdelphij .min_sel = _min_sel, \ 36179895Sdelphij .max_sel = _max_sel, \ 37179895Sdelphij .step = _step, \ 38179895Sdelphij} 39179895Sdelphij 40179895Sdelphij#define STPMIC1_OUTPUT(_ranges, _nbranges) { \ 41179895Sdelphij .ranges = _ranges, \ 42179895Sdelphij .nbranges = _nbranges, \ 43199553Syongari} 44179895Sdelphij 45179895Sdelphijstatic int stpmic1_output_find_uv(int sel, 46179895Sdelphij const struct stpmic1_output *output) 47179895Sdelphij{ 48179895Sdelphij const struct stpmic1_range *range; 49179895Sdelphij int i; 50179895Sdelphij 51179895Sdelphij for (i = 0, range = output->ranges; 52179895Sdelphij i < output->nbranges; i++, range++) { 53179895Sdelphij if (sel >= range->min_sel && sel <= range->max_sel) 54179895Sdelphij return range->min_uv + 55179895Sdelphij (sel - range->min_sel) * range->step; 56179895Sdelphij } 57179895Sdelphij 58179895Sdelphij return -EINVAL; 59179895Sdelphij} 60179895Sdelphij 61179895Sdelphijstatic int stpmic1_output_find_sel(int uv, 62179895Sdelphij const struct stpmic1_output *output) 63179895Sdelphij{ 64179895Sdelphij const struct stpmic1_range *range; 65179895Sdelphij int i; 66179895Sdelphij 67179895Sdelphij for (i = 0, range = output->ranges; 68179895Sdelphij i < output->nbranges; i++, range++) { 69179895Sdelphij if (uv == range->min_uv && !range->step) 70179895Sdelphij return range->min_sel; 71179895Sdelphij 72179895Sdelphij if (uv >= range->min_uv && 73179895Sdelphij uv <= range->min_uv + 74179895Sdelphij (range->max_sel - range->min_sel) * range->step) 75179895Sdelphij return range->min_sel + 76179895Sdelphij (uv - range->min_uv) / range->step; 77179895Sdelphij } 78179895Sdelphij 79179895Sdelphij return -EINVAL; 80179895Sdelphij} 81179895Sdelphij 82179895Sdelphij/* 83179895Sdelphij * BUCK regulators 84179895Sdelphij */ 85179895Sdelphij 86179895Sdelphijstatic const struct stpmic1_range buck1_ranges[] = { 87179895Sdelphij STPMIC1_RANGE(725000, 0, 4, 0), 88179895Sdelphij STPMIC1_RANGE(725000, 5, 36, 25000), 89179895Sdelphij STPMIC1_RANGE(1500000, 37, 63, 0), 90179895Sdelphij}; 91179895Sdelphij 92179895Sdelphijstatic const struct stpmic1_range buck2_ranges[] = { 93179895Sdelphij STPMIC1_RANGE(1000000, 0, 17, 0), 94179895Sdelphij STPMIC1_RANGE(1050000, 18, 19, 0), 95179895Sdelphij STPMIC1_RANGE(1100000, 20, 21, 0), 96179895Sdelphij STPMIC1_RANGE(1150000, 22, 23, 0), 97179895Sdelphij STPMIC1_RANGE(1200000, 24, 25, 0), 98179895Sdelphij STPMIC1_RANGE(1250000, 26, 27, 0), 99179895Sdelphij STPMIC1_RANGE(1300000, 28, 29, 0), 100179895Sdelphij STPMIC1_RANGE(1350000, 30, 31, 0), 101179895Sdelphij STPMIC1_RANGE(1400000, 32, 33, 0), 102179895Sdelphij STPMIC1_RANGE(1450000, 34, 35, 0), 103179895Sdelphij STPMIC1_RANGE(1500000, 36, 63, 0), 104179895Sdelphij}; 105179895Sdelphij 106179895Sdelphijstatic const struct stpmic1_range buck3_ranges[] = { 107179895Sdelphij STPMIC1_RANGE(1000000, 0, 19, 0), 108179895Sdelphij STPMIC1_RANGE(1100000, 20, 23, 0), 109199548Syongari STPMIC1_RANGE(1200000, 24, 27, 0), 110179895Sdelphij STPMIC1_RANGE(1300000, 28, 31, 0), 111199548Syongari STPMIC1_RANGE(1400000, 32, 35, 0), 112199548Syongari STPMIC1_RANGE(1500000, 36, 55, 100000), 113199548Syongari STPMIC1_RANGE(3400000, 56, 63, 0), 114179895Sdelphij}; 115179895Sdelphij 116179895Sdelphijstatic const struct stpmic1_range buck4_ranges[] = { 117179895Sdelphij STPMIC1_RANGE(600000, 0, 27, 25000), 118179895Sdelphij STPMIC1_RANGE(1300000, 28, 29, 0), 119179895Sdelphij STPMIC1_RANGE(1350000, 30, 31, 0), 120179895Sdelphij STPMIC1_RANGE(1400000, 32, 33, 0), 121199548Syongari STPMIC1_RANGE(1450000, 34, 35, 0), 122179895Sdelphij STPMIC1_RANGE(1500000, 36, 60, 100000), 123179895Sdelphij STPMIC1_RANGE(3900000, 61, 63, 0), 124179895Sdelphij}; 125179895Sdelphij 126179895Sdelphij/* BUCK: 1,2,3,4 - voltage ranges */ 127179895Sdelphijstatic const struct stpmic1_output buck_voltage_range[] = { 128199548Syongari STPMIC1_OUTPUT(buck1_ranges, ARRAY_SIZE(buck1_ranges)), 129199548Syongari STPMIC1_OUTPUT(buck2_ranges, ARRAY_SIZE(buck2_ranges)), 130199548Syongari STPMIC1_OUTPUT(buck3_ranges, ARRAY_SIZE(buck3_ranges)), 131199548Syongari STPMIC1_OUTPUT(buck4_ranges, ARRAY_SIZE(buck4_ranges)), 132199548Syongari}; 133199548Syongari 134179895Sdelphij/* BUCK modes */ 135179895Sdelphijstatic const struct dm_regulator_mode buck_modes[] = { 136179895Sdelphij STPMIC1_MODE(STPMIC1_PREG_MODE_HP, STPMIC1_PREG_MODE_HP, "HP"), 137179895Sdelphij STPMIC1_MODE(STPMIC1_PREG_MODE_LP, STPMIC1_PREG_MODE_LP, "LP"), 138179895Sdelphij}; 139179895Sdelphij 140199548Syongaristatic int stpmic1_buck_get_uv(struct udevice *dev, int buck) 141199548Syongari{ 142199548Syongari int sel; 143179895Sdelphij 144179895Sdelphij sel = pmic_reg_read(dev, STPMIC1_BUCKX_MAIN_CR(buck)); 145179895Sdelphij if (sel < 0) 146179895Sdelphij return sel; 147179895Sdelphij 148179895Sdelphij sel &= STPMIC1_BUCK_VOUT_MASK; 149179895Sdelphij sel >>= STPMIC1_BUCK_VOUT_SHIFT; 150179895Sdelphij 151179895Sdelphij return stpmic1_output_find_uv(sel, &buck_voltage_range[buck]); 152179895Sdelphij} 153179895Sdelphij 154179895Sdelphijstatic int stpmic1_buck_get_value(struct udevice *dev) 155179895Sdelphij{ 156179895Sdelphij return stpmic1_buck_get_uv(dev->parent, dev->driver_data - 1); 157179895Sdelphij} 158179895Sdelphij 159179895Sdelphijstatic int stpmic1_buck_set_value(struct udevice *dev, int uv) 160179895Sdelphij{ 161179895Sdelphij int sel, buck = dev->driver_data - 1; 162179895Sdelphij 163179895Sdelphij sel = stpmic1_output_find_sel(uv, &buck_voltage_range[buck]); 164179895Sdelphij if (sel < 0) 165179895Sdelphij return sel; 166179895Sdelphij 167179895Sdelphij return pmic_clrsetbits(dev->parent, 168179895Sdelphij STPMIC1_BUCKX_MAIN_CR(buck), 169179895Sdelphij STPMIC1_BUCK_VOUT_MASK, 170179895Sdelphij sel << STPMIC1_BUCK_VOUT_SHIFT); 171179895Sdelphij} 172179895Sdelphij 173179895Sdelphijstatic int stpmic1_buck_get_enable(struct udevice *dev) 174179895Sdelphij{ 175179895Sdelphij int ret; 176179895Sdelphij 177179895Sdelphij ret = pmic_reg_read(dev->parent, 178179895Sdelphij STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1)); 179179895Sdelphij if (ret < 0) 180179895Sdelphij return false; 181179895Sdelphij 182179895Sdelphij return ret & STPMIC1_BUCK_ENA ? true : false; 183179895Sdelphij} 184179895Sdelphij 185179895Sdelphijstatic int stpmic1_buck_set_enable(struct udevice *dev, bool enable) 186179895Sdelphij{ 187179895Sdelphij struct dm_regulator_uclass_plat *uc_pdata; 188179895Sdelphij int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS : 189179895Sdelphij STPMIC1_DEFAULT_STOP_DELAY_MS; 190179895Sdelphij int ret, uv; 191179895Sdelphij 192179895Sdelphij /* if regulator is already in the wanted state, nothing to do */ 193179895Sdelphij if (stpmic1_buck_get_enable(dev) == enable) 194179895Sdelphij return 0; 195179895Sdelphij 196179895Sdelphij if (enable) { 197179895Sdelphij uc_pdata = dev_get_uclass_plat(dev); 198179895Sdelphij uv = stpmic1_buck_get_value(dev); 199179895Sdelphij if (uv < uc_pdata->min_uV || uv > uc_pdata->max_uV) 200179895Sdelphij stpmic1_buck_set_value(dev, uc_pdata->min_uV); 201179895Sdelphij } 202179895Sdelphij 203179895Sdelphij ret = pmic_clrsetbits(dev->parent, 204179895Sdelphij STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1), 205179895Sdelphij STPMIC1_BUCK_ENA, enable ? STPMIC1_BUCK_ENA : 0); 206179895Sdelphij mdelay(delay); 207179895Sdelphij 208179895Sdelphij return ret; 209179895Sdelphij} 210179895Sdelphij 211179895Sdelphijstatic int stpmic1_buck_get_mode(struct udevice *dev) 212179895Sdelphij{ 213179895Sdelphij int ret; 214179895Sdelphij 215179895Sdelphij ret = pmic_reg_read(dev->parent, 216179895Sdelphij STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1)); 217179895Sdelphij if (ret < 0) 218179895Sdelphij return ret; 219179895Sdelphij 220179895Sdelphij return ret & STPMIC1_BUCK_PREG_MODE ? STPMIC1_PREG_MODE_LP : 221179895Sdelphij STPMIC1_PREG_MODE_HP; 222179895Sdelphij} 223179895Sdelphij 224179895Sdelphijstatic int stpmic1_buck_set_mode(struct udevice *dev, int mode) 225179895Sdelphij{ 226179895Sdelphij return pmic_clrsetbits(dev->parent, 227179895Sdelphij STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1), 228179895Sdelphij STPMIC1_BUCK_PREG_MODE, 229179895Sdelphij mode ? STPMIC1_BUCK_PREG_MODE : 0); 230179895Sdelphij} 231179895Sdelphij 232179895Sdelphijstatic int stpmic1_buck_probe(struct udevice *dev) 233179895Sdelphij{ 234179895Sdelphij struct dm_regulator_uclass_plat *uc_pdata; 235179895Sdelphij 236179895Sdelphij if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_BUCK) 237179895Sdelphij return -EINVAL; 238179895Sdelphij 239179895Sdelphij uc_pdata = dev_get_uclass_plat(dev); 240179895Sdelphij 241199552Syongari uc_pdata->type = REGULATOR_TYPE_BUCK; 242179895Sdelphij uc_pdata->mode = (struct dm_regulator_mode *)buck_modes; 243179895Sdelphij uc_pdata->mode_count = ARRAY_SIZE(buck_modes); 244179895Sdelphij 245179895Sdelphij return 0; 246179895Sdelphij} 247179895Sdelphij 248179895Sdelphijstatic const struct dm_regulator_ops stpmic1_buck_ops = { 249179895Sdelphij .get_value = stpmic1_buck_get_value, 250179895Sdelphij .set_value = stpmic1_buck_set_value, 251179895Sdelphij .get_enable = stpmic1_buck_get_enable, 252179895Sdelphij .set_enable = stpmic1_buck_set_enable, 253179895Sdelphij .get_mode = stpmic1_buck_get_mode, 254179895Sdelphij .set_mode = stpmic1_buck_set_mode, 255179895Sdelphij}; 256179895Sdelphij 257179895SdelphijU_BOOT_DRIVER(stpmic1_buck) = { 258179895Sdelphij .name = "stpmic1_buck", 259179895Sdelphij .id = UCLASS_REGULATOR, 260179895Sdelphij .ops = &stpmic1_buck_ops, 261179895Sdelphij .probe = stpmic1_buck_probe, 262179895Sdelphij}; 263179895Sdelphij 264179895Sdelphij/* 265179895Sdelphij * LDO regulators 266179895Sdelphij */ 267179895Sdelphij 268179895Sdelphijstatic const struct stpmic1_range ldo12_ranges[] = { 269179895Sdelphij STPMIC1_RANGE(1700000, 0, 7, 0), 270179895Sdelphij STPMIC1_RANGE(1700000, 8, 24, 100000), 271179895Sdelphij STPMIC1_RANGE(3300000, 25, 31, 0), 272179895Sdelphij}; 273179895Sdelphij 274179895Sdelphijstatic const struct stpmic1_range ldo3_ranges[] = { 275179895Sdelphij STPMIC1_RANGE(1700000, 0, 7, 0), 276179895Sdelphij STPMIC1_RANGE(1700000, 8, 24, 100000), 277179895Sdelphij STPMIC1_RANGE(3300000, 25, 30, 0), 278179895Sdelphij /* Sel 31 is special case when LDO3 is in mode sync_source (BUCK2/2) */ 279179895Sdelphij}; 280179895Sdelphij 281199552Syongaristatic const struct stpmic1_range ldo5_ranges[] = { 282199552Syongari STPMIC1_RANGE(1700000, 0, 7, 0), 283199552Syongari STPMIC1_RANGE(1700000, 8, 30, 100000), 284199552Syongari STPMIC1_RANGE(3900000, 31, 31, 0), 285179895Sdelphij}; 286179895Sdelphij 287static const struct stpmic1_range ldo6_ranges[] = { 288 STPMIC1_RANGE(900000, 0, 24, 100000), 289 STPMIC1_RANGE(3300000, 25, 31, 0), 290}; 291 292/* LDO: 1,2,3,4,5,6 - voltage ranges */ 293static const struct stpmic1_output ldo_voltage_range[] = { 294 STPMIC1_OUTPUT(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)), 295 STPMIC1_OUTPUT(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)), 296 STPMIC1_OUTPUT(ldo3_ranges, ARRAY_SIZE(ldo3_ranges)), 297 STPMIC1_OUTPUT(NULL, 0), 298 STPMIC1_OUTPUT(ldo5_ranges, ARRAY_SIZE(ldo5_ranges)), 299 STPMIC1_OUTPUT(ldo6_ranges, ARRAY_SIZE(ldo6_ranges)), 300}; 301 302/* LDO modes */ 303static const struct dm_regulator_mode ldo_modes[] = { 304 STPMIC1_MODE(STPMIC1_LDO_MODE_NORMAL, 305 STPMIC1_LDO_MODE_NORMAL, "NORMAL"), 306 STPMIC1_MODE(STPMIC1_LDO_MODE_BYPASS, 307 STPMIC1_LDO_MODE_BYPASS, "BYPASS"), 308 STPMIC1_MODE(STPMIC1_LDO_MODE_SINK_SOURCE, 309 STPMIC1_LDO_MODE_SINK_SOURCE, "SINK SOURCE"), 310}; 311 312static int stpmic1_ldo_get_value(struct udevice *dev) 313{ 314 int sel, ldo = dev->driver_data - 1; 315 316 sel = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo)); 317 if (sel < 0) 318 return sel; 319 320 /* ldo4 => 3,3V */ 321 if (ldo == STPMIC1_LDO4) 322 return STPMIC1_LDO4_UV; 323 324 sel &= STPMIC1_LDO12356_VOUT_MASK; 325 sel >>= STPMIC1_LDO12356_VOUT_SHIFT; 326 327 /* ldo3, sel = 31 => BUCK2/2 */ 328 if (ldo == STPMIC1_LDO3 && sel == STPMIC1_LDO3_DDR_SEL) 329 return stpmic1_buck_get_uv(dev->parent, STPMIC1_BUCK2) / 2; 330 331 return stpmic1_output_find_uv(sel, &ldo_voltage_range[ldo]); 332} 333 334static int stpmic1_ldo_set_value(struct udevice *dev, int uv) 335{ 336 int sel, ldo = dev->driver_data - 1; 337 338 /* ldo4 => not possible */ 339 if (ldo == STPMIC1_LDO4) 340 return -EINVAL; 341 342 sel = stpmic1_output_find_sel(uv, &ldo_voltage_range[ldo]); 343 if (sel < 0) 344 return sel; 345 346 return pmic_clrsetbits(dev->parent, 347 STPMIC1_LDOX_MAIN_CR(ldo), 348 STPMIC1_LDO12356_VOUT_MASK, 349 sel << STPMIC1_LDO12356_VOUT_SHIFT); 350} 351 352static int stpmic1_ldo_get_enable(struct udevice *dev) 353{ 354 int ret; 355 356 ret = pmic_reg_read(dev->parent, 357 STPMIC1_LDOX_MAIN_CR(dev->driver_data - 1)); 358 if (ret < 0) 359 return false; 360 361 return ret & STPMIC1_LDO_ENA ? true : false; 362} 363 364static int stpmic1_ldo_set_enable(struct udevice *dev, bool enable) 365{ 366 struct dm_regulator_uclass_plat *uc_pdata; 367 int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS : 368 STPMIC1_DEFAULT_STOP_DELAY_MS; 369 int ret, uv; 370 371 /* if regulator is already in the wanted state, nothing to do */ 372 if (stpmic1_ldo_get_enable(dev) == enable) 373 return 0; 374 375 if (enable) { 376 uc_pdata = dev_get_uclass_plat(dev); 377 uv = stpmic1_ldo_get_value(dev); 378 if (uv < uc_pdata->min_uV || uv > uc_pdata->max_uV) 379 stpmic1_ldo_set_value(dev, uc_pdata->min_uV); 380 } 381 382 ret = pmic_clrsetbits(dev->parent, 383 STPMIC1_LDOX_MAIN_CR(dev->driver_data - 1), 384 STPMIC1_LDO_ENA, enable ? STPMIC1_LDO_ENA : 0); 385 mdelay(delay); 386 387 return ret; 388} 389 390static int stpmic1_ldo_get_mode(struct udevice *dev) 391{ 392 int ret, ldo = dev->driver_data - 1; 393 394 if (ldo != STPMIC1_LDO3) 395 return -EINVAL; 396 397 ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo)); 398 if (ret < 0) 399 return ret; 400 401 if (ret & STPMIC1_LDO3_MODE) 402 return STPMIC1_LDO_MODE_BYPASS; 403 404 ret &= STPMIC1_LDO12356_VOUT_MASK; 405 ret >>= STPMIC1_LDO12356_VOUT_SHIFT; 406 407 return ret == STPMIC1_LDO3_DDR_SEL ? STPMIC1_LDO_MODE_SINK_SOURCE : 408 STPMIC1_LDO_MODE_NORMAL; 409} 410 411static int stpmic1_ldo_set_mode(struct udevice *dev, int mode) 412{ 413 int ret, ldo = dev->driver_data - 1; 414 415 if (ldo != STPMIC1_LDO3) 416 return -EINVAL; 417 418 ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo)); 419 if (ret < 0) 420 return ret; 421 422 switch (mode) { 423 case STPMIC1_LDO_MODE_SINK_SOURCE: 424 ret &= ~STPMIC1_LDO12356_VOUT_MASK; 425 ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_VOUT_SHIFT; 426 /* fallthrough */ 427 case STPMIC1_LDO_MODE_NORMAL: 428 ret &= ~STPMIC1_LDO3_MODE; 429 break; 430 case STPMIC1_LDO_MODE_BYPASS: 431 ret |= STPMIC1_LDO3_MODE; 432 break; 433 } 434 435 return pmic_reg_write(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo), ret); 436} 437 438static int stpmic1_ldo_probe(struct udevice *dev) 439{ 440 struct dm_regulator_uclass_plat *uc_pdata; 441 442 if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_LDO) 443 return -EINVAL; 444 445 uc_pdata = dev_get_uclass_plat(dev); 446 447 uc_pdata->type = REGULATOR_TYPE_LDO; 448 if (dev->driver_data - 1 == STPMIC1_LDO3) { 449 uc_pdata->mode = (struct dm_regulator_mode *)ldo_modes; 450 uc_pdata->mode_count = ARRAY_SIZE(ldo_modes); 451 } else { 452 uc_pdata->mode_count = 0; 453 } 454 455 return 0; 456} 457 458static const struct dm_regulator_ops stpmic1_ldo_ops = { 459 .get_value = stpmic1_ldo_get_value, 460 .set_value = stpmic1_ldo_set_value, 461 .get_enable = stpmic1_ldo_get_enable, 462 .set_enable = stpmic1_ldo_set_enable, 463 .get_mode = stpmic1_ldo_get_mode, 464 .set_mode = stpmic1_ldo_set_mode, 465}; 466 467U_BOOT_DRIVER(stpmic1_ldo) = { 468 .name = "stpmic1_ldo", 469 .id = UCLASS_REGULATOR, 470 .ops = &stpmic1_ldo_ops, 471 .probe = stpmic1_ldo_probe, 472}; 473 474/* 475 * VREF DDR regulator 476 */ 477 478static int stpmic1_vref_ddr_get_value(struct udevice *dev) 479{ 480 /* BUCK2/2 */ 481 return stpmic1_buck_get_uv(dev->parent, STPMIC1_BUCK2) / 2; 482} 483 484static int stpmic1_vref_ddr_get_enable(struct udevice *dev) 485{ 486 int ret; 487 488 ret = pmic_reg_read(dev->parent, STPMIC1_REFDDR_MAIN_CR); 489 if (ret < 0) 490 return false; 491 492 return ret & STPMIC1_VREF_ENA ? true : false; 493} 494 495static int stpmic1_vref_ddr_set_enable(struct udevice *dev, bool enable) 496{ 497 int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS : 498 STPMIC1_DEFAULT_STOP_DELAY_MS; 499 int ret; 500 501 /* if regulator is already in the wanted state, nothing to do */ 502 if (stpmic1_vref_ddr_get_enable(dev) == enable) 503 return 0; 504 505 ret = pmic_clrsetbits(dev->parent, STPMIC1_REFDDR_MAIN_CR, 506 STPMIC1_VREF_ENA, enable ? STPMIC1_VREF_ENA : 0); 507 mdelay(delay); 508 509 return ret; 510} 511 512static int stpmic1_vref_ddr_probe(struct udevice *dev) 513{ 514 struct dm_regulator_uclass_plat *uc_pdata; 515 516 uc_pdata = dev_get_uclass_plat(dev); 517 518 uc_pdata->type = REGULATOR_TYPE_FIXED; 519 uc_pdata->mode_count = 0; 520 521 return 0; 522} 523 524static const struct dm_regulator_ops stpmic1_vref_ddr_ops = { 525 .get_value = stpmic1_vref_ddr_get_value, 526 .get_enable = stpmic1_vref_ddr_get_enable, 527 .set_enable = stpmic1_vref_ddr_set_enable, 528}; 529 530U_BOOT_DRIVER(stpmic1_vref_ddr) = { 531 .name = "stpmic1_vref_ddr", 532 .id = UCLASS_REGULATOR, 533 .ops = &stpmic1_vref_ddr_ops, 534 .probe = stpmic1_vref_ddr_probe, 535}; 536 537/* 538 * BOOST regulator 539 */ 540 541static int stpmic1_boost_get_enable(struct udevice *dev) 542{ 543 int ret; 544 545 ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR); 546 if (ret < 0) 547 return false; 548 549 return ret & STPMIC1_BST_ON ? true : false; 550} 551 552static int stpmic1_boost_set_enable(struct udevice *dev, bool enable) 553{ 554 int ret; 555 556 ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR); 557 if (ret < 0) 558 return ret; 559 560 if (!enable && ret & STPMIC1_PWR_SW_ON) 561 return -EINVAL; 562 563 /* if regulator is already in the wanted state, nothing to do */ 564 if (!!(ret & STPMIC1_BST_ON) == enable) 565 return 0; 566 567 ret = pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR, 568 STPMIC1_BST_ON, 569 enable ? STPMIC1_BST_ON : 0); 570 if (enable) 571 mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS); 572 573 return ret; 574} 575 576static int stpmic1_boost_probe(struct udevice *dev) 577{ 578 struct dm_regulator_uclass_plat *uc_pdata; 579 580 uc_pdata = dev_get_uclass_plat(dev); 581 582 uc_pdata->type = REGULATOR_TYPE_FIXED; 583 uc_pdata->mode_count = 0; 584 585 return 0; 586} 587 588static const struct dm_regulator_ops stpmic1_boost_ops = { 589 .get_enable = stpmic1_boost_get_enable, 590 .set_enable = stpmic1_boost_set_enable, 591}; 592 593U_BOOT_DRIVER(stpmic1_boost) = { 594 .name = "stpmic1_boost", 595 .id = UCLASS_REGULATOR, 596 .ops = &stpmic1_boost_ops, 597 .probe = stpmic1_boost_probe, 598}; 599 600/* 601 * USB power switch 602 */ 603 604static int stpmic1_pwr_sw_get_enable(struct udevice *dev) 605{ 606 uint mask = 1 << dev->driver_data; 607 int ret; 608 609 ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR); 610 if (ret < 0) 611 return false; 612 613 return ret & mask ? true : false; 614} 615 616static int stpmic1_pwr_sw_set_enable(struct udevice *dev, bool enable) 617{ 618 uint mask = 1 << dev->driver_data; 619 int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS : 620 STPMIC1_DEFAULT_STOP_DELAY_MS; 621 int ret; 622 623 ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR); 624 if (ret < 0) 625 return ret; 626 627 /* if regulator is already in the wanted state, nothing to do */ 628 if (!!(ret & mask) == enable) 629 return 0; 630 631 /* Boost management */ 632 if (enable && !(ret & STPMIC1_BST_ON)) { 633 pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR, 634 STPMIC1_BST_ON, STPMIC1_BST_ON); 635 mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS); 636 } else if (!enable && ret & STPMIC1_BST_ON && 637 (ret & STPMIC1_PWR_SW_ON) != STPMIC1_PWR_SW_ON) { 638 pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR, 639 STPMIC1_BST_ON, 0); 640 } 641 642 ret = pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR, 643 mask, enable ? mask : 0); 644 mdelay(delay); 645 646 return ret; 647} 648 649static int stpmic1_pwr_sw_probe(struct udevice *dev) 650{ 651 struct dm_regulator_uclass_plat *uc_pdata; 652 653 if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_PWR_SW) 654 return -EINVAL; 655 656 uc_pdata = dev_get_uclass_plat(dev); 657 658 uc_pdata->type = REGULATOR_TYPE_FIXED; 659 uc_pdata->mode_count = 0; 660 661 return 0; 662} 663 664static const struct dm_regulator_ops stpmic1_pwr_sw_ops = { 665 .get_enable = stpmic1_pwr_sw_get_enable, 666 .set_enable = stpmic1_pwr_sw_set_enable, 667}; 668 669U_BOOT_DRIVER(stpmic1_pwr_sw) = { 670 .name = "stpmic1_pwr_sw", 671 .id = UCLASS_REGULATOR, 672 .ops = &stpmic1_pwr_sw_ops, 673 .probe = stpmic1_pwr_sw_probe, 674}; 675