1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 * Author: Christophe Kerello <christophe.kerello@st.com> 5 */ 6 7#include <common.h> 8#include <dm.h> 9#include <errno.h> 10#include <linux/delay.h> 11#include <power/pmic.h> 12#include <power/regulator.h> 13#include <power/stpmic1.h> 14 15struct stpmic1_range { 16 int min_uv; 17 int min_sel; 18 int max_sel; 19 int step; 20}; 21 22struct stpmic1_output { 23 const struct stpmic1_range *ranges; 24 int nbranges; 25}; 26 27#define STPMIC1_MODE(_id, _val, _name) { \ 28 .id = _id, \ 29 .register_value = _val, \ 30 .name = _name, \ 31} 32 33#define STPMIC1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \ 34 .min_uv = _min_uv, \ 35 .min_sel = _min_sel, \ 36 .max_sel = _max_sel, \ 37 .step = _step, \ 38} 39 40#define STPMIC1_OUTPUT(_ranges, _nbranges) { \ 41 .ranges = _ranges, \ 42 .nbranges = _nbranges, \ 43} 44 45static int stpmic1_output_find_uv(int sel, 46 const struct stpmic1_output *output) 47{ 48 const struct stpmic1_range *range; 49 int i; 50 51 for (i = 0, range = output->ranges; 52 i < output->nbranges; i++, range++) { 53 if (sel >= range->min_sel && sel <= range->max_sel) 54 return range->min_uv + 55 (sel - range->min_sel) * range->step; 56 } 57 58 return -EINVAL; 59} 60 61static int stpmic1_output_find_sel(int uv, 62 const struct stpmic1_output *output) 63{ 64 const struct stpmic1_range *range; 65 int i; 66 67 for (i = 0, range = output->ranges; 68 i < output->nbranges; i++, range++) { 69 if (uv == range->min_uv && !range->step) 70 return range->min_sel; 71 72 if (uv >= range->min_uv && 73 uv <= range->min_uv + 74 (range->max_sel - range->min_sel) * range->step) 75 return range->min_sel + 76 (uv - range->min_uv) / range->step; 77 } 78 79 return -EINVAL; 80} 81 82/* 83 * BUCK regulators 84 */ 85 86static const struct stpmic1_range buck1_ranges[] = { 87 STPMIC1_RANGE(725000, 0, 4, 0), 88 STPMIC1_RANGE(725000, 5, 36, 25000), 89 STPMIC1_RANGE(1500000, 37, 63, 0), 90}; 91 92static const struct stpmic1_range buck2_ranges[] = { 93 STPMIC1_RANGE(1000000, 0, 17, 0), 94 STPMIC1_RANGE(1050000, 18, 19, 0), 95 STPMIC1_RANGE(1100000, 20, 21, 0), 96 STPMIC1_RANGE(1150000, 22, 23, 0), 97 STPMIC1_RANGE(1200000, 24, 25, 0), 98 STPMIC1_RANGE(1250000, 26, 27, 0), 99 STPMIC1_RANGE(1300000, 28, 29, 0), 100 STPMIC1_RANGE(1350000, 30, 31, 0), 101 STPMIC1_RANGE(1400000, 32, 33, 0), 102 STPMIC1_RANGE(1450000, 34, 35, 0), 103 STPMIC1_RANGE(1500000, 36, 63, 0), 104}; 105 106static const struct stpmic1_range buck3_ranges[] = { 107 STPMIC1_RANGE(1000000, 0, 19, 0), 108 STPMIC1_RANGE(1100000, 20, 23, 0), 109 STPMIC1_RANGE(1200000, 24, 27, 0), 110 STPMIC1_RANGE(1300000, 28, 31, 0), 111 STPMIC1_RANGE(1400000, 32, 35, 0), 112 STPMIC1_RANGE(1500000, 36, 55, 100000), 113 STPMIC1_RANGE(3400000, 56, 63, 0), 114}; 115 116static const struct stpmic1_range buck4_ranges[] = { 117 STPMIC1_RANGE(600000, 0, 27, 25000), 118 STPMIC1_RANGE(1300000, 28, 29, 0), 119 STPMIC1_RANGE(1350000, 30, 31, 0), 120 STPMIC1_RANGE(1400000, 32, 33, 0), 121 STPMIC1_RANGE(1450000, 34, 35, 0), 122 STPMIC1_RANGE(1500000, 36, 60, 100000), 123 STPMIC1_RANGE(3900000, 61, 63, 0), 124}; 125 126/* BUCK: 1,2,3,4 - voltage ranges */ 127static const struct stpmic1_output buck_voltage_range[] = { 128 STPMIC1_OUTPUT(buck1_ranges, ARRAY_SIZE(buck1_ranges)), 129 STPMIC1_OUTPUT(buck2_ranges, ARRAY_SIZE(buck2_ranges)), 130 STPMIC1_OUTPUT(buck3_ranges, ARRAY_SIZE(buck3_ranges)), 131 STPMIC1_OUTPUT(buck4_ranges, ARRAY_SIZE(buck4_ranges)), 132}; 133 134/* BUCK modes */ 135static const struct dm_regulator_mode buck_modes[] = { 136 STPMIC1_MODE(STPMIC1_PREG_MODE_HP, STPMIC1_PREG_MODE_HP, "HP"), 137 STPMIC1_MODE(STPMIC1_PREG_MODE_LP, STPMIC1_PREG_MODE_LP, "LP"), 138}; 139 140static int stpmic1_buck_get_uv(struct udevice *dev, int buck) 141{ 142 int sel; 143 144 sel = pmic_reg_read(dev, STPMIC1_BUCKX_MAIN_CR(buck)); 145 if (sel < 0) 146 return sel; 147 148 sel &= STPMIC1_BUCK_VOUT_MASK; 149 sel >>= STPMIC1_BUCK_VOUT_SHIFT; 150 151 return stpmic1_output_find_uv(sel, &buck_voltage_range[buck]); 152} 153 154static int stpmic1_buck_get_value(struct udevice *dev) 155{ 156 return stpmic1_buck_get_uv(dev->parent, dev->driver_data - 1); 157} 158 159static int stpmic1_buck_set_value(struct udevice *dev, int uv) 160{ 161 int sel, buck = dev->driver_data - 1; 162 163 sel = stpmic1_output_find_sel(uv, &buck_voltage_range[buck]); 164 if (sel < 0) 165 return sel; 166 167 return pmic_clrsetbits(dev->parent, 168 STPMIC1_BUCKX_MAIN_CR(buck), 169 STPMIC1_BUCK_VOUT_MASK, 170 sel << STPMIC1_BUCK_VOUT_SHIFT); 171} 172 173static int stpmic1_buck_get_enable(struct udevice *dev) 174{ 175 int ret; 176 177 ret = pmic_reg_read(dev->parent, 178 STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1)); 179 if (ret < 0) 180 return false; 181 182 return ret & STPMIC1_BUCK_ENA ? true : false; 183} 184 185static int stpmic1_buck_set_enable(struct udevice *dev, bool enable) 186{ 187 struct dm_regulator_uclass_plat *uc_pdata; 188 int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS : 189 STPMIC1_DEFAULT_STOP_DELAY_MS; 190 int ret, uv; 191 192 /* if regulator is already in the wanted state, nothing to do */ 193 if (stpmic1_buck_get_enable(dev) == enable) 194 return 0; 195 196 if (enable) { 197 uc_pdata = dev_get_uclass_plat(dev); 198 uv = stpmic1_buck_get_value(dev); 199 if (uv < uc_pdata->min_uV || uv > uc_pdata->max_uV) 200 stpmic1_buck_set_value(dev, uc_pdata->min_uV); 201 } 202 203 ret = pmic_clrsetbits(dev->parent, 204 STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1), 205 STPMIC1_BUCK_ENA, enable ? STPMIC1_BUCK_ENA : 0); 206 mdelay(delay); 207 208 return ret; 209} 210 211static int stpmic1_buck_get_mode(struct udevice *dev) 212{ 213 int ret; 214 215 ret = pmic_reg_read(dev->parent, 216 STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1)); 217 if (ret < 0) 218 return ret; 219 220 return ret & STPMIC1_BUCK_PREG_MODE ? STPMIC1_PREG_MODE_LP : 221 STPMIC1_PREG_MODE_HP; 222} 223 224static int stpmic1_buck_set_mode(struct udevice *dev, int mode) 225{ 226 return pmic_clrsetbits(dev->parent, 227 STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1), 228 STPMIC1_BUCK_PREG_MODE, 229 mode ? STPMIC1_BUCK_PREG_MODE : 0); 230} 231 232static int stpmic1_buck_probe(struct udevice *dev) 233{ 234 struct dm_regulator_uclass_plat *uc_pdata; 235 236 if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_BUCK) 237 return -EINVAL; 238 239 uc_pdata = dev_get_uclass_plat(dev); 240 241 uc_pdata->type = REGULATOR_TYPE_BUCK; 242 uc_pdata->mode = (struct dm_regulator_mode *)buck_modes; 243 uc_pdata->mode_count = ARRAY_SIZE(buck_modes); 244 245 return 0; 246} 247 248static const struct dm_regulator_ops stpmic1_buck_ops = { 249 .get_value = stpmic1_buck_get_value, 250 .set_value = stpmic1_buck_set_value, 251 .get_enable = stpmic1_buck_get_enable, 252 .set_enable = stpmic1_buck_set_enable, 253 .get_mode = stpmic1_buck_get_mode, 254 .set_mode = stpmic1_buck_set_mode, 255}; 256 257U_BOOT_DRIVER(stpmic1_buck) = { 258 .name = "stpmic1_buck", 259 .id = UCLASS_REGULATOR, 260 .ops = &stpmic1_buck_ops, 261 .probe = stpmic1_buck_probe, 262}; 263 264/* 265 * LDO regulators 266 */ 267 268static const struct stpmic1_range ldo12_ranges[] = { 269 STPMIC1_RANGE(1700000, 0, 7, 0), 270 STPMIC1_RANGE(1700000, 8, 24, 100000), 271 STPMIC1_RANGE(3300000, 25, 31, 0), 272}; 273 274static const struct stpmic1_range ldo3_ranges[] = { 275 STPMIC1_RANGE(1700000, 0, 7, 0), 276 STPMIC1_RANGE(1700000, 8, 24, 100000), 277 STPMIC1_RANGE(3300000, 25, 30, 0), 278 /* Sel 31 is special case when LDO3 is in mode sync_source (BUCK2/2) */ 279}; 280 281static const struct stpmic1_range ldo5_ranges[] = { 282 STPMIC1_RANGE(1700000, 0, 7, 0), 283 STPMIC1_RANGE(1700000, 8, 30, 100000), 284 STPMIC1_RANGE(3900000, 31, 31, 0), 285}; 286 287static const struct stpmic1_range ldo6_ranges[] = { 288 STPMIC1_RANGE(900000, 0, 24, 100000), 289 STPMIC1_RANGE(3300000, 25, 31, 0), 290}; 291 292/* LDO: 1,2,3,4,5,6 - voltage ranges */ 293static const struct stpmic1_output ldo_voltage_range[] = { 294 STPMIC1_OUTPUT(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)), 295 STPMIC1_OUTPUT(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)), 296 STPMIC1_OUTPUT(ldo3_ranges, ARRAY_SIZE(ldo3_ranges)), 297 STPMIC1_OUTPUT(NULL, 0), 298 STPMIC1_OUTPUT(ldo5_ranges, ARRAY_SIZE(ldo5_ranges)), 299 STPMIC1_OUTPUT(ldo6_ranges, ARRAY_SIZE(ldo6_ranges)), 300}; 301 302/* LDO modes */ 303static const struct dm_regulator_mode ldo_modes[] = { 304 STPMIC1_MODE(STPMIC1_LDO_MODE_NORMAL, 305 STPMIC1_LDO_MODE_NORMAL, "NORMAL"), 306 STPMIC1_MODE(STPMIC1_LDO_MODE_BYPASS, 307 STPMIC1_LDO_MODE_BYPASS, "BYPASS"), 308 STPMIC1_MODE(STPMIC1_LDO_MODE_SINK_SOURCE, 309 STPMIC1_LDO_MODE_SINK_SOURCE, "SINK SOURCE"), 310}; 311 312static int stpmic1_ldo_get_value(struct udevice *dev) 313{ 314 int sel, ldo = dev->driver_data - 1; 315 316 sel = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo)); 317 if (sel < 0) 318 return sel; 319 320 /* ldo4 => 3,3V */ 321 if (ldo == STPMIC1_LDO4) 322 return STPMIC1_LDO4_UV; 323 324 sel &= STPMIC1_LDO12356_VOUT_MASK; 325 sel >>= STPMIC1_LDO12356_VOUT_SHIFT; 326 327 /* ldo3, sel = 31 => BUCK2/2 */ 328 if (ldo == STPMIC1_LDO3 && sel == STPMIC1_LDO3_DDR_SEL) 329 return stpmic1_buck_get_uv(dev->parent, STPMIC1_BUCK2) / 2; 330 331 return stpmic1_output_find_uv(sel, &ldo_voltage_range[ldo]); 332} 333 334static int stpmic1_ldo_set_value(struct udevice *dev, int uv) 335{ 336 int sel, ldo = dev->driver_data - 1; 337 338 /* ldo4 => not possible */ 339 if (ldo == STPMIC1_LDO4) 340 return -EINVAL; 341 342 sel = stpmic1_output_find_sel(uv, &ldo_voltage_range[ldo]); 343 if (sel < 0) 344 return sel; 345 346 return pmic_clrsetbits(dev->parent, 347 STPMIC1_LDOX_MAIN_CR(ldo), 348 STPMIC1_LDO12356_VOUT_MASK, 349 sel << STPMIC1_LDO12356_VOUT_SHIFT); 350} 351 352static int stpmic1_ldo_get_enable(struct udevice *dev) 353{ 354 int ret; 355 356 ret = pmic_reg_read(dev->parent, 357 STPMIC1_LDOX_MAIN_CR(dev->driver_data - 1)); 358 if (ret < 0) 359 return false; 360 361 return ret & STPMIC1_LDO_ENA ? true : false; 362} 363 364static int stpmic1_ldo_set_enable(struct udevice *dev, bool enable) 365{ 366 struct dm_regulator_uclass_plat *uc_pdata; 367 int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS : 368 STPMIC1_DEFAULT_STOP_DELAY_MS; 369 int ret, uv; 370 371 /* if regulator is already in the wanted state, nothing to do */ 372 if (stpmic1_ldo_get_enable(dev) == enable) 373 return 0; 374 375 if (enable) { 376 uc_pdata = dev_get_uclass_plat(dev); 377 uv = stpmic1_ldo_get_value(dev); 378 if (uv < uc_pdata->min_uV || uv > uc_pdata->max_uV) 379 stpmic1_ldo_set_value(dev, uc_pdata->min_uV); 380 } 381 382 ret = pmic_clrsetbits(dev->parent, 383 STPMIC1_LDOX_MAIN_CR(dev->driver_data - 1), 384 STPMIC1_LDO_ENA, enable ? STPMIC1_LDO_ENA : 0); 385 mdelay(delay); 386 387 return ret; 388} 389 390static int stpmic1_ldo_get_mode(struct udevice *dev) 391{ 392 int ret, ldo = dev->driver_data - 1; 393 394 if (ldo != STPMIC1_LDO3) 395 return -EINVAL; 396 397 ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo)); 398 if (ret < 0) 399 return ret; 400 401 if (ret & STPMIC1_LDO3_MODE) 402 return STPMIC1_LDO_MODE_BYPASS; 403 404 ret &= STPMIC1_LDO12356_VOUT_MASK; 405 ret >>= STPMIC1_LDO12356_VOUT_SHIFT; 406 407 return ret == STPMIC1_LDO3_DDR_SEL ? STPMIC1_LDO_MODE_SINK_SOURCE : 408 STPMIC1_LDO_MODE_NORMAL; 409} 410 411static int stpmic1_ldo_set_mode(struct udevice *dev, int mode) 412{ 413 int ret, ldo = dev->driver_data - 1; 414 415 if (ldo != STPMIC1_LDO3) 416 return -EINVAL; 417 418 ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo)); 419 if (ret < 0) 420 return ret; 421 422 switch (mode) { 423 case STPMIC1_LDO_MODE_SINK_SOURCE: 424 ret &= ~STPMIC1_LDO12356_VOUT_MASK; 425 ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_VOUT_SHIFT; 426 /* fallthrough */ 427 case STPMIC1_LDO_MODE_NORMAL: 428 ret &= ~STPMIC1_LDO3_MODE; 429 break; 430 case STPMIC1_LDO_MODE_BYPASS: 431 ret |= STPMIC1_LDO3_MODE; 432 break; 433 } 434 435 return pmic_reg_write(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo), ret); 436} 437 438static int stpmic1_ldo_probe(struct udevice *dev) 439{ 440 struct dm_regulator_uclass_plat *uc_pdata; 441 442 if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_LDO) 443 return -EINVAL; 444 445 uc_pdata = dev_get_uclass_plat(dev); 446 447 uc_pdata->type = REGULATOR_TYPE_LDO; 448 if (dev->driver_data - 1 == STPMIC1_LDO3) { 449 uc_pdata->mode = (struct dm_regulator_mode *)ldo_modes; 450 uc_pdata->mode_count = ARRAY_SIZE(ldo_modes); 451 } else { 452 uc_pdata->mode_count = 0; 453 } 454 455 return 0; 456} 457 458static const struct dm_regulator_ops stpmic1_ldo_ops = { 459 .get_value = stpmic1_ldo_get_value, 460 .set_value = stpmic1_ldo_set_value, 461 .get_enable = stpmic1_ldo_get_enable, 462 .set_enable = stpmic1_ldo_set_enable, 463 .get_mode = stpmic1_ldo_get_mode, 464 .set_mode = stpmic1_ldo_set_mode, 465}; 466 467U_BOOT_DRIVER(stpmic1_ldo) = { 468 .name = "stpmic1_ldo", 469 .id = UCLASS_REGULATOR, 470 .ops = &stpmic1_ldo_ops, 471 .probe = stpmic1_ldo_probe, 472}; 473 474/* 475 * VREF DDR regulator 476 */ 477 478static int stpmic1_vref_ddr_get_value(struct udevice *dev) 479{ 480 /* BUCK2/2 */ 481 return stpmic1_buck_get_uv(dev->parent, STPMIC1_BUCK2) / 2; 482} 483 484static int stpmic1_vref_ddr_get_enable(struct udevice *dev) 485{ 486 int ret; 487 488 ret = pmic_reg_read(dev->parent, STPMIC1_REFDDR_MAIN_CR); 489 if (ret < 0) 490 return false; 491 492 return ret & STPMIC1_VREF_ENA ? true : false; 493} 494 495static int stpmic1_vref_ddr_set_enable(struct udevice *dev, bool enable) 496{ 497 int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS : 498 STPMIC1_DEFAULT_STOP_DELAY_MS; 499 int ret; 500 501 /* if regulator is already in the wanted state, nothing to do */ 502 if (stpmic1_vref_ddr_get_enable(dev) == enable) 503 return 0; 504 505 ret = pmic_clrsetbits(dev->parent, STPMIC1_REFDDR_MAIN_CR, 506 STPMIC1_VREF_ENA, enable ? STPMIC1_VREF_ENA : 0); 507 mdelay(delay); 508 509 return ret; 510} 511 512static int stpmic1_vref_ddr_probe(struct udevice *dev) 513{ 514 struct dm_regulator_uclass_plat *uc_pdata; 515 516 uc_pdata = dev_get_uclass_plat(dev); 517 518 uc_pdata->type = REGULATOR_TYPE_FIXED; 519 uc_pdata->mode_count = 0; 520 521 return 0; 522} 523 524static const struct dm_regulator_ops stpmic1_vref_ddr_ops = { 525 .get_value = stpmic1_vref_ddr_get_value, 526 .get_enable = stpmic1_vref_ddr_get_enable, 527 .set_enable = stpmic1_vref_ddr_set_enable, 528}; 529 530U_BOOT_DRIVER(stpmic1_vref_ddr) = { 531 .name = "stpmic1_vref_ddr", 532 .id = UCLASS_REGULATOR, 533 .ops = &stpmic1_vref_ddr_ops, 534 .probe = stpmic1_vref_ddr_probe, 535}; 536 537/* 538 * BOOST regulator 539 */ 540 541static int stpmic1_boost_get_enable(struct udevice *dev) 542{ 543 int ret; 544 545 ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR); 546 if (ret < 0) 547 return false; 548 549 return ret & STPMIC1_BST_ON ? true : false; 550} 551 552static int stpmic1_boost_set_enable(struct udevice *dev, bool enable) 553{ 554 int ret; 555 556 ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR); 557 if (ret < 0) 558 return ret; 559 560 if (!enable && ret & STPMIC1_PWR_SW_ON) 561 return -EINVAL; 562 563 /* if regulator is already in the wanted state, nothing to do */ 564 if (!!(ret & STPMIC1_BST_ON) == enable) 565 return 0; 566 567 ret = pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR, 568 STPMIC1_BST_ON, 569 enable ? STPMIC1_BST_ON : 0); 570 if (enable) 571 mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS); 572 573 return ret; 574} 575 576static int stpmic1_boost_probe(struct udevice *dev) 577{ 578 struct dm_regulator_uclass_plat *uc_pdata; 579 580 uc_pdata = dev_get_uclass_plat(dev); 581 582 uc_pdata->type = REGULATOR_TYPE_FIXED; 583 uc_pdata->mode_count = 0; 584 585 return 0; 586} 587 588static const struct dm_regulator_ops stpmic1_boost_ops = { 589 .get_enable = stpmic1_boost_get_enable, 590 .set_enable = stpmic1_boost_set_enable, 591}; 592 593U_BOOT_DRIVER(stpmic1_boost) = { 594 .name = "stpmic1_boost", 595 .id = UCLASS_REGULATOR, 596 .ops = &stpmic1_boost_ops, 597 .probe = stpmic1_boost_probe, 598}; 599 600/* 601 * USB power switch 602 */ 603 604static int stpmic1_pwr_sw_get_enable(struct udevice *dev) 605{ 606 uint mask = 1 << dev->driver_data; 607 int ret; 608 609 ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR); 610 if (ret < 0) 611 return false; 612 613 return ret & mask ? true : false; 614} 615 616static int stpmic1_pwr_sw_set_enable(struct udevice *dev, bool enable) 617{ 618 uint mask = 1 << dev->driver_data; 619 int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS : 620 STPMIC1_DEFAULT_STOP_DELAY_MS; 621 int ret; 622 623 ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR); 624 if (ret < 0) 625 return ret; 626 627 /* if regulator is already in the wanted state, nothing to do */ 628 if (!!(ret & mask) == enable) 629 return 0; 630 631 /* Boost management */ 632 if (enable && !(ret & STPMIC1_BST_ON)) { 633 pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR, 634 STPMIC1_BST_ON, STPMIC1_BST_ON); 635 mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS); 636 } else if (!enable && ret & STPMIC1_BST_ON && 637 (ret & STPMIC1_PWR_SW_ON) != STPMIC1_PWR_SW_ON) { 638 pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR, 639 STPMIC1_BST_ON, 0); 640 } 641 642 ret = pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR, 643 mask, enable ? mask : 0); 644 mdelay(delay); 645 646 return ret; 647} 648 649static int stpmic1_pwr_sw_probe(struct udevice *dev) 650{ 651 struct dm_regulator_uclass_plat *uc_pdata; 652 653 if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_PWR_SW) 654 return -EINVAL; 655 656 uc_pdata = dev_get_uclass_plat(dev); 657 658 uc_pdata->type = REGULATOR_TYPE_FIXED; 659 uc_pdata->mode_count = 0; 660 661 return 0; 662} 663 664static const struct dm_regulator_ops stpmic1_pwr_sw_ops = { 665 .get_enable = stpmic1_pwr_sw_get_enable, 666 .set_enable = stpmic1_pwr_sw_set_enable, 667}; 668 669U_BOOT_DRIVER(stpmic1_pwr_sw) = { 670 .name = "stpmic1_pwr_sw", 671 .id = UCLASS_REGULATOR, 672 .ops = &stpmic1_pwr_sw_ops, 673 .probe = stpmic1_pwr_sw_probe, 674}; 675