Searched refs:scr (Results 1 - 25 of 25) sorted by relevance

/u-boot/arch/arm/mach-imx/mx6/
H A Dmp.c36 src->scr |= cpu_reset_mask[nr];
42 printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
67 src->scr |= cpu_ctrl_mask[nr];
85 src->scr &= ~cpu_ctrl_mask[nr];
/u-boot/arch/arm/include/asm/arch-rockchip/
H A Duart.h16 unsigned int scr; member in struct:rk_uart
/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c249 u32 scr; local
251 asm volatile ("mrc p15, 0, %0, c1, c1, 0" : "=r" (scr));
253 return scr;
256 static void __secure cp15_write_scr(u32 scr) argument
258 asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
270 u32 scr, reg, cpu; local
273 scr = cp15_read_scr();
274 cp15_write_scr(scr & ~BIT(0));
295 cp15_write_scr(scr);
/u-boot/drivers/spi/
H A Dpl022_spi.c238 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) argument
240 return rate / (cpsdvsr * (1 + scr));
246 u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr, local
262 while (scr <= SSP_SCR_MAX) {
263 tmp = spi_rate(rate, cpsr, scr);
268 best_scr = scr;
276 scr++;
279 scr = SSP_SCR_MIN;
H A Datmel-quadspi.c937 u32 scr, scbr, mask, new_value; local
950 scr = atmel_qspi_read(aq, QSPI_SCR);
951 if ((scr & mask) == new_value)
954 scr = (scr & ~mask) | new_value;
955 atmel_qspi_write(scr, aq, QSPI_SCR);
963 u32 scr, mask, new_value = 0; local
972 scr = atmel_qspi_read(aq, QSPI_SCR);
973 if ((scr & mask) == new_value)
976 scr
[all...]
/u-boot/board/BuR/common/
H A Dbr_resetc.c112 u8 regb, scr; local
128 rc = dm_i2c_read(resetc.i2cdev, RSTCTRL_SCRATCHREG0, &scr, 1);
179 } else if ((regb & 0x1) || scr == 0xCC) {
/u-boot/arch/arm/include/asm/
H A Darmv7m.h31 uint32_t scr; /* offset 0x10: System Control Register */ member in struct:v7m_scb
/u-boot/arch/arm/mach-imx/
H A Dinit.c98 val = readl(&src_regs->scr);
100 writel(val, &src_regs->scr);
/u-boot/arch/arm/mach-imx/imx9/
H A Dsoc.c683 u32 scr, val; local
689 scr = BIT(5);
700 scr = BIT(4);
705 scr = BIT(6);
722 setbits_le32(&global_regs->scr, scr);
801 setbits_le32(&global_regs->scr, BIT(0));
/u-boot/drivers/mmc/
H A Dsandbox_mmc.c119 u32 *scr = (u32 *)data->dest; local
121 scr[0] = cpu_to_be32(2 << 24 | 1 << 15); /* SD version 3 */
H A Dmmc.c1333 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1360 data.dest = (char *)scr;
1370 mmc->scr[0] = __be32_to_cpu(scr[0]);
1371 mmc->scr[1] = __be32_to_cpu(scr[1]);
1373 switch ((mmc->scr[0] >> 24) & 0xf) {
1382 if ((mmc->scr[0] >> 15) & 0x1)
1390 if (mmc->scr[0] & SD_DATA_4BIT)
H A Dfsl_esdhc_imx.c109 uint scr; /* eSDHC control register */ member in struct:fsl_esdhc
H A Docteontx_hsmmc.c970 if (size > 1 && ((IS_SD(mmc) && (mmc->scr[0] & 2)) || !IS_SD(mmc)))
1278 ((IS_SD(mmc) && mmc->scr[0] & 2) || !IS_SD(mmc));
/u-boot/include/
H A Dns16550.h111 UART_REG(scr); /* 10*/
H A Dmmc.h682 uint scr[2]; member in struct:mmc
H A Dimx_lpi2c.h49 u32 scr; member in struct:imx_lpi2c_reg
/u-boot/arch/m68k/include/asm/coldfire/
H A Dlcd.h24 u32 scr; /* 0x28 Sharp Configuration Register */ member in struct:lcd_ctrl
/u-boot/arch/arm/include/asm/arch-imx9/
H A Dimx-regs.h174 u32 scr; member in struct:src_general_regs
/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-pko3.h548 const unsigned int scr = cvmx_pko3_lmtdma_scr_base(); local
550 return (u64 *)(CVMX_SCRATCH_BASE + scr);
/u-boot/arch/arm/include/asm/arch-mx5/
H A Dimx-regs.h429 u32 scr; member in struct:src
/u-boot/drivers/mtd/nand/raw/
H A Dzynq_nand.c118 u32 scr; /* 0x14 */ member in struct:zynq_nand_smc_regs
295 writel(ZYNQ_NAND_SET_CYCLES, &smc->reg->scr);
/u-boot/arch/arm/include/asm/arch-vf610/
H A Dimx-regs.h306 u32 scr; member in struct:src
/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dimx-regs.h335 u32 scr; member in struct:src
/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h467 u32 scr; member in struct:src
/u-boot/arch/arm/include/asm/arch-mx7/
H A Dimx-regs.h233 u32 scr; member in struct:src

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