1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2022 NXP
4 */
5
6#ifndef __ASM_ARCH_IMX9_REGS_H__
7#define __ASM_ARCH_IMX9_REGS_H__
8
9#define ARCH_MXC
10#define FEC_QUIRK_ENET_MAC
11
12#define IOMUXC_BASE_ADDR	0x443C0000UL
13#define CCM_BASE_ADDR		0x44450000UL
14#define CCM_CCGR_BASE_ADDR	0x44458000UL
15#define SYSCNT_CTRL_BASE_ADDR	0x44290000
16
17#define ANATOP_BASE_ADDR    0x44480000UL
18
19#define WDG3_BASE_ADDR      0x42490000UL
20#define WDG4_BASE_ADDR      0x424a0000UL
21#define WDG5_BASE_ADDR      0x424b0000UL
22
23#define FSB_BASE_ADDR       0x47510000UL
24
25#define ANATOP_BASE_ADDR    0x44480000UL
26
27#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x42420000
28#define BLK_CTRL_S_ANOMIX_BASE_ADDR  0x444f0000
29
30#define SRC_IPS_BASE_ADDR	(0x44460000)
31#define SRC_GLOBAL_RBASE	(SRC_IPS_BASE_ADDR + 0x0000)
32
33#define SRC_DDR_RBASE		(SRC_IPS_BASE_ADDR + 0x1000)
34#define SRC_ML_RBASE		(SRC_IPS_BASE_ADDR + 0x1800)
35#define SRC_MEDIA_RBASE		(SRC_IPS_BASE_ADDR + 0x2400)
36#define SRC_M33P_RBASE		(SRC_IPS_BASE_ADDR + 0x2800)
37
38#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
39#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
40#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
41#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
42
43#define IMG_CONTAINER_BASE             (0x80000000UL)
44
45#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK        GENMASK(3, 1)
46#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII          (0x0 << 1)
47#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII         (0x4 << 1)
48#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII        (0x1 << 1)
49#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN            (0x1 << 0)
50
51#define MARKETING_GRADING_MASK	GENMASK(5, 4)
52#define SPEED_GRADING_MASK	GENMASK(11, 6)
53
54#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
55#include <asm/types.h>
56#include <stdbool.h>
57
58struct mu_type {
59	u32 ver;
60	u32 par;
61	u32 cr;
62	u32 sr;
63	u32 reserved0[60];
64	u32 fcr;
65	u32 fsr;
66	u32 reserved1[2];
67	u32 gier;
68	u32 gcr;
69	u32 gsr;
70	u32 reserved2;
71	u32 tcr;
72	u32 tsr;
73	u32 rcr;
74	u32 rsr;
75	u32 reserved3[52];
76	u32 tr[16];
77	u32 reserved4[16];
78	u32 rr[16];
79	u32 reserved5[14];
80	u32 mu_attr;
81};
82
83enum mix_power_domain {
84	MIX_PD_MEDIAMIX,
85	MIX_PD_MLMIX,
86	MIX_PD_DDRMIX,
87};
88
89enum src_mix_slice_id {
90	SRC_MIX_EDGELOCK = 0,
91	SRC_MIX_AONMIX = 1,
92	SRC_MIX_WAKEUPMIX = 2,
93	SRC_MIX_DDRMIX = 3,
94	SRC_MIX_DDRPHY = 4,
95	SRC_MIX_ML = 5,
96	SRC_MIX_NIC = 6,
97	SRC_MIX_HSIO = 7,
98	SRC_MIX_MEDIA = 8,
99	SRC_MIX_CM33 = 9,
100	SRC_MIX_CA55C0 = 10,
101	SRC_MIX_CA55C1 = 11,
102	SRC_MIX_CA55CLUSTER = 12,
103};
104
105enum src_mem_slice_id {
106	SRC_MEM_AONMIX = 0,
107	SRC_MEM_WAKEUPMIX = 1,
108	SRC_MEM_DDRMIX = 2,
109	SRC_MEM_DDRPHY = 3,
110	SRC_MEM_ML = 4,
111	SRC_MEM_NIC = 5,
112	SRC_MEM_OCRAM = 6,
113	SRC_MEM_HSIO = 7,
114	SRC_MEM_MEDIA = 8,
115	SRC_MEM_CA55C0 = 9,
116	SRC_MEM_CA55C1 = 10,
117	SRC_MEM_CA55CLUSTER = 11,
118	SRC_MEM_L3 = 12,
119};
120
121struct blk_ctrl_s_aonmix_regs {
122	u32 cm33_irq_mask[7];
123	u32 initnsvtor;
124	u32 reserved1[8];
125	u32 ca55_irq_mask[7];
126	u32 initsvtor;
127	u32 m33_cfg;
128	u32 reserved2[11];
129	u32 axbs_aon_ctrl;
130	u32 reserved3[27];
131	u32 dap_access_stkybit;
132	u32 reserved4[3];
133	u32 lp_handshake[2];
134	u32 ca55_cpuwait;
135	u32 ca55_rvbaraddr0_l;
136	u32 ca55_rvbaraddr0_h;
137	u32 ca55_rvbaraddr1_l;
138	u32 ca55_rvbaraddr1_h;
139	u32 s401_irq_mask;
140	u32 s401_reset_req_mask;
141	u32 s401_halt_st;
142	u32 ca55_mode;
143	u32 nmi_mask;
144	u32 nmi_clr;
145	u32 wdog_any_mask;
146	u32 s4v1_ipi_noclk_ref1;
147};
148
149struct blk_ctrl_wakeupmix_regs {
150	u32 upper_addr;
151	u32 ipg_debug_cm33;
152	u32 reserved[2];
153	u32 qch_dis;
154	u32 ssi;
155	u32 reserved1[1];
156	u32 dexsc_err;
157	u32 mqs_setting;
158	u32 sai_clk_sel;
159	u32 eqos_gpr;
160	u32 enet_clk_sel;
161	u32 reserved2[1];
162	u32 volt_detect;
163	u32 i3c2_wakeup;
164	u32 ipg_debug_ca55c0;
165	u32 ipg_debug_ca55c1;
166	u32 axi_attr_cfg;
167	u32 i3c2_sda_irq;
168};
169
170struct src_general_regs {
171	u32 reserved[1];
172	u32 authen_ctrl;
173	u32 reserved1[2];
174	u32 scr;
175	u32 srtmr;
176	u32 srmask;
177	u32 reserved2[1];
178	u32 srmr[6];
179	u32 reserved3[2];
180	u32 sbmr[2];
181	u32 reserved4[2];
182	u32 srsr;
183	u32 gpr[19];
184	u32 reserved5[24];
185	u32 gpr20;
186	u32 cm_quiesce;
187	u32 cold_reset_ssar_ack_ctrl;
188	u32 sp_iso_ctrl;
189	u32 rom_lp_ctrl;
190	u32 a55_deny_stat;
191};
192
193struct src_mem_slice_regs {
194	u32 reserved[1];
195	u32 mem_ctrl;
196	u32 memlp_ctrl_0;
197	u32 reserved1[1];
198	u32 memlp_ctrl_1;
199	u32 memlp_ctrl_2;
200	u32 mem_stat;
201};
202
203struct src_mix_slice_regs {
204	u32 reserved[1];
205	u32 authen_ctrl;
206	u32 reserved1[2];
207	u32 lpm_setting[3];
208	u32 reserved2[1];
209	u32 slice_sw_ctrl;
210	u32 single_reset_sw_ctrl;
211	u32 reserved3[6];
212	u32 a55_hdsk_ack_ctrl;
213	u32 a55_hdsk_ack_stat;
214	u32 reserved4[2];
215	u32 ssar_ack_ctrl;
216	u32 ssar_ack_stat;
217	u32 reserved5[1];
218	u32 iso_off_dly_por;
219	u32 iso_on_dly;
220	u32 iso_off_dly;
221	u32 psw_off_lf_dly;
222	u32 reserved6[1];
223	u32 psw_off_hf_dly;
224	u32 psw_on_lf_dly;
225	u32 psw_on_hf_dly;
226	u32 reserved7[1];
227	u32 psw_ack_ctrl[2];
228	u32 psw_ack_stat;
229	u32 reserved8[1];
230	u32 mtr_ack_ctrl;
231	u32 mtr_ack_stat;
232	u32 reserved9[2];
233	u32 upi_stat[4];
234	u32 fsm_stat;
235	u32 func_stat;
236};
237#endif
238
239#endif
240