#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
6cd4f48b |
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18-Jan-2021 |
Marek Vasut <marex@denx.de> |
spi: imx: Define register bits in the driver The CSPI/ECSPI register bits do not differ between newer SoCs, instead of having multiple copies of the same thing for each iMX SoC, define the bits in the driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de> |
#
f09f1ecb |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
Use __ASSEMBLY__ as the assembly macros Some places use __ASSEMBLER__ instead which does not work since the Makefile does not define it. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
54d8d494 |
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08-Nov-2017 |
Martyn Welch <martyn.welch@collabora.co.uk> |
arm: mx5: Add more register definitions Add register definitions require for video configuration. Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Reviewed-by: Stefano Babic <sbabic@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> |
#
065a1ece |
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08-Nov-2017 |
Martyn Welch <martyn.welch@collabora.co.uk> |
pwm: imx: Enable PWM support on i.MX53 Add missing parts for i.MX53 PWM support Acked-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> |
#
067716ba |
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22-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Move SYS_CACHELINE_SIZE over to Kconfig This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr> |
#
fc5ad477 |
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12-Oct-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: cpu: move common chip revision id's Move common chip revision id's to main cpu header file mx25 generic include cpu header for chip revision Signed-off-by: Adrian Alonso <aalonso@freescale.com> |
#
1005ccda |
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02-Jun-2015 |
Chris Kuethe <chris.kuethe@gmail.com> |
patch - arm - define SYS_CACHELINE_SIZE for mx5 mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Matthew Starr <mstarr@hedonline.com> Cc: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
32c81ea6 |
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14-Nov-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
imx: consolidate set_chipselect_size function Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
d7cbcc76 |
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17-Feb-2014 |
Markus Niebel <Markus.Niebel@tq-group.de> |
spi: spi-mxc: add defines for clk inactive state for ECSPI Provide define for the SCLK_CTL field of the config reg of ECSPI. While at it, oder the defines to improve readability and make adding more defines easier. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> |
#
1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
6adbd302 |
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23-Apr-2013 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
imx: Add useful fuse definitions Define the UID (SoC unique ID) fuses, and the fuses available for the user. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
#
8f3ff11c |
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23-Apr-2013 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
imx: Homogenize and fix fuse register definitions IIM: - Homogenize prg_p naming (the reference manuals are not always self-consistent for that). - Add missing SCSx and bank registers. - Fix the number of banks on i.MX53. OCOTP: - Rename iim to ocotp in order to avoid confusion. - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the reference manual. - Merge the existing spinoff gp1 fuse definition on i.MX6. - Fix the number of banks on i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de> |
#
1155d555 |
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24-Apr-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53ard: Move register masks into imx-regs.h imx-regs.h is more appropriate location for containing register masks. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> |
#
0f1411bc |
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09-Apr-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
spi: mxc_spi: Set master mode for all channels The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
abbab703 |
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22-Oct-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
mx31/mx35/mx51/mx53/mx6: add watchdog Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de> |
#
782b0288 |
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14-Oct-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx5: lowlevel_init.S: Fix PLL settings for mx53 Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
362635bd |
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17-Sep-2012 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
mx51evk: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
8e99ecd7 |
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13-Aug-2012 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
mxc: Define architecture identifier Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> |
#
124a06d7 |
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15-Aug-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
imx-common/cmd_bmode.c: add imx bmode (bootmode) command This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Note: MX53 support untested. Acked-by: Stefano Babic <sbabic@denx.de> |
#
df369dcd |
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19-Jul-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
i.mx53: add definition for I2C3_BASE_ADDR Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> |
#
05d4df1d |
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31-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Allow mx6 to access the IPUv3 registers Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
fff6ef72 |
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15-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53: Allow IPUv3 driver to also work on mx53 Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and mx53 SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
54cd1dee |
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07-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53loco: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. The kernel uses this data to distinguish between Dialog versus mc34708 based boards, and also to distinguish between revA and revB of the mc34708 based boards. Suggested-by: Yu Li <yk@magniel.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> |
#
d87c85ce |
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21-Feb-2012 |
Stefano Babic <sbabic@denx.de> |
MX5: Add definitions for SATA controller Add base address and MXC_SATA_CLK to return the clock used for the SATA controller. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Dirk Behme <dirk.behme@de.bosch.com> |
#
4a9677e5 |
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21-Feb-2012 |
Stefano Babic <sbabic@denx.de> |
Define UART4 and UART5 base addresses Signed-off-by: Stefano Babic <sbabic@denx.de> |
#
08c61a58 |
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31-Jan-2012 |
Eric Nelson <eric.nelson@boundarydevices.com> |
mxc_spi: move machine specifics into CPU headers Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU Introduce two new macros to control conditional setup MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x) Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org> Tested-by: Jason Liu <jason.hui@linaro.org> |
#
40f6fffe |
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22-Nov-2011 |
Stefano Babic <sbabic@denx.de> |
MX: serial_mxc: cleanup removing nasty #ifdef The serial driver for iMX SOCs is continuosly changed if a new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port> defines were used only to find the base address for the selected UART. Instead of that, move the base address to the board configuration file and drop all #ifdef from driver. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Helmut Raiger <helmut.raiger@hale.at> CC: John Rigby <jcrigby@gmail.com> CC: Matthias Weisser <weisserm@arcor.de> CC: Jason Liu <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linaro.org> |
#
bf2eaf51 |
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23-Sep-2011 |
Marek Vasut <marek.vasut@gmail.com> |
MX5: Modify the PLL decoding algorithm The PLL decoding algorithm didn't take into account many configuration bits. Adjust it according to Linux kernel. Also, add PLL4 for MX53. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Tested-by: Jason Liu <Jason.hui@linaro.org> |
#
8edcc6f2 |
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11-Sep-2011 |
Marek Vasut <marek.vasut@gmail.com> |
FEC: Move imx_get_mac_from_fuse() definition to fec_mxc.h Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> |
#
7d8d0b1a |
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21-Aug-2011 |
Stefano Babic <sbabic@denx.de> |
MX5: make use of GPIO framework for MX5 processor Signed-off-by: Stefano Babic <sbabic@denx.de> |
#
9db1bfa1 |
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13-Jul-2011 |
David Jander <david@protonic.nl> |
ARM: MX51: PLL errata workaround This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl> |
#
0edf8b5b |
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06-Jul-2011 |
Stefano Babic <sbabic@denx.de> |
MX5: Update to autogenerated asm-offsets.h On i.MX5, the asm-offsets.h file is not yet generated as it should be. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de> |
#
a6e961c2 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Introduce a function for setting the chip select size Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
a682b3f7 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Add iomux structure Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
ac4020e3 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Make the weim structure complete Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
ac87c17d |
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19-Jan-2011 |
Stefano Babic <sbabic@denx.de> |
SPI: mxc_spi: replace fixed offsets with structures This patch cleans driver code replacing all accesses to registers with fixed offsets with a corresponding structure. Signed-off-by: Stefano Babic <sbabic@denx.de> |
#
595f3e56 |
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03-Jan-2011 |
Liu Hui-R64343 <r64343@freescale.com> |
MX5: Add initial support for MX53 processor Add initial support for Freescale MX53 processor, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro Signed-off-by: Jason Liu <r64343@freescale.com> |
#
565e39c5 |
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18-Nov-2010 |
Liu Hui-R64343 <r64343@freescale.com> |
imx: Get fec mac address from fuse The patch is to support getting FEC MAC address from fuse bank. Signed-off-by: Jason Liu <r64343@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> |
#
1ab027cb |
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27-Oct-2010 |
Shawn Guo <shawn.gsc@gmail.com> |
mx51evk: support new relocation scheme This patch is to fix build breakage and support new relocation scheme for mx51evk. - Correct IRAM base address and add size definition The IRAM starts from 0x1FFE0000 on final revsion i.mx51 than 0x1FFE8000 which is for older revision. - Include imx-regs.h in mx51evk.h Definitions like CSD0_BASE_ADDR and IRAM_BASE_ADDR can be referred to. - Define CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE They are used to define init RAM layout. - Remove comment for CONFIG_SYS_GBL_DATA_SIZE which has been buried by Wolfgang's commit below 25ddd1fb: Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value Signed-off-by: Shawn Guo <shawn.gsc@gmail.com> |
#
ff9f475d |
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17-Oct-2010 |
Jason Liu <r64343@freescale.com> |
MX5: rename mx51 to mx5 Rename mx51 to mx5 in order to support more mx51 like-style SOCs such as MX53 and the followings. Signed-off-by: Jason Liu <r64343@freescale.com> |
#
6cd4f48b |
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18-Jan-2021 |
Marek Vasut <marex@denx.de> |
spi: imx: Define register bits in the driver The CSPI/ECSPI register bits do not differ between newer SoCs, instead of having multiple copies of the same thing for each iMX SoC, define the bits in the driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de> |
#
f09f1ecb |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
Use __ASSEMBLY__ as the assembly macros Some places use __ASSEMBLER__ instead which does not work since the Makefile does not define it. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
54d8d494 |
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08-Nov-2017 |
Martyn Welch <martyn.welch@collabora.co.uk> |
arm: mx5: Add more register definitions Add register definitions require for video configuration. Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Reviewed-by: Stefano Babic <sbabic@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> |
#
065a1ece |
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08-Nov-2017 |
Martyn Welch <martyn.welch@collabora.co.uk> |
pwm: imx: Enable PWM support on i.MX53 Add missing parts for i.MX53 PWM support Acked-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> |
#
067716ba |
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22-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Move SYS_CACHELINE_SIZE over to Kconfig This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr> |
#
fc5ad477 |
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12-Oct-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: cpu: move common chip revision id's Move common chip revision id's to main cpu header file mx25 generic include cpu header for chip revision Signed-off-by: Adrian Alonso <aalonso@freescale.com> |
#
1005ccda |
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02-Jun-2015 |
Chris Kuethe <chris.kuethe@gmail.com> |
patch - arm - define SYS_CACHELINE_SIZE for mx5 mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Matthew Starr <mstarr@hedonline.com> Cc: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
32c81ea6 |
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14-Nov-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
imx: consolidate set_chipselect_size function Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
d7cbcc76 |
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17-Feb-2014 |
Markus Niebel <Markus.Niebel@tq-group.de> |
spi: spi-mxc: add defines for clk inactive state for ECSPI Provide define for the SCLK_CTL field of the config reg of ECSPI. While at it, oder the defines to improve readability and make adding more defines easier. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> |
#
1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
6adbd302 |
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23-Apr-2013 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
imx: Add useful fuse definitions Define the UID (SoC unique ID) fuses, and the fuses available for the user. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
#
8f3ff11c |
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23-Apr-2013 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
imx: Homogenize and fix fuse register definitions IIM: - Homogenize prg_p naming (the reference manuals are not always self-consistent for that). - Add missing SCSx and bank registers. - Fix the number of banks on i.MX53. OCOTP: - Rename iim to ocotp in order to avoid confusion. - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the reference manual. - Merge the existing spinoff gp1 fuse definition on i.MX6. - Fix the number of banks on i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de> |
#
1155d555 |
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24-Apr-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53ard: Move register masks into imx-regs.h imx-regs.h is more appropriate location for containing register masks. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> |
#
0f1411bc |
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09-Apr-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
spi: mxc_spi: Set master mode for all channels The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
abbab703 |
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22-Oct-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
mx31/mx35/mx51/mx53/mx6: add watchdog Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de> |
#
782b0288 |
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14-Oct-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx5: lowlevel_init.S: Fix PLL settings for mx53 Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
362635bd |
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17-Sep-2012 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
mx51evk: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
8e99ecd7 |
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13-Aug-2012 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
mxc: Define architecture identifier Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> |
#
124a06d7 |
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15-Aug-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
imx-common/cmd_bmode.c: add imx bmode (bootmode) command This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Note: MX53 support untested. Acked-by: Stefano Babic <sbabic@denx.de> |
#
df369dcd |
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19-Jul-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
i.mx53: add definition for I2C3_BASE_ADDR Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> |
#
05d4df1d |
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31-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Allow mx6 to access the IPUv3 registers Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
fff6ef72 |
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15-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53: Allow IPUv3 driver to also work on mx53 Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and mx53 SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
54cd1dee |
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07-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53loco: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. The kernel uses this data to distinguish between Dialog versus mc34708 based boards, and also to distinguish between revA and revB of the mc34708 based boards. Suggested-by: Yu Li <yk@magniel.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> |
#
d87c85ce |
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21-Feb-2012 |
Stefano Babic <sbabic@denx.de> |
MX5: Add definitions for SATA controller Add base address and MXC_SATA_CLK to return the clock used for the SATA controller. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Dirk Behme <dirk.behme@de.bosch.com> |
#
4a9677e5 |
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21-Feb-2012 |
Stefano Babic <sbabic@denx.de> |
Define UART4 and UART5 base addresses Signed-off-by: Stefano Babic <sbabic@denx.de> |
#
08c61a58 |
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31-Jan-2012 |
Eric Nelson <eric.nelson@boundarydevices.com> |
mxc_spi: move machine specifics into CPU headers Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU Introduce two new macros to control conditional setup MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x) Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org> Tested-by: Jason Liu <jason.hui@linaro.org> |
#
40f6fffe |
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22-Nov-2011 |
Stefano Babic <sbabic@denx.de> |
MX: serial_mxc: cleanup removing nasty #ifdef The serial driver for iMX SOCs is continuosly changed if a new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port> defines were used only to find the base address for the selected UART. Instead of that, move the base address to the board configuration file and drop all #ifdef from driver. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Helmut Raiger <helmut.raiger@hale.at> CC: John Rigby <jcrigby@gmail.com> CC: Matthias Weisser <weisserm@arcor.de> CC: Jason Liu <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linaro.org> |
#
bf2eaf51 |
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23-Sep-2011 |
Marek Vasut <marek.vasut@gmail.com> |
MX5: Modify the PLL decoding algorithm The PLL decoding algorithm didn't take into account many configuration bits. Adjust it according to Linux kernel. Also, add PLL4 for MX53. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Tested-by: Jason Liu <Jason.hui@linaro.org> |
#
8edcc6f2 |
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11-Sep-2011 |
Marek Vasut <marek.vasut@gmail.com> |
FEC: Move imx_get_mac_from_fuse() definition to fec_mxc.h Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> |
#
7d8d0b1a |
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21-Aug-2011 |
Stefano Babic <sbabic@denx.de> |
MX5: make use of GPIO framework for MX5 processor Signed-off-by: Stefano Babic <sbabic@denx.de> |
#
9db1bfa1 |
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13-Jul-2011 |
David Jander <david@protonic.nl> |
ARM: MX51: PLL errata workaround This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl> |
#
0edf8b5b |
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06-Jul-2011 |
Stefano Babic <sbabic@denx.de> |
MX5: Update to autogenerated asm-offsets.h On i.MX5, the asm-offsets.h file is not yet generated as it should be. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de> |
#
a6e961c2 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Introduce a function for setting the chip select size Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
a682b3f7 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Add iomux structure Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
ac4020e3 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Make the weim structure complete Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
ac87c17d |
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19-Jan-2011 |
Stefano Babic <sbabic@denx.de> |
SPI: mxc_spi: replace fixed offsets with structures This patch cleans driver code replacing all accesses to registers with fixed offsets with a corresponding structure. Signed-off-by: Stefano Babic <sbabic@denx.de> |
#
595f3e56 |
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03-Jan-2011 |
Liu Hui-R64343 <r64343@freescale.com> |
MX5: Add initial support for MX53 processor Add initial support for Freescale MX53 processor, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro Signed-off-by: Jason Liu <r64343@freescale.com> |
#
565e39c5 |
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18-Nov-2010 |
Liu Hui-R64343 <r64343@freescale.com> |
imx: Get fec mac address from fuse The patch is to support getting FEC MAC address from fuse bank. Signed-off-by: Jason Liu <r64343@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> |
#
1ab027cb |
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27-Oct-2010 |
Shawn Guo <shawn.gsc@gmail.com> |
mx51evk: support new relocation scheme This patch is to fix build breakage and support new relocation scheme for mx51evk. - Correct IRAM base address and add size definition The IRAM starts from 0x1FFE0000 on final revsion i.mx51 than 0x1FFE8000 which is for older revision. - Include imx-regs.h in mx51evk.h Definitions like CSD0_BASE_ADDR and IRAM_BASE_ADDR can be referred to. - Define CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE They are used to define init RAM layout. - Remove comment for CONFIG_SYS_GBL_DATA_SIZE which has been buried by Wolfgang's commit below 25ddd1fb: Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value Signed-off-by: Shawn Guo <shawn.gsc@gmail.com> |
#
ff9f475d |
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17-Oct-2010 |
Jason Liu <r64343@freescale.com> |
MX5: rename mx51 to mx5 Rename mx51 to mx5 in order to support more mx51 like-style SOCs such as MX53 and the followings. Signed-off-by: Jason Liu <r64343@freescale.com> |
#
f09f1ecb |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
Use __ASSEMBLY__ as the assembly macros Some places use __ASSEMBLER__ instead which does not work since the Makefile does not define it. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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54d8d494 |
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08-Nov-2017 |
Martyn Welch <martyn.welch@collabora.co.uk> |
arm: mx5: Add more register definitions Add register definitions require for video configuration. Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Reviewed-by: Stefano Babic <sbabic@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> |
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065a1ece |
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08-Nov-2017 |
Martyn Welch <martyn.welch@collabora.co.uk> |
pwm: imx: Enable PWM support on i.MX53 Add missing parts for i.MX53 PWM support Acked-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> |
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067716ba |
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22-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Move SYS_CACHELINE_SIZE over to Kconfig This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr> |
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fc5ad477 |
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12-Oct-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: cpu: move common chip revision id's Move common chip revision id's to main cpu header file mx25 generic include cpu header for chip revision Signed-off-by: Adrian Alonso <aalonso@freescale.com> |
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1005ccda |
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02-Jun-2015 |
Chris Kuethe <chris.kuethe@gmail.com> |
patch - arm - define SYS_CACHELINE_SIZE for mx5 mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Matthew Starr <mstarr@hedonline.com> Cc: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> |
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32c81ea6 |
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14-Nov-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
imx: consolidate set_chipselect_size function Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
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d7cbcc76 |
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17-Feb-2014 |
Markus Niebel <Markus.Niebel@tq-group.de> |
spi: spi-mxc: add defines for clk inactive state for ECSPI Provide define for the SCLK_CTL field of the config reg of ECSPI. While at it, oder the defines to improve readability and make adding more defines easier. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> |
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1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
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6adbd302 |
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23-Apr-2013 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
imx: Add useful fuse definitions Define the UID (SoC unique ID) fuses, and the fuses available for the user. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
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8f3ff11c |
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23-Apr-2013 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
imx: Homogenize and fix fuse register definitions IIM: - Homogenize prg_p naming (the reference manuals are not always self-consistent for that). - Add missing SCSx and bank registers. - Fix the number of banks on i.MX53. OCOTP: - Rename iim to ocotp in order to avoid confusion. - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the reference manual. - Merge the existing spinoff gp1 fuse definition on i.MX6. - Fix the number of banks on i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de> |
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1155d555 |
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24-Apr-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53ard: Move register masks into imx-regs.h imx-regs.h is more appropriate location for containing register masks. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> |
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0f1411bc |
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09-Apr-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
spi: mxc_spi: Set master mode for all channels The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
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abbab703 |
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22-Oct-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
mx31/mx35/mx51/mx53/mx6: add watchdog Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de> |
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782b0288 |
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14-Oct-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx5: lowlevel_init.S: Fix PLL settings for mx53 Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
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362635bd |
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17-Sep-2012 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
mx51evk: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> |
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8e99ecd7 |
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13-Aug-2012 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
mxc: Define architecture identifier Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> |
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124a06d7 |
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15-Aug-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
imx-common/cmd_bmode.c: add imx bmode (bootmode) command This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Note: MX53 support untested. Acked-by: Stefano Babic <sbabic@denx.de> |
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df369dcd |
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19-Jul-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
i.mx53: add definition for I2C3_BASE_ADDR Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> |
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05d4df1d |
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31-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Allow mx6 to access the IPUv3 registers Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
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fff6ef72 |
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15-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53: Allow IPUv3 driver to also work on mx53 Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and mx53 SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
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54cd1dee |
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07-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53loco: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. The kernel uses this data to distinguish between Dialog versus mc34708 based boards, and also to distinguish between revA and revB of the mc34708 based boards. Suggested-by: Yu Li <yk@magniel.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> |
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d87c85ce |
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21-Feb-2012 |
Stefano Babic <sbabic@denx.de> |
MX5: Add definitions for SATA controller Add base address and MXC_SATA_CLK to return the clock used for the SATA controller. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Dirk Behme <dirk.behme@de.bosch.com> |
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4a9677e5 |
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21-Feb-2012 |
Stefano Babic <sbabic@denx.de> |
Define UART4 and UART5 base addresses Signed-off-by: Stefano Babic <sbabic@denx.de> |
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08c61a58 |
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31-Jan-2012 |
Eric Nelson <eric.nelson@boundarydevices.com> |
mxc_spi: move machine specifics into CPU headers Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU Introduce two new macros to control conditional setup MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x) Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org> Tested-by: Jason Liu <jason.hui@linaro.org> |
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40f6fffe |
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22-Nov-2011 |
Stefano Babic <sbabic@denx.de> |
MX: serial_mxc: cleanup removing nasty #ifdef The serial driver for iMX SOCs is continuosly changed if a new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port> defines were used only to find the base address for the selected UART. Instead of that, move the base address to the board configuration file and drop all #ifdef from driver. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Helmut Raiger <helmut.raiger@hale.at> CC: John Rigby <jcrigby@gmail.com> CC: Matthias Weisser <weisserm@arcor.de> CC: Jason Liu <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linaro.org> |
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bf2eaf51 |
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23-Sep-2011 |
Marek Vasut <marek.vasut@gmail.com> |
MX5: Modify the PLL decoding algorithm The PLL decoding algorithm didn't take into account many configuration bits. Adjust it according to Linux kernel. Also, add PLL4 for MX53. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Tested-by: Jason Liu <Jason.hui@linaro.org> |
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8edcc6f2 |
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11-Sep-2011 |
Marek Vasut <marek.vasut@gmail.com> |
FEC: Move imx_get_mac_from_fuse() definition to fec_mxc.h Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> |
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7d8d0b1a |
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21-Aug-2011 |
Stefano Babic <sbabic@denx.de> |
MX5: make use of GPIO framework for MX5 processor Signed-off-by: Stefano Babic <sbabic@denx.de> |
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9db1bfa1 |
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13-Jul-2011 |
David Jander <david@protonic.nl> |
ARM: MX51: PLL errata workaround This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl> |
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0edf8b5b |
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06-Jul-2011 |
Stefano Babic <sbabic@denx.de> |
MX5: Update to autogenerated asm-offsets.h On i.MX5, the asm-offsets.h file is not yet generated as it should be. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de> |
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a6e961c2 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Introduce a function for setting the chip select size Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
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a682b3f7 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Add iomux structure Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
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ac4020e3 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Make the weim structure complete Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
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ac87c17d |
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19-Jan-2011 |
Stefano Babic <sbabic@denx.de> |
SPI: mxc_spi: replace fixed offsets with structures This patch cleans driver code replacing all accesses to registers with fixed offsets with a corresponding structure. Signed-off-by: Stefano Babic <sbabic@denx.de> |
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595f3e56 |
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03-Jan-2011 |
Liu Hui-R64343 <r64343@freescale.com> |
MX5: Add initial support for MX53 processor Add initial support for Freescale MX53 processor, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro Signed-off-by: Jason Liu <r64343@freescale.com> |
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565e39c5 |
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18-Nov-2010 |
Liu Hui-R64343 <r64343@freescale.com> |
imx: Get fec mac address from fuse The patch is to support getting FEC MAC address from fuse bank. Signed-off-by: Jason Liu <r64343@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> |
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1ab027cb |
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27-Oct-2010 |
Shawn Guo <shawn.gsc@gmail.com> |
mx51evk: support new relocation scheme This patch is to fix build breakage and support new relocation scheme for mx51evk. - Correct IRAM base address and add size definition The IRAM starts from 0x1FFE0000 on final revsion i.mx51 than 0x1FFE8000 which is for older revision. - Include imx-regs.h in mx51evk.h Definitions like CSD0_BASE_ADDR and IRAM_BASE_ADDR can be referred to. - Define CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE They are used to define init RAM layout. - Remove comment for CONFIG_SYS_GBL_DATA_SIZE which has been buried by Wolfgang's commit below 25ddd1fb: Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value Signed-off-by: Shawn Guo <shawn.gsc@gmail.com> |
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ff9f475d |
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17-Oct-2010 |
Jason Liu <r64343@freescale.com> |
MX5: rename mx51 to mx5 Rename mx51 to mx5 in order to support more mx51 like-style SOCs such as MX53 and the followings. Signed-off-by: Jason Liu <r64343@freescale.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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54d8d494 |
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08-Nov-2017 |
Martyn Welch <martyn.welch@collabora.co.uk> |
arm: mx5: Add more register definitions Add register definitions require for video configuration. Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Reviewed-by: Stefano Babic <sbabic@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> |
#
065a1ece |
|
08-Nov-2017 |
Martyn Welch <martyn.welch@collabora.co.uk> |
pwm: imx: Enable PWM support on i.MX53 Add missing parts for i.MX53 PWM support Acked-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> |
#
067716ba |
|
22-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Move SYS_CACHELINE_SIZE over to Kconfig This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr> |
#
fc5ad477 |
|
12-Oct-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: cpu: move common chip revision id's Move common chip revision id's to main cpu header file mx25 generic include cpu header for chip revision Signed-off-by: Adrian Alonso <aalonso@freescale.com> |
#
1005ccda |
|
02-Jun-2015 |
Chris Kuethe <chris.kuethe@gmail.com> |
patch - arm - define SYS_CACHELINE_SIZE for mx5 mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Matthew Starr <mstarr@hedonline.com> Cc: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
32c81ea6 |
|
14-Nov-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
imx: consolidate set_chipselect_size function Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
d7cbcc76 |
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17-Feb-2014 |
Markus Niebel <Markus.Niebel@tq-group.de> |
spi: spi-mxc: add defines for clk inactive state for ECSPI Provide define for the SCLK_CTL field of the config reg of ECSPI. While at it, oder the defines to improve readability and make adding more defines easier. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
6adbd302 |
|
23-Apr-2013 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
imx: Add useful fuse definitions Define the UID (SoC unique ID) fuses, and the fuses available for the user. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
#
8f3ff11c |
|
23-Apr-2013 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
imx: Homogenize and fix fuse register definitions IIM: - Homogenize prg_p naming (the reference manuals are not always self-consistent for that). - Add missing SCSx and bank registers. - Fix the number of banks on i.MX53. OCOTP: - Rename iim to ocotp in order to avoid confusion. - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the reference manual. - Merge the existing spinoff gp1 fuse definition on i.MX6. - Fix the number of banks on i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de> |
#
1155d555 |
|
24-Apr-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53ard: Move register masks into imx-regs.h imx-regs.h is more appropriate location for containing register masks. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> |
#
0f1411bc |
|
09-Apr-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
spi: mxc_spi: Set master mode for all channels The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
abbab703 |
|
22-Oct-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
mx31/mx35/mx51/mx53/mx6: add watchdog Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de> |
#
782b0288 |
|
14-Oct-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx5: lowlevel_init.S: Fix PLL settings for mx53 Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
362635bd |
|
17-Sep-2012 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
mx51evk: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
8e99ecd7 |
|
13-Aug-2012 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
mxc: Define architecture identifier Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> |
#
124a06d7 |
|
15-Aug-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
imx-common/cmd_bmode.c: add imx bmode (bootmode) command This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Note: MX53 support untested. Acked-by: Stefano Babic <sbabic@denx.de> |
#
df369dcd |
|
19-Jul-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
i.mx53: add definition for I2C3_BASE_ADDR Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> |
#
05d4df1d |
|
31-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Allow mx6 to access the IPUv3 registers Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
fff6ef72 |
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15-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53: Allow IPUv3 driver to also work on mx53 Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and mx53 SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
54cd1dee |
|
07-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53loco: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. The kernel uses this data to distinguish between Dialog versus mc34708 based boards, and also to distinguish between revA and revB of the mc34708 based boards. Suggested-by: Yu Li <yk@magniel.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> |
#
d87c85ce |
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21-Feb-2012 |
Stefano Babic <sbabic@denx.de> |
MX5: Add definitions for SATA controller Add base address and MXC_SATA_CLK to return the clock used for the SATA controller. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Dirk Behme <dirk.behme@de.bosch.com> |
#
4a9677e5 |
|
21-Feb-2012 |
Stefano Babic <sbabic@denx.de> |
Define UART4 and UART5 base addresses Signed-off-by: Stefano Babic <sbabic@denx.de> |
#
08c61a58 |
|
31-Jan-2012 |
Eric Nelson <eric.nelson@boundarydevices.com> |
mxc_spi: move machine specifics into CPU headers Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU Introduce two new macros to control conditional setup MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x) Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org> Tested-by: Jason Liu <jason.hui@linaro.org> |
#
40f6fffe |
|
22-Nov-2011 |
Stefano Babic <sbabic@denx.de> |
MX: serial_mxc: cleanup removing nasty #ifdef The serial driver for iMX SOCs is continuosly changed if a new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port> defines were used only to find the base address for the selected UART. Instead of that, move the base address to the board configuration file and drop all #ifdef from driver. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Helmut Raiger <helmut.raiger@hale.at> CC: John Rigby <jcrigby@gmail.com> CC: Matthias Weisser <weisserm@arcor.de> CC: Jason Liu <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linaro.org> |
#
bf2eaf51 |
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23-Sep-2011 |
Marek Vasut <marek.vasut@gmail.com> |
MX5: Modify the PLL decoding algorithm The PLL decoding algorithm didn't take into account many configuration bits. Adjust it according to Linux kernel. Also, add PLL4 for MX53. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Tested-by: Jason Liu <Jason.hui@linaro.org> |
#
8edcc6f2 |
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11-Sep-2011 |
Marek Vasut <marek.vasut@gmail.com> |
FEC: Move imx_get_mac_from_fuse() definition to fec_mxc.h Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> |
#
7d8d0b1a |
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21-Aug-2011 |
Stefano Babic <sbabic@denx.de> |
MX5: make use of GPIO framework for MX5 processor Signed-off-by: Stefano Babic <sbabic@denx.de> |
#
9db1bfa1 |
|
13-Jul-2011 |
David Jander <david@protonic.nl> |
ARM: MX51: PLL errata workaround This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl> |
#
0edf8b5b |
|
06-Jul-2011 |
Stefano Babic <sbabic@denx.de> |
MX5: Update to autogenerated asm-offsets.h On i.MX5, the asm-offsets.h file is not yet generated as it should be. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de> |
#
a6e961c2 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Introduce a function for setting the chip select size Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
a682b3f7 |
|
07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Add iomux structure Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
ac4020e3 |
|
07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Make the weim structure complete Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
#
ac87c17d |
|
19-Jan-2011 |
Stefano Babic <sbabic@denx.de> |
SPI: mxc_spi: replace fixed offsets with structures This patch cleans driver code replacing all accesses to registers with fixed offsets with a corresponding structure. Signed-off-by: Stefano Babic <sbabic@denx.de> |
#
595f3e56 |
|
03-Jan-2011 |
Liu Hui-R64343 <r64343@freescale.com> |
MX5: Add initial support for MX53 processor Add initial support for Freescale MX53 processor, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro Signed-off-by: Jason Liu <r64343@freescale.com> |
#
565e39c5 |
|
18-Nov-2010 |
Liu Hui-R64343 <r64343@freescale.com> |
imx: Get fec mac address from fuse The patch is to support getting FEC MAC address from fuse bank. Signed-off-by: Jason Liu <r64343@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> |
#
1ab027cb |
|
27-Oct-2010 |
Shawn Guo <shawn.gsc@gmail.com> |
mx51evk: support new relocation scheme This patch is to fix build breakage and support new relocation scheme for mx51evk. - Correct IRAM base address and add size definition The IRAM starts from 0x1FFE0000 on final revsion i.mx51 than 0x1FFE8000 which is for older revision. - Include imx-regs.h in mx51evk.h Definitions like CSD0_BASE_ADDR and IRAM_BASE_ADDR can be referred to. - Define CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE They are used to define init RAM layout. - Remove comment for CONFIG_SYS_GBL_DATA_SIZE which has been buried by Wolfgang's commit below 25ddd1fb: Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value Signed-off-by: Shawn Guo <shawn.gsc@gmail.com> |
#
ff9f475d |
|
17-Oct-2010 |
Jason Liu <r64343@freescale.com> |
MX5: rename mx51 to mx5 Rename mx51 to mx5 in order to support more mx51 like-style SOCs such as MX53 and the followings. Signed-off-by: Jason Liu <r64343@freescale.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
54d8d494 |
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08-Nov-2017 |
Martyn Welch <martyn.welch@collabora.co.uk> |
arm: mx5: Add more register definitions Add register definitions require for video configuration. Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Reviewed-by: Stefano Babic <sbabic@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
|
#
065a1ece |
|
08-Nov-2017 |
Martyn Welch <martyn.welch@collabora.co.uk> |
pwm: imx: Enable PWM support on i.MX53 Add missing parts for i.MX53 PWM support Acked-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
|
#
067716ba |
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22-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Move SYS_CACHELINE_SIZE over to Kconfig This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
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fc5ad477 |
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12-Oct-2015 |
Adrian Alonso <aalonso@freescale.com> |
imx: cpu: move common chip revision id's Move common chip revision id's to main cpu header file mx25 generic include cpu header for chip revision Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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1005ccda |
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02-Jun-2015 |
Chris Kuethe <chris.kuethe@gmail.com> |
patch - arm - define SYS_CACHELINE_SIZE for mx5 mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Matthew Starr <mstarr@hedonline.com> Cc: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
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32c81ea6 |
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14-Nov-2014 |
Fabio Estevam <fabio.estevam@freescale.com> |
imx: consolidate set_chipselect_size function Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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d7cbcc76 |
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17-Feb-2014 |
Markus Niebel <Markus.Niebel@tq-group.de> |
spi: spi-mxc: add defines for clk inactive state for ECSPI Provide define for the SCLK_CTL field of the config reg of ECSPI. While at it, oder the defines to improve readability and make adding more defines easier. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
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6adbd302 |
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23-Apr-2013 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
imx: Add useful fuse definitions Define the UID (SoC unique ID) fuses, and the fuses available for the user. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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8f3ff11c |
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23-Apr-2013 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
imx: Homogenize and fix fuse register definitions IIM: - Homogenize prg_p naming (the reference manuals are not always self-consistent for that). - Add missing SCSx and bank registers. - Fix the number of banks on i.MX53. OCOTP: - Rename iim to ocotp in order to avoid confusion. - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the reference manual. - Merge the existing spinoff gp1 fuse definition on i.MX6. - Fix the number of banks on i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de>
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1155d555 |
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24-Apr-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53ard: Move register masks into imx-regs.h imx-regs.h is more appropriate location for containing register masks. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
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0f1411bc |
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09-Apr-2013 |
Fabio Estevam <fabio.estevam@freescale.com> |
spi: mxc_spi: Set master mode for all channels The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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#
abbab703 |
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22-Oct-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
mx31/mx35/mx51/mx53/mx6: add watchdog Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
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782b0288 |
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14-Oct-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx5: lowlevel_init.S: Fix PLL settings for mx53 Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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362635bd |
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17-Sep-2012 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
mx51evk: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
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8e99ecd7 |
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13-Aug-2012 |
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
mxc: Define architecture identifier Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com>
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124a06d7 |
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15-Aug-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
imx-common/cmd_bmode.c: add imx bmode (bootmode) command This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Note: MX53 support untested. Acked-by: Stefano Babic <sbabic@denx.de>
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df369dcd |
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19-Jul-2012 |
Troy Kisky <troy.kisky@boundarydevices.com> |
i.mx53: add definition for I2C3_BASE_ADDR Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
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05d4df1d |
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31-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx6: Allow mx6 to access the IPUv3 registers Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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fff6ef72 |
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15-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53: Allow IPUv3 driver to also work on mx53 Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and mx53 SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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54cd1dee |
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07-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx53loco: Add CONFIG_REVISION_TAG FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. The kernel uses this data to distinguish between Dialog versus mc34708 based boards, and also to distinguish between revA and revB of the mc34708 based boards. Suggested-by: Yu Li <yk@magniel.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
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d87c85ce |
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21-Feb-2012 |
Stefano Babic <sbabic@denx.de> |
MX5: Add definitions for SATA controller Add base address and MXC_SATA_CLK to return the clock used for the SATA controller. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Dirk Behme <dirk.behme@de.bosch.com>
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4a9677e5 |
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21-Feb-2012 |
Stefano Babic <sbabic@denx.de> |
Define UART4 and UART5 base addresses Signed-off-by: Stefano Babic <sbabic@denx.de>
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08c61a58 |
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31-Jan-2012 |
Eric Nelson <eric.nelson@boundarydevices.com> |
mxc_spi: move machine specifics into CPU headers Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU Introduce two new macros to control conditional setup MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x) Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org> Tested-by: Jason Liu <jason.hui@linaro.org>
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40f6fffe |
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22-Nov-2011 |
Stefano Babic <sbabic@denx.de> |
MX: serial_mxc: cleanup removing nasty #ifdef The serial driver for iMX SOCs is continuosly changed if a new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port> defines were used only to find the base address for the selected UART. Instead of that, move the base address to the board configuration file and drop all #ifdef from driver. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Helmut Raiger <helmut.raiger@hale.at> CC: John Rigby <jcrigby@gmail.com> CC: Matthias Weisser <weisserm@arcor.de> CC: Jason Liu <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linaro.org>
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bf2eaf51 |
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23-Sep-2011 |
Marek Vasut <marek.vasut@gmail.com> |
MX5: Modify the PLL decoding algorithm The PLL decoding algorithm didn't take into account many configuration bits. Adjust it according to Linux kernel. Also, add PLL4 for MX53. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Tested-by: Jason Liu <Jason.hui@linaro.org>
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8edcc6f2 |
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11-Sep-2011 |
Marek Vasut <marek.vasut@gmail.com> |
FEC: Move imx_get_mac_from_fuse() definition to fec_mxc.h Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
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7d8d0b1a |
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21-Aug-2011 |
Stefano Babic <sbabic@denx.de> |
MX5: make use of GPIO framework for MX5 processor Signed-off-by: Stefano Babic <sbabic@denx.de>
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9db1bfa1 |
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13-Jul-2011 |
David Jander <david@protonic.nl> |
ARM: MX51: PLL errata workaround This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl>
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0edf8b5b |
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06-Jul-2011 |
Stefano Babic <sbabic@denx.de> |
MX5: Update to autogenerated asm-offsets.h On i.MX5, the asm-offsets.h file is not yet generated as it should be. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de>
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a6e961c2 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Introduce a function for setting the chip select size Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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a682b3f7 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Add iomux structure Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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ac4020e3 |
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07-Jun-2011 |
Fabio Estevam <fabio.estevam@freescale.com> |
MX5: Make the weim structure complete Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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ac87c17d |
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19-Jan-2011 |
Stefano Babic <sbabic@denx.de> |
SPI: mxc_spi: replace fixed offsets with structures This patch cleans driver code replacing all accesses to registers with fixed offsets with a corresponding structure. Signed-off-by: Stefano Babic <sbabic@denx.de>
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595f3e56 |
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03-Jan-2011 |
Liu Hui-R64343 <r64343@freescale.com> |
MX5: Add initial support for MX53 processor Add initial support for Freescale MX53 processor, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro Signed-off-by: Jason Liu <r64343@freescale.com>
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565e39c5 |
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18-Nov-2010 |
Liu Hui-R64343 <r64343@freescale.com> |
imx: Get fec mac address from fuse The patch is to support getting FEC MAC address from fuse bank. Signed-off-by: Jason Liu <r64343@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de>
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1ab027cb |
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27-Oct-2010 |
Shawn Guo <shawn.gsc@gmail.com> |
mx51evk: support new relocation scheme This patch is to fix build breakage and support new relocation scheme for mx51evk. - Correct IRAM base address and add size definition The IRAM starts from 0x1FFE0000 on final revsion i.mx51 than 0x1FFE8000 which is for older revision. - Include imx-regs.h in mx51evk.h Definitions like CSD0_BASE_ADDR and IRAM_BASE_ADDR can be referred to. - Define CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE They are used to define init RAM layout. - Remove comment for CONFIG_SYS_GBL_DATA_SIZE which has been buried by Wolfgang's commit below 25ddd1fb: Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value Signed-off-by: Shawn Guo <shawn.gsc@gmail.com>
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ff9f475d |
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17-Oct-2010 |
Jason Liu <r64343@freescale.com> |
MX5: rename mx51 to mx5 Rename mx51 to mx5 in order to support more mx51 like-style SOCs such as MX53 and the followings. Signed-off-by: Jason Liu <r64343@freescale.com>
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