1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2016 Freescale Semiconductors, Inc. 4 * 5 * I2CLP driver for i.MX 6 * 7 */ 8#ifndef __IMX_LPI2C_H__ 9#define __IMX_LPI2C_H__ 10 11#include <clk.h> 12 13struct imx_lpi2c_bus { 14 int index; 15 ulong base; 16 ulong driver_data; 17 int speed; 18 struct i2c_pads_info *pads_info; 19 struct udevice *bus; 20 struct clk per_clk; 21 struct clk ipg_clk; 22}; 23 24struct imx_lpi2c_reg { 25 u32 verid; 26 u32 param; 27 u8 reserved_0[8]; 28 u32 mcr; 29 u32 msr; 30 u32 mier; 31 u32 mder; 32 u32 mcfgr0; 33 u32 mcfgr1; 34 u32 mcfgr2; 35 u32 mcfgr3; 36 u8 reserved_1[16]; 37 u32 mdmr; 38 u8 reserved_2[4]; 39 u32 mccr0; 40 u8 reserved_3[4]; 41 u32 mccr1; 42 u8 reserved_4[4]; 43 u32 mfcr; 44 u32 mfsr; 45 u32 mtdr; 46 u8 reserved_5[12]; 47 u32 mrdr; 48 u8 reserved_6[156]; 49 u32 scr; 50 u32 ssr; 51 u32 sier; 52 u32 sder; 53 u8 reserved_7[4]; 54 u32 scfgr1; 55 u32 scfgr2; 56 u8 reserved_8[20]; 57 u32 samr; 58 u8 reserved_9[12]; 59 u32 sasr; 60 u32 star; 61 u8 reserved_10[8]; 62 u32 stdr; 63 u8 reserved_11[12]; 64 u32 srdr; 65}; 66 67typedef enum lpi2c_status { 68 LPI2C_SUCESS = 0, 69 LPI2C_END_PACKET_ERR, 70 LPI2C_STOP_ERR, 71 LPI2C_NAK_ERR, 72 LPI2C_ARB_LOST_ERR, 73 LPI2C_FIFO_ERR, 74 LPI2C_PIN_LOW_TIMEOUT_ERR, 75 LPI2C_DATA_MATCH_ERR, 76 LPI2C_BUSY, 77 LPI2C_IDLE, 78 LPI2C_BIT_ERR, 79 LPI2C_NO_TRANS_PROG, 80 LPI2C_DMA_REQ_FAIL, 81} lpi2c_status_t; 82 83/* ---------------------------------------------------------------------------- 84 -- LPI2C Register Masks 85 ---------------------------------------------------------------------------- */ 86 87/*! 88 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks 89 * @{ 90 */ 91 92/*! @name VERID - Version ID Register */ 93#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) 94#define LPI2C_VERID_FEATURE_SHIFT (0U) 95#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) 96#define LPI2C_VERID_MINOR_MASK (0xFF0000U) 97#define LPI2C_VERID_MINOR_SHIFT (16U) 98#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) 99#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) 100#define LPI2C_VERID_MAJOR_SHIFT (24U) 101#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) 102 103/*! @name PARAM - Parameter Register */ 104#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) 105#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) 106#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) 107#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) 108#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) 109#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) 110 111/*! @name MCR - Master Control Register */ 112#define LPI2C_MCR_MEN_MASK (0x1U) 113#define LPI2C_MCR_MEN_SHIFT (0U) 114#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) 115#define LPI2C_MCR_RST_MASK (0x2U) 116#define LPI2C_MCR_RST_SHIFT (1U) 117#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) 118#define LPI2C_MCR_DOZEN_MASK (0x4U) 119#define LPI2C_MCR_DOZEN_SHIFT (2U) 120#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) 121#define LPI2C_MCR_DBGEN_MASK (0x8U) 122#define LPI2C_MCR_DBGEN_SHIFT (3U) 123#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) 124#define LPI2C_MCR_RTF_MASK (0x100U) 125#define LPI2C_MCR_RTF_SHIFT (8U) 126#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) 127#define LPI2C_MCR_RRF_MASK (0x200U) 128#define LPI2C_MCR_RRF_SHIFT (9U) 129#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) 130 131/*! @name MSR - Master Status Register */ 132#define LPI2C_MSR_TDF_MASK (0x1U) 133#define LPI2C_MSR_TDF_SHIFT (0U) 134#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) 135#define LPI2C_MSR_RDF_MASK (0x2U) 136#define LPI2C_MSR_RDF_SHIFT (1U) 137#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) 138#define LPI2C_MSR_EPF_MASK (0x100U) 139#define LPI2C_MSR_EPF_SHIFT (8U) 140#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) 141#define LPI2C_MSR_SDF_MASK (0x200U) 142#define LPI2C_MSR_SDF_SHIFT (9U) 143#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) 144#define LPI2C_MSR_NDF_MASK (0x400U) 145#define LPI2C_MSR_NDF_SHIFT (10U) 146#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) 147#define LPI2C_MSR_ALF_MASK (0x800U) 148#define LPI2C_MSR_ALF_SHIFT (11U) 149#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) 150#define LPI2C_MSR_FEF_MASK (0x1000U) 151#define LPI2C_MSR_FEF_SHIFT (12U) 152#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) 153#define LPI2C_MSR_PLTF_MASK (0x2000U) 154#define LPI2C_MSR_PLTF_SHIFT (13U) 155#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) 156#define LPI2C_MSR_DMF_MASK (0x4000U) 157#define LPI2C_MSR_DMF_SHIFT (14U) 158#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) 159#define LPI2C_MSR_MBF_MASK (0x1000000U) 160#define LPI2C_MSR_MBF_SHIFT (24U) 161#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) 162#define LPI2C_MSR_BBF_MASK (0x2000000U) 163#define LPI2C_MSR_BBF_SHIFT (25U) 164#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) 165 166/*! @name MIER - Master Interrupt Enable Register */ 167#define LPI2C_MIER_TDIE_MASK (0x1U) 168#define LPI2C_MIER_TDIE_SHIFT (0U) 169#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) 170#define LPI2C_MIER_RDIE_MASK (0x2U) 171#define LPI2C_MIER_RDIE_SHIFT (1U) 172#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) 173#define LPI2C_MIER_EPIE_MASK (0x100U) 174#define LPI2C_MIER_EPIE_SHIFT (8U) 175#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) 176#define LPI2C_MIER_SDIE_MASK (0x200U) 177#define LPI2C_MIER_SDIE_SHIFT (9U) 178#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) 179#define LPI2C_MIER_NDIE_MASK (0x400U) 180#define LPI2C_MIER_NDIE_SHIFT (10U) 181#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) 182#define LPI2C_MIER_ALIE_MASK (0x800U) 183#define LPI2C_MIER_ALIE_SHIFT (11U) 184#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) 185#define LPI2C_MIER_FEIE_MASK (0x1000U) 186#define LPI2C_MIER_FEIE_SHIFT (12U) 187#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) 188#define LPI2C_MIER_PLTIE_MASK (0x2000U) 189#define LPI2C_MIER_PLTIE_SHIFT (13U) 190#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) 191#define LPI2C_MIER_DMIE_MASK (0x4000U) 192#define LPI2C_MIER_DMIE_SHIFT (14U) 193#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) 194 195/*! @name MDER - Master DMA Enable Register */ 196#define LPI2C_MDER_TDDE_MASK (0x1U) 197#define LPI2C_MDER_TDDE_SHIFT (0U) 198#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) 199#define LPI2C_MDER_RDDE_MASK (0x2U) 200#define LPI2C_MDER_RDDE_SHIFT (1U) 201#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) 202 203/*! @name MCFGR0 - Master Configuration Register 0 */ 204#define LPI2C_MCFGR0_HREN_MASK (0x1U) 205#define LPI2C_MCFGR0_HREN_SHIFT (0U) 206#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) 207#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) 208#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) 209#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) 210#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) 211#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) 212#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) 213#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) 214#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) 215#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) 216#define LPI2C_MCFGR0_RDMO_MASK (0x200U) 217#define LPI2C_MCFGR0_RDMO_SHIFT (9U) 218#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) 219 220/*! @name MCFGR1 - Master Configuration Register 1 */ 221#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) 222#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) 223#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) 224#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) 225#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) 226#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) 227#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) 228#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) 229#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) 230#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) 231#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) 232#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) 233#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) 234#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) 235#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) 236#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) 237#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) 238#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) 239 240/*! @name MCFGR2 - Master Configuration Register 2 */ 241#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) 242#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) 243#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) 244#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) 245#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) 246#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) 247#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) 248#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) 249#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) 250 251/*! @name MCFGR3 - Master Configuration Register 3 */ 252#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) 253#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) 254#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) 255 256/*! @name MDMR - Master Data Match Register */ 257#define LPI2C_MDMR_MATCH0_MASK (0xFFU) 258#define LPI2C_MDMR_MATCH0_SHIFT (0U) 259#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) 260#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) 261#define LPI2C_MDMR_MATCH1_SHIFT (16U) 262#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) 263 264/*! @name MCCR0 - Master Clock Configuration Register 0 */ 265#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) 266#define LPI2C_MCCR0_CLKLO_SHIFT (0U) 267#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) 268#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) 269#define LPI2C_MCCR0_CLKHI_SHIFT (8U) 270#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) 271#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) 272#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) 273#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) 274#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) 275#define LPI2C_MCCR0_DATAVD_SHIFT (24U) 276#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) 277 278/*! @name MCCR1 - Master Clock Configuration Register 1 */ 279#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) 280#define LPI2C_MCCR1_CLKLO_SHIFT (0U) 281#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) 282#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) 283#define LPI2C_MCCR1_CLKHI_SHIFT (8U) 284#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) 285#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) 286#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) 287#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) 288#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) 289#define LPI2C_MCCR1_DATAVD_SHIFT (24U) 290#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) 291 292/*! @name MFCR - Master FIFO Control Register */ 293#define LPI2C_MFCR_TXWATER_MASK (0xFFU) 294#define LPI2C_MFCR_TXWATER_SHIFT (0U) 295#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) 296#define LPI2C_MFCR_RXWATER_MASK (0xFF0000U) 297#define LPI2C_MFCR_RXWATER_SHIFT (16U) 298#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) 299 300/*! @name MFSR - Master FIFO Status Register */ 301#define LPI2C_MFSR_TXCOUNT_MASK (0xFFU) 302#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) 303#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) 304#define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U) 305#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) 306#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) 307 308/*! @name MTDR - Master Transmit Data Register */ 309#define LPI2C_MTDR_DATA_MASK (0xFFU) 310#define LPI2C_MTDR_DATA_SHIFT (0U) 311#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) 312#define LPI2C_MTDR_CMD_MASK (0x700U) 313#define LPI2C_MTDR_CMD_SHIFT (8U) 314#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) 315 316/*! @name MRDR - Master Receive Data Register */ 317#define LPI2C_MRDR_DATA_MASK (0xFFU) 318#define LPI2C_MRDR_DATA_SHIFT (0U) 319#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) 320#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) 321#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) 322#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) 323 324/*! @name SCR - Slave Control Register */ 325#define LPI2C_SCR_SEN_MASK (0x1U) 326#define LPI2C_SCR_SEN_SHIFT (0U) 327#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) 328#define LPI2C_SCR_RST_MASK (0x2U) 329#define LPI2C_SCR_RST_SHIFT (1U) 330#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) 331#define LPI2C_SCR_FILTEN_MASK (0x10U) 332#define LPI2C_SCR_FILTEN_SHIFT (4U) 333#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) 334#define LPI2C_SCR_FILTDZ_MASK (0x20U) 335#define LPI2C_SCR_FILTDZ_SHIFT (5U) 336#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) 337#define LPI2C_SCR_RTF_MASK (0x100U) 338#define LPI2C_SCR_RTF_SHIFT (8U) 339#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) 340#define LPI2C_SCR_RRF_MASK (0x200U) 341#define LPI2C_SCR_RRF_SHIFT (9U) 342#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) 343 344/*! @name SSR - Slave Status Register */ 345#define LPI2C_SSR_TDF_MASK (0x1U) 346#define LPI2C_SSR_TDF_SHIFT (0U) 347#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) 348#define LPI2C_SSR_RDF_MASK (0x2U) 349#define LPI2C_SSR_RDF_SHIFT (1U) 350#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) 351#define LPI2C_SSR_AVF_MASK (0x4U) 352#define LPI2C_SSR_AVF_SHIFT (2U) 353#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) 354#define LPI2C_SSR_TAF_MASK (0x8U) 355#define LPI2C_SSR_TAF_SHIFT (3U) 356#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) 357#define LPI2C_SSR_RSF_MASK (0x100U) 358#define LPI2C_SSR_RSF_SHIFT (8U) 359#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) 360#define LPI2C_SSR_SDF_MASK (0x200U) 361#define LPI2C_SSR_SDF_SHIFT (9U) 362#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) 363#define LPI2C_SSR_BEF_MASK (0x400U) 364#define LPI2C_SSR_BEF_SHIFT (10U) 365#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) 366#define LPI2C_SSR_FEF_MASK (0x800U) 367#define LPI2C_SSR_FEF_SHIFT (11U) 368#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) 369#define LPI2C_SSR_AM0F_MASK (0x1000U) 370#define LPI2C_SSR_AM0F_SHIFT (12U) 371#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) 372#define LPI2C_SSR_AM1F_MASK (0x2000U) 373#define LPI2C_SSR_AM1F_SHIFT (13U) 374#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) 375#define LPI2C_SSR_GCF_MASK (0x4000U) 376#define LPI2C_SSR_GCF_SHIFT (14U) 377#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) 378#define LPI2C_SSR_SARF_MASK (0x8000U) 379#define LPI2C_SSR_SARF_SHIFT (15U) 380#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) 381#define LPI2C_SSR_SBF_MASK (0x1000000U) 382#define LPI2C_SSR_SBF_SHIFT (24U) 383#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) 384#define LPI2C_SSR_BBF_MASK (0x2000000U) 385#define LPI2C_SSR_BBF_SHIFT (25U) 386#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) 387 388/*! @name SIER - Slave Interrupt Enable Register */ 389#define LPI2C_SIER_TDIE_MASK (0x1U) 390#define LPI2C_SIER_TDIE_SHIFT (0U) 391#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) 392#define LPI2C_SIER_RDIE_MASK (0x2U) 393#define LPI2C_SIER_RDIE_SHIFT (1U) 394#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) 395#define LPI2C_SIER_AVIE_MASK (0x4U) 396#define LPI2C_SIER_AVIE_SHIFT (2U) 397#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) 398#define LPI2C_SIER_TAIE_MASK (0x8U) 399#define LPI2C_SIER_TAIE_SHIFT (3U) 400#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) 401#define LPI2C_SIER_RSIE_MASK (0x100U) 402#define LPI2C_SIER_RSIE_SHIFT (8U) 403#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) 404#define LPI2C_SIER_SDIE_MASK (0x200U) 405#define LPI2C_SIER_SDIE_SHIFT (9U) 406#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) 407#define LPI2C_SIER_BEIE_MASK (0x400U) 408#define LPI2C_SIER_BEIE_SHIFT (10U) 409#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) 410#define LPI2C_SIER_FEIE_MASK (0x800U) 411#define LPI2C_SIER_FEIE_SHIFT (11U) 412#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) 413#define LPI2C_SIER_AM0IE_MASK (0x1000U) 414#define LPI2C_SIER_AM0IE_SHIFT (12U) 415#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) 416#define LPI2C_SIER_AM1F_MASK (0x2000U) 417#define LPI2C_SIER_AM1F_SHIFT (13U) 418#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) 419#define LPI2C_SIER_GCIE_MASK (0x4000U) 420#define LPI2C_SIER_GCIE_SHIFT (14U) 421#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) 422#define LPI2C_SIER_SARIE_MASK (0x8000U) 423#define LPI2C_SIER_SARIE_SHIFT (15U) 424#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) 425 426/*! @name SDER - Slave DMA Enable Register */ 427#define LPI2C_SDER_TDDE_MASK (0x1U) 428#define LPI2C_SDER_TDDE_SHIFT (0U) 429#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) 430#define LPI2C_SDER_RDDE_MASK (0x2U) 431#define LPI2C_SDER_RDDE_SHIFT (1U) 432#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) 433#define LPI2C_SDER_AVDE_MASK (0x4U) 434#define LPI2C_SDER_AVDE_SHIFT (2U) 435#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) 436 437/*! @name SCFGR1 - Slave Configuration Register 1 */ 438#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) 439#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) 440#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) 441#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) 442#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) 443#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) 444#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) 445#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) 446#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) 447#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) 448#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) 449#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) 450#define LPI2C_SCFGR1_GCEN_MASK (0x100U) 451#define LPI2C_SCFGR1_GCEN_SHIFT (8U) 452#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) 453#define LPI2C_SCFGR1_SAEN_MASK (0x200U) 454#define LPI2C_SCFGR1_SAEN_SHIFT (9U) 455#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) 456#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) 457#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) 458#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) 459#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) 460#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) 461#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) 462#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) 463#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) 464#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) 465#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) 466#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) 467#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) 468#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) 469#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) 470#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) 471 472/*! @name SCFGR2 - Slave Configuration Register 2 */ 473#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) 474#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) 475#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) 476#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) 477#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) 478#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) 479#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) 480#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) 481#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) 482#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) 483#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) 484#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) 485 486/*! @name SAMR - Slave Address Match Register */ 487#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) 488#define LPI2C_SAMR_ADDR0_SHIFT (1U) 489#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) 490#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) 491#define LPI2C_SAMR_ADDR1_SHIFT (17U) 492#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) 493 494/*! @name SASR - Slave Address Status Register */ 495#define LPI2C_SASR_RADDR_MASK (0x7FFU) 496#define LPI2C_SASR_RADDR_SHIFT (0U) 497#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) 498#define LPI2C_SASR_ANV_MASK (0x4000U) 499#define LPI2C_SASR_ANV_SHIFT (14U) 500#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) 501 502/*! @name STAR - Slave Transmit ACK Register */ 503#define LPI2C_STAR_TXNACK_MASK (0x1U) 504#define LPI2C_STAR_TXNACK_SHIFT (0U) 505#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) 506 507/*! @name STDR - Slave Transmit Data Register */ 508#define LPI2C_STDR_DATA_MASK (0xFFU) 509#define LPI2C_STDR_DATA_SHIFT (0U) 510#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) 511 512/*! @name SRDR - Slave Receive Data Register */ 513#define LPI2C_SRDR_DATA_MASK (0xFFU) 514#define LPI2C_SRDR_DATA_SHIFT (0U) 515#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) 516#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) 517#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) 518#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) 519#define LPI2C_SRDR_SOF_MASK (0x8000U) 520#define LPI2C_SRDR_SOF_SHIFT (15U) 521#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) 522 523#endif /* __ASM_ARCH_IMX_I2C_H__ */ 524