1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2008,2010 Freescale Semiconductor, Inc 4 * Andy Fleming 5 * 6 * Based (loosely) on the Linux code 7 */ 8 9#ifndef _MMC_H_ 10#define _MMC_H_ 11 12#include <linux/bitops.h> 13#include <linux/list.h> 14#include <linux/sizes.h> 15#include <linux/compiler.h> 16#include <linux/dma-direction.h> 17#include <part.h> 18 19struct bd_info; 20 21#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) 22#define MMC_SUPPORTS_TUNING 23#endif 24#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 25#define MMC_SUPPORTS_TUNING 26#endif 27 28/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ 29#define SD_VERSION_SD (1U << 31) 30#define MMC_VERSION_MMC (1U << 30) 31 32#define MAKE_SDMMC_VERSION(a, b, c) \ 33 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c)) 34#define MAKE_SD_VERSION(a, b, c) \ 35 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c)) 36#define MAKE_MMC_VERSION(a, b, c) \ 37 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c)) 38 39#define EXTRACT_SDMMC_MAJOR_VERSION(x) \ 40 (((u32)(x) >> 16) & 0xff) 41#define EXTRACT_SDMMC_MINOR_VERSION(x) \ 42 (((u32)(x) >> 8) & 0xff) 43#define EXTRACT_SDMMC_CHANGE_VERSION(x) \ 44 ((u32)(x) & 0xff) 45 46#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0) 47#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0) 48#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0) 49#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0) 50 51#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0) 52#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0) 53#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0) 54#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0) 55#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0) 56#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0) 57#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) 58#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) 59#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) 60#define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0) 61#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) 62#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) 63#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) 64#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) 65 66#define MMC_CAP(mode) (1 << mode) 67#define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS)) 68#define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52) 69#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52) 70#define MMC_MODE_HS200 MMC_CAP(MMC_HS_200) 71#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400) 72#define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES) 73 74#define MMC_CAP_NONREMOVABLE BIT(14) 75#define MMC_CAP_NEEDS_POLL BIT(15) 76#define MMC_CAP_CD_ACTIVE_HIGH BIT(16) 77 78#define MMC_MODE_8BIT BIT(30) 79#define MMC_MODE_4BIT BIT(29) 80#define MMC_MODE_1BIT BIT(28) 81#define MMC_MODE_SPI BIT(27) 82 83 84#define SD_DATA_4BIT 0x00040000 85 86#define IS_SD(x) ((x)->version & SD_VERSION_SD) 87#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC) 88 89#define MMC_DATA_READ 1 90#define MMC_DATA_WRITE 2 91 92#define MMC_CMD_GO_IDLE_STATE 0 93#define MMC_CMD_SEND_OP_COND 1 94#define MMC_CMD_ALL_SEND_CID 2 95#define MMC_CMD_SET_RELATIVE_ADDR 3 96#define MMC_CMD_SET_DSR 4 97#define MMC_CMD_SWITCH 6 98#define MMC_CMD_SELECT_CARD 7 99#define MMC_CMD_SEND_EXT_CSD 8 100#define MMC_CMD_SEND_CSD 9 101#define MMC_CMD_SEND_CID 10 102#define MMC_CMD_STOP_TRANSMISSION 12 103#define MMC_CMD_SEND_STATUS 13 104#define MMC_CMD_SET_BLOCKLEN 16 105#define MMC_CMD_READ_SINGLE_BLOCK 17 106#define MMC_CMD_READ_MULTIPLE_BLOCK 18 107#define MMC_CMD_SEND_TUNING_BLOCK 19 108#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21 109#define MMC_CMD_SET_BLOCK_COUNT 23 110#define MMC_CMD_WRITE_SINGLE_BLOCK 24 111#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 112#define MMC_CMD_ERASE_GROUP_START 35 113#define MMC_CMD_ERASE_GROUP_END 36 114#define MMC_CMD_ERASE 38 115#define MMC_CMD_APP_CMD 55 116#define MMC_CMD_SPI_READ_OCR 58 117#define MMC_CMD_SPI_CRC_ON_OFF 59 118#define MMC_CMD_RES_MAN 62 119 120#define MMC_CMD62_ARG1 0xefac62ec 121#define MMC_CMD62_ARG2 0xcbaea7 122 123 124#define SD_CMD_SEND_RELATIVE_ADDR 3 125#define SD_CMD_SWITCH_FUNC 6 126#define SD_CMD_SEND_IF_COND 8 127#define SD_CMD_SWITCH_UHS18V 11 128 129#define SD_CMD_APP_SET_BUS_WIDTH 6 130#define SD_CMD_APP_SD_STATUS 13 131#define SD_CMD_ERASE_WR_BLK_START 32 132#define SD_CMD_ERASE_WR_BLK_END 33 133#define SD_CMD_APP_SEND_OP_COND 41 134#define SD_CMD_APP_SEND_SCR 51 135 136static inline bool mmc_is_tuning_cmd(uint cmdidx) 137{ 138 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) || 139 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK)) 140 return true; 141 return false; 142} 143 144/* SCR definitions in different words */ 145#define SD_HIGHSPEED_BUSY 0x00020000 146#define SD_HIGHSPEED_SUPPORTED 0x00020000 147 148#define UHS_SDR12_BUS_SPEED 0 149#define HIGH_SPEED_BUS_SPEED 1 150#define UHS_SDR25_BUS_SPEED 1 151#define UHS_SDR50_BUS_SPEED 2 152#define UHS_SDR104_BUS_SPEED 3 153#define UHS_DDR50_BUS_SPEED 4 154 155#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED) 156#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED) 157#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED) 158#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED) 159#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED) 160 161#define OCR_BUSY 0x80000000 162#define OCR_HCS 0x40000000 163#define OCR_S18R 0x1000000 164#define OCR_VOLTAGE_MASK 0x007FFF80 165#define OCR_ACCESS_MODE 0x60000000 166 167#define MMC_ERASE_ARG 0x00000000 168#define MMC_SECURE_ERASE_ARG 0x80000000 169#define MMC_TRIM_ARG 0x00000001 170#define MMC_DISCARD_ARG 0x00000003 171#define MMC_SECURE_TRIM1_ARG 0x80000001 172#define MMC_SECURE_TRIM2_ARG 0x80008000 173 174#define MMC_STATUS_MASK (~0x0206BF7F) 175#define MMC_STATUS_SWITCH_ERROR (1 << 7) 176#define MMC_STATUS_RDY_FOR_DATA (1 << 8) 177#define MMC_STATUS_CURR_STATE (0xf << 9) 178#define MMC_STATUS_ERROR (1 << 19) 179 180#define MMC_STATE_PRG (7 << 9) 181#define MMC_STATE_TRANS (4 << 9) 182 183#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 184#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 185#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 186#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 187#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 188#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 189#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 190#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 191#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 192#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 193#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 194#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 195#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 196#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 197#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 198#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 199#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 200 201#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 202#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte 203 addressed by index which are 204 1 in value field */ 205#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte 206 addressed by index, which are 207 1 in value field */ 208#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ 209 210#define SD_SWITCH_CHECK 0 211#define SD_SWITCH_SWITCH 1 212 213/* 214 * EXT_CSD fields 215 */ 216#define EXT_CSD_ENH_START_ADDR 136 /* R/W */ 217#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ 218#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 219#define EXT_CSD_PARTITION_SETTING 155 /* R/W */ 220#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ 221#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ 222#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ 223#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 224#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */ 225#define EXT_CSD_WR_REL_PARAM 166 /* R */ 226#define EXT_CSD_WR_REL_SET 167 /* R/W */ 227#define EXT_CSD_RPMB_MULT 168 /* RO */ 228#define EXT_CSD_USER_WP 171 /* R/W & R/W/C_P & R/W/E_P */ 229#define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */ 230#define EXT_CSD_BOOT_WP_STATUS 174 /* R */ 231#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 232#define EXT_CSD_BOOT_BUS_WIDTH 177 233#define EXT_CSD_PART_CONF 179 /* R/W */ 234#define EXT_CSD_BUS_WIDTH 183 /* R/W */ 235#define EXT_CSD_STROBE_SUPPORT 184 /* R/W */ 236#define EXT_CSD_HS_TIMING 185 /* R/W */ 237#define EXT_CSD_REV 192 /* RO */ 238#define EXT_CSD_CARD_TYPE 196 /* RO */ 239#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */ 240#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 241#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 242#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 243#define EXT_CSD_BOOT_MULT 226 /* RO */ 244#define EXT_CSD_SEC_FEATURE 231 /* RO */ 245#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ 246#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ 247 248/* 249 * EXT_CSD field definitions 250 */ 251 252#define EXT_CSD_CMD_SET_NORMAL (1 << 0) 253#define EXT_CSD_CMD_SET_SECURE (1 << 1) 254#define EXT_CSD_CMD_SET_CPSECURE (1 << 2) 255 256#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ 257#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ 258#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) 259#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) 260#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ 261 | EXT_CSD_CARD_TYPE_DDR_1_2V) 262 263#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */ 264 /* SDR mode @1.8V I/O */ 265#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */ 266 /* SDR mode @1.2V I/O */ 267#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ 268 EXT_CSD_CARD_TYPE_HS200_1_2V) 269#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) 270#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) 271#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ 272 EXT_CSD_CARD_TYPE_HS400_1_2V) 273 274#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 275#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 276#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 277#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 278#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 279#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */ 280#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */ 281 282#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */ 283#define EXT_CSD_TIMING_HS 1 /* HS */ 284#define EXT_CSD_TIMING_HS200 2 /* HS200 */ 285#define EXT_CSD_TIMING_HS400 3 /* HS400 */ 286#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */ 287 288#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) 289#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) 290#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) 291#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) 292 293#define EXT_CSD_BOOT_ACK(x) (x << 6) 294#define EXT_CSD_BOOT_PART_NUM(x) (x << 3) 295#define EXT_CSD_PARTITION_ACCESS(x) (x << 0) 296 297#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1) 298#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7) 299#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7) 300 301#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) 302#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) 303#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) 304 305#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) 306 307#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ 308#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ 309 310#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ 311 312#define EXT_CSD_BOOT_WP_B_SEC_WP_SEL (0x80) /* enable partition selector */ 313#define EXT_CSD_BOOT_WP_B_PWR_WP_SEC_SEL (0x02) /* partition selector to protect */ 314#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01) /* power-on write-protect */ 315 316#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ 317#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ 318 319#define EXT_CSD_SEC_FEATURE_TRIM_EN (1 << 4) /* Support secure & insecure trim */ 320 321#define R1_ILLEGAL_COMMAND (1 << 22) 322#define R1_APP_CMD (1 << 5) 323 324#define MMC_RSP_PRESENT (1 << 0) 325#define MMC_RSP_136 (1 << 1) /* 136 bit response */ 326#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ 327#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ 328#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ 329 330#define MMC_RSP_NONE (0) 331#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 332#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ 333 MMC_RSP_BUSY) 334#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) 335#define MMC_RSP_R3 (MMC_RSP_PRESENT) 336#define MMC_RSP_R4 (MMC_RSP_PRESENT) 337#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 338#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 339#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 340 341#define MMCPART_NOAVAILABLE (0xff) 342#define PART_ACCESS_MASK (0x7) 343#define PART_SUPPORT (0x1) 344#define ENHNCD_SUPPORT (0x2) 345#define PART_ENH_ATTRIB (0x1f) 346 347#define MMC_QUIRK_RETRY_SEND_CID BIT(0) 348#define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1) 349#define MMC_QUIRK_RETRY_APP_CMD BIT(2) 350 351enum mmc_voltage { 352 MMC_SIGNAL_VOLTAGE_000 = 0, 353 MMC_SIGNAL_VOLTAGE_120 = 1, 354 MMC_SIGNAL_VOLTAGE_180 = 2, 355 MMC_SIGNAL_VOLTAGE_330 = 4, 356}; 357 358#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\ 359 MMC_SIGNAL_VOLTAGE_180 |\ 360 MMC_SIGNAL_VOLTAGE_330) 361 362/* Maximum block size for MMC */ 363#define MMC_MAX_BLOCK_LEN 512 364 365/* The number of MMC physical partitions. These consist of: 366 * boot partitions (2), general purpose partitions (4) in MMC v4.4. 367 */ 368#define MMC_NUM_BOOT_PARTITION 2 369#define MMC_PART_RPMB 3 /* RPMB partition number */ 370 371/* timing specification used */ 372#define MMC_TIMING_LEGACY 0 373#define MMC_TIMING_MMC_HS 1 374#define MMC_TIMING_SD_HS 2 375#define MMC_TIMING_UHS_SDR12 3 376#define MMC_TIMING_UHS_SDR25 4 377#define MMC_TIMING_UHS_SDR50 5 378#define MMC_TIMING_UHS_SDR104 6 379#define MMC_TIMING_UHS_DDR50 7 380#define MMC_TIMING_MMC_DDR52 8 381#define MMC_TIMING_MMC_HS200 9 382#define MMC_TIMING_MMC_HS400 10 383 384/* Driver model support */ 385 386/** 387 * struct mmc_uclass_priv - Holds information about a device used by the uclass 388 */ 389struct mmc_uclass_priv { 390 struct mmc *mmc; 391}; 392 393/** 394 * mmc_get_mmc_dev() - get the MMC struct pointer for a device 395 * 396 * Provided that the device is already probed and ready for use, this value 397 * will be available. 398 * 399 * @dev: Device 400 * Return: associated mmc struct pointer if available, else NULL 401 */ 402struct mmc *mmc_get_mmc_dev(const struct udevice *dev); 403 404/* End of driver model support */ 405 406struct mmc_cid { 407 unsigned long psn; 408 unsigned short oid; 409 unsigned char mid; 410 unsigned char prv; 411 unsigned char mdt; 412 char pnm[7]; 413}; 414 415struct mmc_cmd { 416 ushort cmdidx; 417 uint resp_type; 418 uint cmdarg; 419 uint response[4]; 420}; 421 422struct mmc_data { 423 union { 424 char *dest; 425 const char *src; /* src buffers don't get written to */ 426 }; 427 uint flags; 428 uint blocks; 429 uint blocksize; 430}; 431 432/* forward decl. */ 433struct mmc; 434 435#if CONFIG_IS_ENABLED(DM_MMC) 436struct dm_mmc_ops { 437 /** 438 * deferred_probe() - Some configurations that need to be deferred 439 * to just before enumerating the device 440 * 441 * @dev: Device to init 442 * @return 0 if Ok, -ve if error 443 */ 444 int (*deferred_probe)(struct udevice *dev); 445 /** 446 * reinit() - Re-initialization to clear old configuration for 447 * mmc rescan. 448 * 449 * @dev: Device to reinit 450 * @return 0 if Ok, -ve if error 451 */ 452 int (*reinit)(struct udevice *dev); 453 /** 454 * send_cmd() - Send a command to the MMC device 455 * 456 * @dev: Device to receive the command 457 * @cmd: Command to send 458 * @data: Additional data to send/receive 459 * @return 0 if OK, -ve on error 460 */ 461 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd, 462 struct mmc_data *data); 463 464 /** 465 * set_ios() - Set the I/O speed/width for an MMC device 466 * 467 * @dev: Device to update 468 * @return 0 if OK, -ve on error 469 */ 470 int (*set_ios)(struct udevice *dev); 471 472 /** 473 * get_cd() - See whether a card is present 474 * 475 * @dev: Device to check 476 * @return 0 if not present, 1 if present, -ve on error 477 */ 478 int (*get_cd)(struct udevice *dev); 479 480 /** 481 * get_wp() - See whether a card has write-protect enabled 482 * 483 * @dev: Device to check 484 * @return 0 if write-enabled, 1 if write-protected, -ve on error 485 */ 486 int (*get_wp)(struct udevice *dev); 487 488#ifdef MMC_SUPPORTS_TUNING 489 /** 490 * execute_tuning() - Start the tuning process 491 * 492 * @dev: Device to start the tuning 493 * @opcode: Command opcode to send 494 * @return 0 if OK, -ve on error 495 */ 496 int (*execute_tuning)(struct udevice *dev, uint opcode); 497#endif 498 499 /** 500 * wait_dat0() - wait until dat0 is in the target state 501 * (CLK must be running during the wait) 502 * 503 * @dev: Device to check 504 * @state: target state 505 * @timeout_us: timeout in us 506 * @return 0 if dat0 is in the target state, -ve on error 507 */ 508 int (*wait_dat0)(struct udevice *dev, int state, int timeout_us); 509 510#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 511 /* set_enhanced_strobe() - set HS400 enhanced strobe */ 512 int (*set_enhanced_strobe)(struct udevice *dev); 513#endif 514 515 /** 516 * host_power_cycle - host specific tasks in power cycle sequence 517 * Called between mmc_power_off() and 518 * mmc_power_on() 519 * 520 * @dev: Device to check 521 * @return 0 if not present, 1 if present, -ve on error 522 */ 523 int (*host_power_cycle)(struct udevice *dev); 524 525 /** 526 * get_b_max - get maximum length of single transfer 527 * Called before reading blocks from the card, 528 * useful for system which have e.g. DMA limits 529 * on various memory ranges. 530 * 531 * @dev: Device to check 532 * @dst: Destination buffer in memory 533 * @blkcnt: Total number of blocks in this transfer 534 * @return maximum number of blocks for this transfer 535 */ 536 int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt); 537 538 /** 539 * hs400_prepare_ddr - prepare to switch to DDR mode 540 * 541 * @dev: Device to check 542 * @return 0 if success, -ve on error 543 */ 544 int (*hs400_prepare_ddr)(struct udevice *dev); 545}; 546 547#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) 548 549/* Transition functions for compatibility */ 550int mmc_set_ios(struct mmc *mmc); 551int mmc_getcd(struct mmc *mmc); 552int mmc_getwp(struct mmc *mmc); 553int mmc_execute_tuning(struct mmc *mmc, uint opcode); 554int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us); 555int mmc_set_enhanced_strobe(struct mmc *mmc); 556int mmc_host_power_cycle(struct mmc *mmc); 557int mmc_deferred_probe(struct mmc *mmc); 558int mmc_reinit(struct mmc *mmc); 559int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt); 560int mmc_hs400_prepare_ddr(struct mmc *mmc); 561int mmc_send_stop_transmission(struct mmc *mmc, bool write); 562 563#else 564struct mmc_ops { 565 int (*send_cmd)(struct mmc *mmc, 566 struct mmc_cmd *cmd, struct mmc_data *data); 567 int (*set_ios)(struct mmc *mmc); 568 int (*init)(struct mmc *mmc); 569 int (*getcd)(struct mmc *mmc); 570 int (*getwp)(struct mmc *mmc); 571 int (*host_power_cycle)(struct mmc *mmc); 572 int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt); 573 int (*wait_dat0)(struct mmc *mmc, int state, int timeout_us); 574}; 575 576static inline int mmc_hs400_prepare_ddr(struct mmc *mmc) 577{ 578 return 0; 579} 580#endif 581 582struct mmc_config { 583 const char *name; 584#if !CONFIG_IS_ENABLED(DM_MMC) 585 const struct mmc_ops *ops; 586#endif 587 uint host_caps; 588 uint voltages; 589 uint f_min; 590 uint f_max; 591 uint b_max; 592 unsigned char part_type; 593#if CONFIG_IS_ENABLED(MMC_PWRSEQ) 594 struct udevice *pwr_dev; 595#endif 596}; 597 598struct sd_ssr { 599 unsigned int au; /* In sectors */ 600 unsigned int erase_timeout; /* In milliseconds */ 601 unsigned int erase_offset; /* In milliseconds */ 602}; 603 604enum bus_mode { 605 MMC_LEGACY, 606 MMC_HS, 607 SD_HS, 608 MMC_HS_52, 609 MMC_DDR_52, 610 UHS_SDR12, 611 UHS_SDR25, 612 UHS_SDR50, 613 UHS_DDR50, 614 UHS_SDR104, 615 MMC_HS_200, 616 MMC_HS_400, 617 MMC_HS_400_ES, 618 MMC_MODES_END 619}; 620 621const char *mmc_mode_name(enum bus_mode mode); 622void mmc_dump_capabilities(const char *text, uint caps); 623 624static inline bool mmc_is_mode_ddr(enum bus_mode mode) 625{ 626 if (mode == MMC_DDR_52) 627 return true; 628#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 629 else if (mode == UHS_DDR50) 630 return true; 631#endif 632#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 633 else if (mode == MMC_HS_400) 634 return true; 635#endif 636#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 637 else if (mode == MMC_HS_400_ES) 638 return true; 639#endif 640 else 641 return false; 642} 643 644#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \ 645 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \ 646 MMC_CAP(UHS_DDR50)) 647 648static inline bool supports_uhs(uint caps) 649{ 650#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 651 return (caps & UHS_CAPS) ? true : false; 652#else 653 return false; 654#endif 655} 656 657/* 658 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device 659 * with mmc_get_mmc_dev(). 660 * 661 * TODO struct mmc should be in mmc_private but it's hard to fix right now 662 */ 663struct mmc { 664#if !CONFIG_IS_ENABLED(BLK) 665 struct list_head link; 666#endif 667 const struct mmc_config *cfg; /* provided configuration */ 668 uint version; 669 void *priv; 670 uint has_init; 671 int high_capacity; 672 bool clk_disable; /* true if the clock can be turned off */ 673 uint bus_width; 674 uint clock; 675 uint saved_clock; 676 enum mmc_voltage signal_voltage; 677 uint card_caps; 678 uint host_caps; 679 uint ocr; 680 uint dsr; 681 uint dsr_imp; 682 uint scr[2]; 683 uint csd[4]; 684 uint cid[4]; 685 ushort rca; 686 u8 part_support; 687 u8 part_attr; 688 u8 wr_rel_set; 689 u8 part_config; 690 u8 gen_cmd6_time; /* units: 10 ms */ 691 u8 part_switch_time; /* units: 10 ms */ 692 uint tran_speed; 693 uint legacy_speed; /* speed for the legacy mode provided by the card */ 694 uint read_bl_len; 695 bool can_trim; 696#if CONFIG_IS_ENABLED(MMC_WRITE) 697 uint write_bl_len; 698 uint erase_grp_size; /* in 512-byte sectors */ 699#endif 700#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) 701 uint hc_wp_grp_size; /* in 512-byte sectors */ 702#endif 703#if CONFIG_IS_ENABLED(MMC_WRITE) 704 struct sd_ssr ssr; /* SD status register */ 705#endif 706 u64 capacity; 707 u64 capacity_user; 708 u64 capacity_boot; 709 u64 capacity_rpmb; 710 u64 capacity_gp[4]; 711#ifndef CONFIG_SPL_BUILD 712 u64 enh_user_start; 713 u64 enh_user_size; 714#endif 715#if !CONFIG_IS_ENABLED(BLK) 716 struct blk_desc block_dev; 717#endif 718 char op_cond_pending; /* 1 if we are waiting on an op_cond command */ 719 char init_in_progress; /* 1 if we have done mmc_start_init() */ 720 char preinit; /* start init as early as possible */ 721 int ddr_mode; 722#if CONFIG_IS_ENABLED(DM_MMC) 723 struct udevice *dev; /* Device for this MMC controller */ 724#if CONFIG_IS_ENABLED(DM_REGULATOR) 725 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/ 726 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/ 727#endif 728#endif 729 u8 *ext_csd; 730 u32 cardtype; /* cardtype read from the MMC */ 731 enum mmc_voltage current_voltage; 732 enum bus_mode selected_mode; /* mode currently used */ 733 enum bus_mode best_mode; /* best mode is the supported mode with the 734 * highest bandwidth. It may not always be the 735 * operating mode due to limitations when 736 * accessing the boot partitions 737 */ 738 u32 quirks; 739 bool tuning:1; 740 bool hs400_tuning:1; 741 742 enum bus_mode user_speed_mode; /* input speed mode from user */ 743}; 744 745#if CONFIG_IS_ENABLED(DM_MMC) 746#define mmc_to_dev(_mmc) _mmc->dev 747#else 748#define mmc_to_dev(_mmc) NULL 749#endif 750 751struct mmc_hwpart_conf { 752 struct { 753 uint enh_start; /* in 512-byte sectors */ 754 uint enh_size; /* in 512-byte sectors, if 0 no enh area */ 755 unsigned wr_rel_change : 1; 756 unsigned wr_rel_set : 1; 757 } user; 758 struct { 759 uint size; /* in 512-byte sectors */ 760 unsigned enhanced : 1; 761 unsigned wr_rel_change : 1; 762 unsigned wr_rel_set : 1; 763 } gp_part[4]; 764}; 765 766enum mmc_hwpart_conf_mode { 767 MMC_HWPART_CONF_CHECK, 768 MMC_HWPART_CONF_SET, 769 MMC_HWPART_CONF_COMPLETE, 770}; 771 772struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); 773 774/** 775 * mmc_bind() - Set up a new MMC device ready for probing 776 * 777 * A child block device is bound with the UCLASS_MMC interface type. This 778 * allows the device to be used with CONFIG_BLK 779 * 780 * @dev: MMC device to set up 781 * @mmc: MMC struct 782 * @cfg: MMC configuration 783 * Return: 0 if OK, -ve on error 784 */ 785int mmc_bind(struct udevice *dev, struct mmc *mmc, 786 const struct mmc_config *cfg); 787void mmc_destroy(struct mmc *mmc); 788 789/** 790 * mmc_unbind() - Unbind a MMC device's child block device 791 * 792 * @dev: MMC device 793 * Return: 0 if OK, -ve on error 794 */ 795int mmc_unbind(struct udevice *dev); 796int mmc_initialize(struct bd_info *bis); 797int mmc_init_device(int num); 798int mmc_init(struct mmc *mmc); 799int mmc_send_tuning(struct mmc *mmc, u32 opcode); 800int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data); 801int mmc_deinit(struct mmc *mmc); 802 803/** 804 * mmc_of_parse() - Parse the device tree to get the capabilities of the host 805 * 806 * @dev: MMC device 807 * @cfg: MMC configuration 808 * Return: 0 if OK, -ve on error 809 */ 810int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg); 811 812#if CONFIG_IS_ENABLED(MMC_PWRSEQ) 813/** 814 * mmc_pwrseq_get_power() - get a power device from device tree 815 * 816 * @dev: MMC device 817 * @cfg: MMC configuration 818 * Return: 0 if OK, -ve on error 819 */ 820int mmc_pwrseq_get_power(struct udevice *dev, struct mmc_config *cfg); 821#endif 822 823int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); 824 825/** 826 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV 827 * 828 * @voltage: The mmc_voltage to convert 829 * Return: the value in mV if OK, -EINVAL on error (invalid mmc_voltage value) 830 */ 831int mmc_voltage_to_mv(enum mmc_voltage voltage); 832 833/** 834 * mmc_set_clock() - change the bus clock 835 * @mmc: MMC struct 836 * @clock: bus frequency in Hz 837 * @disable: flag indicating if the clock must on or off 838 * Return: 0 if OK, -ve on error 839 */ 840int mmc_set_clock(struct mmc *mmc, uint clock, bool disable); 841 842#define MMC_CLK_ENABLE false 843#define MMC_CLK_DISABLE true 844 845struct mmc *find_mmc_device(int dev_num); 846int mmc_set_dev(int dev_num); 847void print_mmc_devices(char separator); 848 849/** 850 * get_mmc_num() - get the total MMC device number 851 * 852 * Return: 0 if there is no MMC device, else the number of devices 853 */ 854int get_mmc_num(void); 855int mmc_switch_part(struct mmc *mmc, unsigned int part_num); 856int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, 857 enum mmc_hwpart_conf_mode mode); 858 859#if !CONFIG_IS_ENABLED(DM_MMC) 860int mmc_getcd(struct mmc *mmc); 861int board_mmc_getcd(struct mmc *mmc); 862int mmc_getwp(struct mmc *mmc); 863int board_mmc_getwp(struct mmc *mmc); 864#endif 865 866int mmc_set_dsr(struct mmc *mmc, u16 val); 867/* Function to change the size of boot partition and rpmb partitions */ 868int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 869 unsigned long rpmbsize); 870/* Function to modify the PARTITION_CONFIG field of EXT_CSD */ 871int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); 872/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ 873int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); 874/* Function to modify the RST_n_FUNCTION field of EXT_CSD */ 875int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); 876/* Functions to read / write the RPMB partition */ 877int mmc_rpmb_set_key(struct mmc *mmc, void *key); 878int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); 879int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, 880 unsigned short cnt, unsigned char *key); 881int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, 882 unsigned short cnt, unsigned char *key); 883 884/** 885 * mmc_rpmb_route_frames() - route RPMB data frames 886 * @mmc Pointer to a MMC device struct 887 * @req Request data frames 888 * @reqlen Length of data frames in bytes 889 * @rsp Supplied buffer for response data frames 890 * @rsplen Length of supplied buffer for response data frames 891 * 892 * The RPMB data frames are routed to/from some external entity, for 893 * example a Trusted Exectuion Environment in an arm TrustZone protected 894 * secure world. It's expected that it's the external entity who is in 895 * control of the RPMB key. 896 * 897 * Returns 0 on success, < 0 on error. 898 */ 899int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen, 900 void *rsp, unsigned long rsplen); 901 902/** 903 * mmc_set_bkops_enable() - enable background operations 904 * @param mmc Pointer to a MMC device struct 905 * @param autobkops Enable automatic bkops, not manual bkops 906 * @param enable Enable bkops, not disable 907 * 908 * Enable or disable automatic or manual background operation of the eMMC. 909 * 910 * Return: 0 on success, <0 on error. 911 */ 912int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable); 913 914/** 915 * Start device initialization and return immediately; it does not block on 916 * polling OCR (operation condition register) status. Useful for checking 917 * the presence of SD/eMMC when no card detect logic is available. 918 * 919 * @param mmc Pointer to a MMC device struct 920 * @param quiet Be quiet, do not print error messages when card is not detected. 921 * Return: 0 on success, <0 on error. 922 */ 923int mmc_get_op_cond(struct mmc *mmc, bool quiet); 924 925/** 926 * Start device initialization and return immediately; it does not block on 927 * polling OCR (operation condition register) status. Then you should call 928 * mmc_init, which would block on polling OCR status and complete the device 929 * initializatin. 930 * 931 * @param mmc Pointer to a MMC device struct 932 * Return: 0 on success, <0 on error. 933 */ 934int mmc_start_init(struct mmc *mmc); 935 936/** 937 * Set preinit flag of mmc device. 938 * 939 * This will cause the device to be pre-inited during mmc_initialize(), 940 * which may save boot time if the device is not accessed until later. 941 * Some eMMC devices take 200-300ms to init, but unfortunately they 942 * must be sent a series of commands to even get them to start preparing 943 * for operation. 944 * 945 * @param mmc Pointer to a MMC device struct 946 * @param preinit preinit flag value 947 */ 948void mmc_set_preinit(struct mmc *mmc, int preinit); 949 950#ifdef CONFIG_MMC_SPI 951#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) 952#else 953#define mmc_host_is_spi(mmc) 0 954#endif 955 956#define mmc_dev(x) ((x)->dev) 957 958void board_mmc_power_init(void); 959int board_mmc_init(struct bd_info *bis); 960int cpu_mmc_init(struct bd_info *bis); 961int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); 962# ifdef CONFIG_SYS_MMC_ENV_PART 963extern uint mmc_get_env_part(struct mmc *mmc); 964# endif 965int mmc_get_env_dev(void); 966 967/* Minimum partition switch timeout in units of 10-milliseconds */ 968#define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */ 969 970/** 971 * mmc_get_blk_desc() - Get the block descriptor for an MMC device 972 * 973 * @mmc: MMC device 974 * Return: block descriptor if found, else NULL 975 */ 976struct blk_desc *mmc_get_blk_desc(struct mmc *mmc); 977 978/** 979 * mmc_get_blk() - Get the block device for an MMC device 980 * 981 * @dev: MMC device 982 * @blkp: Returns pointer to probed block device on sucesss 983 * 984 * Return: 0 on success, -ve on error 985 */ 986int mmc_get_blk(struct udevice *dev, struct udevice **blkp); 987 988/** 989 * mmc_send_ext_csd() - read the extended CSD register 990 * 991 * @mmc: MMC device 992 * @ext_csd a cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by 993 * the caller, e.g. using 994 * ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN) 995 * Return: 0 for success 996 */ 997int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd); 998 999/** 1000 * mmc_boot_wp() - power on write protect boot partitions 1001 * 1002 * The boot partitions are write protected until the next power cycle. 1003 * 1004 * Return: 0 for success 1005 */ 1006int mmc_boot_wp(struct mmc *mmc); 1007 1008/** 1009 * mmc_boot_wp_single_partition() - set write protection to a boot partition. 1010 * 1011 * This function sets a single boot partition to protect and leave the 1012 * other partition writable. 1013 * 1014 * @param mmc the mmc device. 1015 * @param partition 0 - first boot partition, 1 - second boot partition. 1016 * @return 0 for success 1017 */ 1018int mmc_boot_wp_single_partition(struct mmc *mmc, int partition); 1019 1020static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data) 1021{ 1022 return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 1023} 1024 1025#endif /* _MMC_H_ */ 1026