/u-boot/drivers/video/rockchip/ |
H A D | rk_mipi.h | 15 u32 ref_clk; member in struct:rk_mipi_priv
|
H A D | rk3399_mipi.c | 83 priv->ref_clk = 24 * MHz; 84 priv->sys_clk = priv->ref_clk;
|
H A D | rk3288_mipi.c | 91 priv->ref_clk = 24 * MHz; 92 priv->sys_clk = priv->ref_clk;
|
H A D | rk_mipi.c | 206 u32 refclk = priv->ref_clk;
|
/u-boot/board/k+p/kp_imx53/ |
H A D | kp_imx53.c | 78 u32 ref_clk = MXC_HCLK; local 82 ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK); 86 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 87 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
|
/u-boot/board/ge/mx53ppd/ |
H A D | mx53ppd.c | 104 u32 ref_clk = MXC_HCLK; local 109 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 115 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 116 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
|
/u-boot/drivers/phy/qcom/ |
H A D | phy-qcom-snps-eusb2.c | 127 struct clk *ref_clk; member in struct:qcom_snps_eusb2_phy_priv 175 unsigned long ref_clk_freq = clk_get_rate(qcom_snps_eusb2->ref_clk); 238 /* update ref_clk related registers */ 300 clk_prepare_enable(qcom_snps_eusb2->ref_clk); 318 clk_disable_unprepare(qcom_snps_eusb2->ref_clk); 332 qcom_snps_eusb2->ref_clk = devm_clk_get(dev, "ref"); 333 if (IS_ERR(qcom_snps_eusb2->ref_clk)) { 335 return PTR_ERR(qcom_snps_eusb2->ref_clk);
|
/u-boot/board/beckhoff/mx53cx9020/ |
H A D | mx53cx9020.c | 145 u32 ref_clk = MXC_HCLK; local 150 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 154 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 155 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
|
/u-boot/board/freescale/mx53loco/ |
H A D | mx53loco.c | 192 u32 ref_clk = MXC_HCLK; local 197 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 201 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 202 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
|
/u-boot/board/menlo/m53menlo/ |
H A D | m53menlo.c | 449 const u32 ref_clk = MXC_HCLK; local 462 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); 466 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); 472 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
|
/u-boot/drivers/phy/rockchip/ |
H A D | phy-rockchip-inno-dsidphy.c | 211 struct clk *ref_clk; member in struct:inno_dsidphy 311 * Upstream Linux tries to read the ref_clk, while the BSP 315 prate = clk_get_rate(inno->ref_clk); 545 clk_prepare_enable(inno->ref_clk); 580 clk_disable_unprepare(inno->ref_clk); 631 inno->ref_clk = devm_clk_get(dev, "ref"); 632 if (IS_ERR(inno->ref_clk)) { 633 ret = PTR_ERR(inno->ref_clk);
|
H A D | phy-rockchip-naneng-combphy.c | 83 struct clk ref_clk; member in struct:rockchip_combphy_priv 187 ret = clk_enable(&priv->ref_clk); 200 clk_disable(&priv->ref_clk); 209 clk_disable(&priv->ref_clk); 255 ret = clk_get_by_index(dev, 0, &priv->ref_clk); 258 return PTR_ERR(&priv->ref_clk); 464 clk_set_rate(&priv->ref_clk, 100000000);
|
/u-boot/board/inversepath/usbarmory/ |
H A D | usbarmory.c | 376 u32 ref_clk = MXC_HCLK; local 381 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); 385 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); 390 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
|
/u-boot/drivers/clk/ |
H A D | clk_versal.c | 111 static ulong ref_clk; variable 378 return ref_clk; 566 printf("pl_alt_ref_clk:%ld ref_clk:%ld\n", pl_alt_ref_clk, ref_clk); 688 ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk);
|
/u-boot/arch/arm/mach-imx/mx5/ |
H A D | clock.c | 69 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) 70 #define PLL_FREQ_MIN(ref_clk) \ 71 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
|
/u-boot/drivers/phy/ |
H A D | phy-mtk-tphy.c | 256 struct clk ref_clk; /* reference clock of (digital) phy */ member in struct:mtk_phy_instance 626 ret = clk_enable(&instance->ref_clk); 628 dev_err(tphy->dev, "failed to enable ref_clk\n"); 635 clk_disable(&instance->ref_clk); 693 clk_disable(&instance->ref_clk); 803 &instance->ref_clk);
|
/u-boot/drivers/spi/ |
H A D | cadence_qspi.h | 299 unsigned int ref_clk, unsigned int sclk_hz,
|
H A D | cadence_qspi_apb.c | 223 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__, 285 unsigned int ref_clk, unsigned int sclk_hz, 297 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk); 284 cadence_qspi_apb_delay(void *reg_base, unsigned int ref_clk, unsigned int sclk_hz, unsigned int tshsl_ns, unsigned int tsd2d_ns, unsigned int tchsh_ns, unsigned int tslch_ns) argument
|
/u-boot/drivers/usb/dwc3/ |
H A D | core.c | 138 if (dwc->ref_clk) { 139 rate = clk_get_rate(dwc->ref_clk); 647 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
|
H A D | core.h | 680 * @ref_clk: reference clock 780 struct clk *ref_clk; member in struct:dwc3
|
H A D | dwc3-generic.c | 84 index = ofnode_stringlist_search(node, "clock-names", "ref_clk"); 89 index = ofnode_stringlist_search(node, "clock-names", "ref_clk"); 92 dwc3->ref_clk = &glue->clks.clks[index];
|
/u-boot/drivers/net/ |
H A D | sja1105.c | 2028 struct sja1105_cgu_mii_ctrl ref_clk; local 2041 ref_clk.clksrc = clk_sources[port]; 2042 ref_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 2043 ref_clk.pd = 0; /* Power Down off => enabled */ 2044 sja1105_cgu_mii_control_packing(packed_buf, &ref_clk, PACK);
|
/u-boot/arch/mips/mach-octeon/ |
H A D | octeon_qlm.c | 3576 int ref_clk; local 3584 ref_clk = ref_clk_cn78xx[node][qlm][lane_mode]; 3585 clk_settings = &refclk_settings_cn78xx[lane_mode][ref_clk]; 3586 debug("%s(%d, %d): lane_mode: 0x%x, ref_clk: %d\n", __func__, node, qlm, lane_mode, 3587 ref_clk); 3591 __func__, ref_clk, lane_mode, qlm);
|