1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Eric Gao <eric.gao@rock-chips.com>
5 */
6
7#include <common.h>
8#include <clk.h>
9#include <display.h>
10#include <dm.h>
11#include <log.h>
12#include <panel.h>
13#include <regmap.h>
14#include "rk_mipi.h"
15#include <syscon.h>
16#include <asm/gpio.h>
17#include <dm/uclass-internal.h>
18#include <linux/err.h>
19#include <linux/kernel.h>
20#include <asm/arch-rockchip/clock.h>
21#include <asm/arch-rockchip/cru.h>
22#include <asm/arch-rockchip/grf_rk3399.h>
23#include <asm/arch-rockchip/hardware.h>
24#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
25
26/* Select mipi dsi source, big or little vop */
27static int rk_mipi_dsi_source_select(struct udevice *dev)
28{
29	struct rk_mipi_priv *priv = dev_get_priv(dev);
30	struct rk3399_grf_regs *grf = priv->grf;
31	struct display_plat *disp_uc_plat = dev_get_uclass_plat(dev);
32
33	/* Select the video source */
34	switch (disp_uc_plat->source_id) {
35	case VOP_B:
36		rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
37			     GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
38		break;
39	case VOP_L:
40		rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
41			     GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
42		break;
43	default:
44		debug("%s: Invalid VOP id\n", __func__);
45		return -EINVAL;
46	}
47
48	return 0;
49}
50
51/* Setup mipi dphy working mode */
52static void rk_mipi_dphy_mode_set(struct udevice *dev)
53{
54	struct rk_mipi_priv *priv = dev_get_priv(dev);
55	struct rk3399_grf_regs *grf = priv->grf;
56	int val;
57
58	/* Set Controller as TX mode */
59	val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
60	rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);
61
62	/* Exit tx stop mode */
63	val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;
64	rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);
65
66	/* Disable turnequest */
67	val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;
68	rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);
69}
70
71/*
72 * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
73 * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
74 * enable backlight.
75 */
76static int rk_display_enable(struct udevice *dev, int panel_bpp,
77			  const struct display_timing *timing)
78{
79	int ret;
80	struct rk_mipi_priv *priv = dev_get_priv(dev);
81
82	/* Fill the mipi controller parameter */
83	priv->ref_clk = 24 * MHz;
84	priv->sys_clk = priv->ref_clk;
85	priv->pix_clk = timing->pixelclock.typ;
86	priv->phy_clk = priv->pix_clk * 6;
87	priv->txbyte_clk = priv->phy_clk / 8;
88	priv->txesc_clk = 20 * MHz;
89
90	/* Select vop port, big or little */
91	rk_mipi_dsi_source_select(dev);
92
93	/* Set mipi dphy work mode */
94	rk_mipi_dphy_mode_set(dev);
95
96	/* Config  and enable mipi dsi according to timing */
97	ret = rk_mipi_dsi_enable(dev, timing);
98	if (ret) {
99		debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
100		      __func__, ret);
101		return ret;
102	}
103
104	/* Config and enable mipi phy */
105	ret = rk_mipi_phy_enable(dev);
106	if (ret) {
107		debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
108		      __func__, ret);
109		return ret;
110	}
111
112	/* Enable backlight */
113	ret = panel_enable_backlight(priv->panel);
114	if (ret) {
115		debug("%s: panel_enable_backlight() failed (err=%d)\n",
116		      __func__, ret);
117		return ret;
118	}
119
120	return 0;
121}
122
123static int rk_mipi_of_to_plat(struct udevice *dev)
124{
125	struct rk_mipi_priv *priv = dev_get_priv(dev);
126
127	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
128	if (IS_ERR_OR_NULL(priv->grf)) {
129		debug("%s: Get syscon grf failed (ret=%p)\n",
130		      __func__, priv->grf);
131		return  -ENXIO;
132	}
133	priv->regs = dev_read_addr(dev);
134	if (priv->regs == FDT_ADDR_T_NONE) {
135		debug("%s: Get MIPI dsi address failed\n", __func__);
136		return  -ENXIO;
137	}
138
139	return 0;
140}
141
142/*
143 * Probe function: check panel existence and readingit's timing. Then config
144 * mipi dsi controller and enable it according to the timing parameter.
145 */
146static int rk_mipi_probe(struct udevice *dev)
147{
148	int ret;
149	struct rk_mipi_priv *priv = dev_get_priv(dev);
150
151	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
152					   &priv->panel);
153	if (ret) {
154		debug("%s: Can not find panel (err=%d)\n", __func__, ret);
155		return ret;
156	}
157
158	return 0;
159}
160
161static const struct dm_display_ops rk_mipi_dsi_ops = {
162	.read_timing = rk_mipi_read_timing,
163	.enable = rk_display_enable,
164};
165
166static const struct udevice_id rk_mipi_dsi_ids[] = {
167	{ .compatible = "rockchip,rk3399-mipi-dsi" },
168	{ .compatible = "rockchip,rk3399_mipi_dsi" },
169	{ }
170};
171
172U_BOOT_DRIVER(rk_mipi_dsi) = {
173	.name	= "rk_mipi_dsi",
174	.id	= UCLASS_DISPLAY,
175	.of_match = rk_mipi_dsi_ids,
176	.of_to_plat = rk_mipi_of_to_plat,
177	.probe	= rk_mipi_probe,
178	.ops	= &rk_mipi_dsi_ops,
179	.priv_auto	  = sizeof(struct rk_mipi_priv),
180};
181