#
95b4d655 |
|
12-Apr-2024 |
Felipe Balbi <felipe.balbi@linux.intel.com> |
usb: dwc3: gadget: properly check ep cmd Upstream Linux commit 5999914f227b. The cmd argument we pass to dwc3_send_gadget_ep_cmd() could contain extra arguments embedded. When checking for StartTransfer command, we need to make sure to match only lower 4 bits which contain the actual command and ignore the rest. Reported-by: Janusz Dziedzic <januszx.dziedzic@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> [A. Sverdlin: cherry-picked only DWC3_DEPCMD_CMD() define] Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/20240412202611.3565052-6-alexander.sverdlin@siemens.com Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> |
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com> |
#
c55ac51a |
|
27-Nov-2022 |
Sean Anderson <sean.anderson@seco.com> |
usb: dwc3: Program GFLADJ GUCTL.REFCLKPER can only account for clock frequencies with integer periods. To address this, program REFCLK_FLADJ with the relative error caused by period truncation. The formula given in the register reference has been rearranged to allow calculation based on rate (instead of period), and to allow for fixed-point arithmetic. Additionally, calculate a value for 240MHZDECR. This configures a simulated 240Mhz clock using a counter with one fractional bit (PLS1). This register is programmed only for versions >= 2.50a, since this is the check also used by commit db2be4e9e30c ("usb: dwc3: Add frame length adjustment quirk"). [ marek: Ported from Linux kernel commit 596c87856e08d ("usb: dwc3: Program GFLADJ") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux |
#
57548e8b |
|
27-Nov-2022 |
Balaji Prakash J <bjagadee@codeaurora.org> |
usb: dwc3: reference clock period configuration Set reference clock period when it differs from dwc3 default hardware set. We could calculate clock period based on reference clock frequency. But this information is not always available. This is the case of PCI bus attached USB host. For that reason we use a custom property. Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference clock while hardware default is 19.2 MHz. [ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from property name; mention tested hardware ] [ marek: Ported from Linux kernel commit 7bee318838890 ("usb: dwc3: reference clock period configuration") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux |
#
8ae84e64 |
|
27-Nov-2022 |
Marek Vasut <marex@denx.de> |
usb: dwc3: Cache ref_clk pointer in struct dwc3 Cache ref_clk clock pointer in struct dwc3 . This is a preparatory patch for subsequent backports from Linux kernel which configure GFLADJ register content based on the ref_clk rate and therefore need access to the ref_clk pointer. It is possible to extract the clock pointer from existing clk_bulk list of already claimed clock, no need to call clk_get*() again. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> |
#
f150b8d2 |
|
15-Oct-2021 |
Michael Walle <michael@walle.cc> |
usb: dwc3: Enable undefined length INCR burst type [backport from linux commit d9612c2f0449e24983a8b689603210486a930c90] Enable the undefined length INCR burst type and set INCRx. Different platform may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d274cbbc |
|
15-Oct-2021 |
Michael Walle <michael@walle.cc> |
usb: dwc3: Add frame length adjustment quirk [backport from linux commit db2be4e9e30c6e43e48c5749d3fc74cee0a6bbb3] Add adjust_frame_length_quirk for writing to fladj register which adjusts (micro)frame length to value provided by "snps,quirk-frame-length-adjustment" property thus avoiding USB 2.0 devices to time-out over a longer run Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> |
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> |
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> |
#
23ba2d63 |
|
18-May-2018 |
Mugunthan V N <mugunthanvnm@ti.com> |
usb: dwc3: Add dwc3_init/remove with DM_USB The patch is preparing dwc3 core for enabling DM_USB with peripheral driver with using driver model support. The driver will be bound by the DWC3 wrapper driver based on the dr_mode device tree entry. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> (Remove dwc3-omap changes) Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7e9cb796 |
|
03-Mar-2015 |
Joonyoung Shim <jy0922.shim@samsung.com> |
usb: dwc3: make dwc3_set_mode to static This commit makes the dwc3_set_mode() as static, to prevent collisions. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> |
#
2252d150 |
|
03-Mar-2015 |
Ćukasz Majewski <l.majewski@samsung.com> |
usb: dwc3: Remove BIT(x) macro from DWC3's gadget code The BIT() macro is used only in those places, so it is reasonable to replace it by a constant value. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> |
#
793d347f |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: add support for multiple dwc3 controllers Added support for multiple dwc3 controllers. This gives uboot the capability to control multiple dwc3 controllers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
71744d0d |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: core: make dwc3 core build in uboot *) Changed the include header files to that used in u-boot. *) Removed phy_* APIs *) Removed jiffies and used a simple while loop *) Used dma_alloc_coherent and dma_free_coherent APIs of u-boot *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
b6d959ac |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: ep0: make dwc3 ep0 build in uboot *) Changed the included header files to that used in u-boot. *) added dwc3_ep_event_string() used in ep0.c *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
027b6103 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: remove pm related operations from dwc3 driver Removed all pm related operations including pm_runtime APIs, suspend/resume hooks as support for these are not present in u-boot. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
9848e574 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: fix dwc3 header files Changed the header files included in core.h and io.h to the u-boot header files so that these files can be included in other dwc3 source files and be compiled in uboot. Also added otg.h which has the defines for dr_mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
30c31d58 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: Modify the file headers to u-boot format Modified the file header to the format that is used in u-boot. Also included in the header, the commit in linux kernel from which each of these files are added. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
85d5e707 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: add dwc3 folder from linux kernel to u-boot Added dwc3 folder from linux kernel 3.19-rc1 (97bf6af1f9) to u-boot. This will be adapted to work with u-boot in the following patches. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com> |
#
c55ac51a |
|
27-Nov-2022 |
Sean Anderson <sean.anderson@seco.com> |
usb: dwc3: Program GFLADJ GUCTL.REFCLKPER can only account for clock frequencies with integer periods. To address this, program REFCLK_FLADJ with the relative error caused by period truncation. The formula given in the register reference has been rearranged to allow calculation based on rate (instead of period), and to allow for fixed-point arithmetic. Additionally, calculate a value for 240MHZDECR. This configures a simulated 240Mhz clock using a counter with one fractional bit (PLS1). This register is programmed only for versions >= 2.50a, since this is the check also used by commit db2be4e9e30c ("usb: dwc3: Add frame length adjustment quirk"). [ marek: Ported from Linux kernel commit 596c87856e08d ("usb: dwc3: Program GFLADJ") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux |
#
57548e8b |
|
27-Nov-2022 |
Balaji Prakash J <bjagadee@codeaurora.org> |
usb: dwc3: reference clock period configuration Set reference clock period when it differs from dwc3 default hardware set. We could calculate clock period based on reference clock frequency. But this information is not always available. This is the case of PCI bus attached USB host. For that reason we use a custom property. Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference clock while hardware default is 19.2 MHz. [ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from property name; mention tested hardware ] [ marek: Ported from Linux kernel commit 7bee318838890 ("usb: dwc3: reference clock period configuration") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux |
#
8ae84e64 |
|
27-Nov-2022 |
Marek Vasut <marex@denx.de> |
usb: dwc3: Cache ref_clk pointer in struct dwc3 Cache ref_clk clock pointer in struct dwc3 . This is a preparatory patch for subsequent backports from Linux kernel which configure GFLADJ register content based on the ref_clk rate and therefore need access to the ref_clk pointer. It is possible to extract the clock pointer from existing clk_bulk list of already claimed clock, no need to call clk_get*() again. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> |
#
f150b8d2 |
|
15-Oct-2021 |
Michael Walle <michael@walle.cc> |
usb: dwc3: Enable undefined length INCR burst type [backport from linux commit d9612c2f0449e24983a8b689603210486a930c90] Enable the undefined length INCR burst type and set INCRx. Different platform may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d274cbbc |
|
15-Oct-2021 |
Michael Walle <michael@walle.cc> |
usb: dwc3: Add frame length adjustment quirk [backport from linux commit db2be4e9e30c6e43e48c5749d3fc74cee0a6bbb3] Add adjust_frame_length_quirk for writing to fladj register which adjusts (micro)frame length to value provided by "snps,quirk-frame-length-adjustment" property thus avoiding USB 2.0 devices to time-out over a longer run Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> |
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> |
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> |
#
23ba2d63 |
|
18-May-2018 |
Mugunthan V N <mugunthanvnm@ti.com> |
usb: dwc3: Add dwc3_init/remove with DM_USB The patch is preparing dwc3 core for enabling DM_USB with peripheral driver with using driver model support. The driver will be bound by the DWC3 wrapper driver based on the dr_mode device tree entry. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> (Remove dwc3-omap changes) Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7e9cb796 |
|
03-Mar-2015 |
Joonyoung Shim <jy0922.shim@samsung.com> |
usb: dwc3: make dwc3_set_mode to static This commit makes the dwc3_set_mode() as static, to prevent collisions. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> |
#
2252d150 |
|
03-Mar-2015 |
Ćukasz Majewski <l.majewski@samsung.com> |
usb: dwc3: Remove BIT(x) macro from DWC3's gadget code The BIT() macro is used only in those places, so it is reasonable to replace it by a constant value. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> |
#
793d347f |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: add support for multiple dwc3 controllers Added support for multiple dwc3 controllers. This gives uboot the capability to control multiple dwc3 controllers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
71744d0d |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: core: make dwc3 core build in uboot *) Changed the include header files to that used in u-boot. *) Removed phy_* APIs *) Removed jiffies and used a simple while loop *) Used dma_alloc_coherent and dma_free_coherent APIs of u-boot *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
b6d959ac |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: ep0: make dwc3 ep0 build in uboot *) Changed the included header files to that used in u-boot. *) added dwc3_ep_event_string() used in ep0.c *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
027b6103 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: remove pm related operations from dwc3 driver Removed all pm related operations including pm_runtime APIs, suspend/resume hooks as support for these are not present in u-boot. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
9848e574 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: fix dwc3 header files Changed the header files included in core.h and io.h to the u-boot header files so that these files can be included in other dwc3 source files and be compiled in uboot. Also added otg.h which has the defines for dr_mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
30c31d58 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: Modify the file headers to u-boot format Modified the file header to the format that is used in u-boot. Also included in the header, the commit in linux kernel from which each of these files are added. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
85d5e707 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: add dwc3 folder from linux kernel to u-boot Added dwc3 folder from linux kernel 3.19-rc1 (97bf6af1f9) to u-boot. This will be adapted to work with u-boot in the following patches. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
c55ac51a |
|
27-Nov-2022 |
Sean Anderson <sean.anderson@seco.com> |
usb: dwc3: Program GFLADJ GUCTL.REFCLKPER can only account for clock frequencies with integer periods. To address this, program REFCLK_FLADJ with the relative error caused by period truncation. The formula given in the register reference has been rearranged to allow calculation based on rate (instead of period), and to allow for fixed-point arithmetic. Additionally, calculate a value for 240MHZDECR. This configures a simulated 240Mhz clock using a counter with one fractional bit (PLS1). This register is programmed only for versions >= 2.50a, since this is the check also used by commit db2be4e9e30c ("usb: dwc3: Add frame length adjustment quirk"). [ marek: Ported from Linux kernel commit 596c87856e08d ("usb: dwc3: Program GFLADJ") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux |
#
57548e8b |
|
27-Nov-2022 |
Balaji Prakash J <bjagadee@codeaurora.org> |
usb: dwc3: reference clock period configuration Set reference clock period when it differs from dwc3 default hardware set. We could calculate clock period based on reference clock frequency. But this information is not always available. This is the case of PCI bus attached USB host. For that reason we use a custom property. Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference clock while hardware default is 19.2 MHz. [ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from property name; mention tested hardware ] [ marek: Ported from Linux kernel commit 7bee318838890 ("usb: dwc3: reference clock period configuration") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux |
#
8ae84e64 |
|
27-Nov-2022 |
Marek Vasut <marex@denx.de> |
usb: dwc3: Cache ref_clk pointer in struct dwc3 Cache ref_clk clock pointer in struct dwc3 . This is a preparatory patch for subsequent backports from Linux kernel which configure GFLADJ register content based on the ref_clk rate and therefore need access to the ref_clk pointer. It is possible to extract the clock pointer from existing clk_bulk list of already claimed clock, no need to call clk_get*() again. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> |
#
f150b8d2 |
|
15-Oct-2021 |
Michael Walle <michael@walle.cc> |
usb: dwc3: Enable undefined length INCR burst type [backport from linux commit d9612c2f0449e24983a8b689603210486a930c90] Enable the undefined length INCR burst type and set INCRx. Different platform may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d274cbbc |
|
15-Oct-2021 |
Michael Walle <michael@walle.cc> |
usb: dwc3: Add frame length adjustment quirk [backport from linux commit db2be4e9e30c6e43e48c5749d3fc74cee0a6bbb3] Add adjust_frame_length_quirk for writing to fladj register which adjusts (micro)frame length to value provided by "snps,quirk-frame-length-adjustment" property thus avoiding USB 2.0 devices to time-out over a longer run Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> |
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> |
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> |
#
23ba2d63 |
|
18-May-2018 |
Mugunthan V N <mugunthanvnm@ti.com> |
usb: dwc3: Add dwc3_init/remove with DM_USB The patch is preparing dwc3 core for enabling DM_USB with peripheral driver with using driver model support. The driver will be bound by the DWC3 wrapper driver based on the dr_mode device tree entry. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> (Remove dwc3-omap changes) Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7e9cb796 |
|
03-Mar-2015 |
Joonyoung Shim <jy0922.shim@samsung.com> |
usb: dwc3: make dwc3_set_mode to static This commit makes the dwc3_set_mode() as static, to prevent collisions. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> |
#
2252d150 |
|
03-Mar-2015 |
Ćukasz Majewski <l.majewski@samsung.com> |
usb: dwc3: Remove BIT(x) macro from DWC3's gadget code The BIT() macro is used only in those places, so it is reasonable to replace it by a constant value. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> |
#
793d347f |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: add support for multiple dwc3 controllers Added support for multiple dwc3 controllers. This gives uboot the capability to control multiple dwc3 controllers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
71744d0d |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: core: make dwc3 core build in uboot *) Changed the include header files to that used in u-boot. *) Removed phy_* APIs *) Removed jiffies and used a simple while loop *) Used dma_alloc_coherent and dma_free_coherent APIs of u-boot *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
b6d959ac |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: ep0: make dwc3 ep0 build in uboot *) Changed the included header files to that used in u-boot. *) added dwc3_ep_event_string() used in ep0.c *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
027b6103 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: remove pm related operations from dwc3 driver Removed all pm related operations including pm_runtime APIs, suspend/resume hooks as support for these are not present in u-boot. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
9848e574 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: fix dwc3 header files Changed the header files included in core.h and io.h to the u-boot header files so that these files can be included in other dwc3 source files and be compiled in uboot. Also added otg.h which has the defines for dr_mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
30c31d58 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: Modify the file headers to u-boot format Modified the file header to the format that is used in u-boot. Also included in the header, the commit in linux kernel from which each of these files are added. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
85d5e707 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: add dwc3 folder from linux kernel to u-boot Added dwc3 folder from linux kernel 3.19-rc1 (97bf6af1f9) to u-boot. This will be adapted to work with u-boot in the following patches. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
f150b8d2 |
|
15-Oct-2021 |
Michael Walle <michael@walle.cc> |
usb: dwc3: Enable undefined length INCR burst type [backport from linux commit d9612c2f0449e24983a8b689603210486a930c90] Enable the undefined length INCR burst type and set INCRx. Different platform may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d274cbbc |
|
15-Oct-2021 |
Michael Walle <michael@walle.cc> |
usb: dwc3: Add frame length adjustment quirk [backport from linux commit db2be4e9e30c6e43e48c5749d3fc74cee0a6bbb3] Add adjust_frame_length_quirk for writing to fladj register which adjusts (micro)frame length to value provided by "snps,quirk-frame-length-adjustment" property thus avoiding USB 2.0 devices to time-out over a longer run Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> |
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> |
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> |
#
23ba2d63 |
|
18-May-2018 |
Mugunthan V N <mugunthanvnm@ti.com> |
usb: dwc3: Add dwc3_init/remove with DM_USB The patch is preparing dwc3 core for enabling DM_USB with peripheral driver with using driver model support. The driver will be bound by the DWC3 wrapper driver based on the dr_mode device tree entry. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> (Remove dwc3-omap changes) Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7e9cb796 |
|
03-Mar-2015 |
Joonyoung Shim <jy0922.shim@samsung.com> |
usb: dwc3: make dwc3_set_mode to static This commit makes the dwc3_set_mode() as static, to prevent collisions. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> |
#
2252d150 |
|
03-Mar-2015 |
Ćukasz Majewski <l.majewski@samsung.com> |
usb: dwc3: Remove BIT(x) macro from DWC3's gadget code The BIT() macro is used only in those places, so it is reasonable to replace it by a constant value. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> |
#
793d347f |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: add support for multiple dwc3 controllers Added support for multiple dwc3 controllers. This gives uboot the capability to control multiple dwc3 controllers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
71744d0d |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: core: make dwc3 core build in uboot *) Changed the include header files to that used in u-boot. *) Removed phy_* APIs *) Removed jiffies and used a simple while loop *) Used dma_alloc_coherent and dma_free_coherent APIs of u-boot *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
b6d959ac |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: ep0: make dwc3 ep0 build in uboot *) Changed the included header files to that used in u-boot. *) added dwc3_ep_event_string() used in ep0.c *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
027b6103 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: remove pm related operations from dwc3 driver Removed all pm related operations including pm_runtime APIs, suspend/resume hooks as support for these are not present in u-boot. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
9848e574 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: fix dwc3 header files Changed the header files included in core.h and io.h to the u-boot header files so that these files can be included in other dwc3 source files and be compiled in uboot. Also added otg.h which has the defines for dr_mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
30c31d58 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: Modify the file headers to u-boot format Modified the file header to the format that is used in u-boot. Also included in the header, the commit in linux kernel from which each of these files are added. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
85d5e707 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: add dwc3 folder from linux kernel to u-boot Added dwc3 folder from linux kernel 3.19-rc1 (97bf6af1f9) to u-boot. This will be adapted to work with u-boot in the following patches. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> |
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> |
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> |
#
23ba2d63 |
|
18-May-2018 |
Mugunthan V N <mugunthanvnm@ti.com> |
usb: dwc3: Add dwc3_init/remove with DM_USB The patch is preparing dwc3 core for enabling DM_USB with peripheral driver with using driver model support. The driver will be bound by the DWC3 wrapper driver based on the dr_mode device tree entry. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> (Remove dwc3-omap changes) Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7e9cb796 |
|
03-Mar-2015 |
Joonyoung Shim <jy0922.shim@samsung.com> |
usb: dwc3: make dwc3_set_mode to static This commit makes the dwc3_set_mode() as static, to prevent collisions. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> |
#
2252d150 |
|
03-Mar-2015 |
Ćukasz Majewski <l.majewski@samsung.com> |
usb: dwc3: Remove BIT(x) macro from DWC3's gadget code The BIT() macro is used only in those places, so it is reasonable to replace it by a constant value. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> |
#
793d347f |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: add support for multiple dwc3 controllers Added support for multiple dwc3 controllers. This gives uboot the capability to control multiple dwc3 controllers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
71744d0d |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: core: make dwc3 core build in uboot *) Changed the include header files to that used in u-boot. *) Removed phy_* APIs *) Removed jiffies and used a simple while loop *) Used dma_alloc_coherent and dma_free_coherent APIs of u-boot *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
b6d959ac |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: ep0: make dwc3 ep0 build in uboot *) Changed the included header files to that used in u-boot. *) added dwc3_ep_event_string() used in ep0.c *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
027b6103 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: remove pm related operations from dwc3 driver Removed all pm related operations including pm_runtime APIs, suspend/resume hooks as support for these are not present in u-boot. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
9848e574 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: fix dwc3 header files Changed the header files included in core.h and io.h to the u-boot header files so that these files can be included in other dwc3 source files and be compiled in uboot. Also added otg.h which has the defines for dr_mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
30c31d58 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: Modify the file headers to u-boot format Modified the file header to the format that is used in u-boot. Also included in the header, the commit in linux kernel from which each of these files are added. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
85d5e707 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: add dwc3 folder from linux kernel to u-boot Added dwc3 folder from linux kernel 3.19-rc1 (97bf6af1f9) to u-boot. This will be adapted to work with u-boot in the following patches. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
64697942 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: amend UTMI/UTMIW phy interface setup Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
fafaa022 |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Enable AutoRetry feature in the controller By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
5c207282 |
|
18-Dec-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Fix UTMI/UTMIW phy interface initialization DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
ba6c5f7a |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT Add a new function that read quirk and configuration information from the DT. The goal is to allow platforms using their own version of DWC3 driver to migrate to the generic DWC3 driver. The function is adapted from the function dwc3_get_properties() in the linux dwc3 driver introduced in commit c5ac6116db35d. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
33a99b43 |
|
11-Sep-2019 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit No one is actually implementing those functions. We could remove calls to these altogether, but it does not really hurt to keep the empty inlined version at the moment and it satisfies a symmetry with the gadget mode. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
fd09c205 |
|
21-Nov-2018 |
Sven Schwermer <sven@svenschwermer.de> |
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/ This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
|
#
23ba2d63 |
|
18-May-2018 |
Mugunthan V N <mugunthanvnm@ti.com> |
usb: dwc3: Add dwc3_init/remove with DM_USB The patch is preparing dwc3 core for enabling DM_USB with peripheral driver with using driver model support. The driver will be bound by the DWC3 wrapper driver based on the dr_mode device tree entry. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> (Remove dwc3-omap changes) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7e9cb796 |
|
03-Mar-2015 |
Joonyoung Shim <jy0922.shim@samsung.com> |
usb: dwc3: make dwc3_set_mode to static This commit makes the dwc3_set_mode() as static, to prevent collisions. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
|
#
2252d150 |
|
03-Mar-2015 |
Lukasz Majewski <l.majewski@samsung.com> |
usb: dwc3: Remove BIT(x) macro from DWC3's gadget code The BIT() macro is used only in those places, so it is reasonable to replace it by a constant value. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
|
#
793d347f |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: add support for multiple dwc3 controllers Added support for multiple dwc3 controllers. This gives uboot the capability to control multiple dwc3 controllers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
|
#
71744d0d |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: core: make dwc3 core build in uboot *) Changed the include header files to that used in u-boot. *) Removed phy_* APIs *) Removed jiffies and used a simple while loop *) Used dma_alloc_coherent and dma_free_coherent APIs of u-boot *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
|
#
b6d959ac |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: ep0: make dwc3 ep0 build in uboot *) Changed the included header files to that used in u-boot. *) added dwc3_ep_event_string() used in ep0.c *) Fixed other misc warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
|
#
027b6103 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: remove pm related operations from dwc3 driver Removed all pm related operations including pm_runtime APIs, suspend/resume hooks as support for these are not present in u-boot. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
|
#
9848e574 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: fix dwc3 header files Changed the header files included in core.h and io.h to the u-boot header files so that these files can be included in other dwc3 source files and be compiled in uboot. Also added otg.h which has the defines for dr_mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
|
#
30c31d58 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: Modify the file headers to u-boot format Modified the file header to the format that is used in u-boot. Also included in the header, the commit in linux kernel from which each of these files are added. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
|
#
85d5e707 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
usb: dwc3: add dwc3 folder from linux kernel to u-boot Added dwc3 folder from linux kernel 3.19-rc1 (97bf6af1f9) to u-boot. This will be adapted to work with u-boot in the following patches. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
|