#
b4b0228d |
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27-Jan-2024 |
Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> |
spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data The current implementation encounters issues when testing data ranging from 0 to 8 bytes. This was confirmed through testing with both ISSI (IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode. Upon investigation, it was observed that utilizing the "SPI_NOR_OCTAL_READ" flag and attempting to read less than 8 bytes in STIG mode results in a read failure, leading to a compare test failure. To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode. This is based on patch series: https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhumkar@amd.com/ Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c77efca2 |
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12-Sep-2023 |
Udit Kumar <u-kumar1@ti.com> |
spi: cadence_qspi: Select flash subnode at runtime Currently spi driver gets flash parameter from first subnode. Few boards have more than one flash with different parameters and selection of flash is done by on board switch settings. In such case, uboot needs to be recompiled with updated device tree to align with board switch settings. This patch allows to select flash node at runtime. Boards those are supporting multiple flashes needs to implement cadence_qspi_get_subnode function and return correct flash node. Cc: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f7d4cab1 |
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24-Aug-2022 |
Ashok Reddy Soma <ashok.reddy.soma@amd.com> |
spi: cadence-qspi: Use priv instead of plat across the driver As per driver model we should enumerate plat structure only in of_to_plat() and should be used only in probe(). Copy required plat structure info into priv structure in probe() and use priv structure across the driver. So replace plat with priv structure across the driver. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
248fe9f3 |
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12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence_qspi: Enable apb linear mode for apb read & write operations On versal platform, enable apb linear mode for apb read and write execute operations amd disable it when using dma reads. This is done by xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled, else we use direct raw reads and writes in case of mini U-Boot. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
bf8dae5f |
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12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence-qspi: reset qspi flash for versal platform When flash operated at non default mode like DDR, flash need to be reset to operate in SDR mode to read flash ids by spi-nor framework. Reset the flash to the default state before using the flash. This reset is handled by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we do raw read and write access by the registers. Versal platform utilizes spi calibration for read delay programming, so incase by default read delay property is set in DT. We make sure not to use read delay from DT by overwriting read_delay with -1. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
cf553bf2 |
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12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
arm64: versal: Add versal specific cadence ospi driver Add support for cadence ospi driver for Versal platform. This driver provides support for DMA read operation which utilizes cadence qspi driver. If "cdns,is-dma" DT property is specified use dma for read operation from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in cadence_ospi_versal driver add a weak function defination in cadence_qspi driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
1e2b8139 |
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12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence-qspi: move cadence qspi macros to header file Move all the cadence macros from cadence_qspi_apb.c to cadence_qspi.h file. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
55b3ba4c |
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30-Mar-2022 |
Tom Rini <trini@konsulko.com> |
spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e145606f |
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22-Feb-2022 |
Christian Gmeiner <christian.gmeiner@gmail.com> |
spi: cadence-qspi: Make reset control optional In the TI am65 device tree files there is no reset defined. Also the Linux kernel driver uses devm_reset_control_get_optional_exclusive(..) to get the reset. Lets do the same as the kernel does and make thr reset optinal. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
38b0852b |
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25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add support for octal DTR flashes Set up opcode extension and enable/disable DTR mode based on whether the command is DTR or not. xSPI flashes can have a 4-byte dummy address associated with some commands like the Read Status Register command in octal DTR mode. Since the flash does not support sending the dummy address, we can not use automatic write completion polling in DTR mode. Further, no write completion polling makes it impossible to use DAC mode for DTR writes. In that mode, the controller does not know beforehand how long a write will be and so it can de-assert Chip Select (CS#) at any time. Once CS# is de-assert, the flash will go into burning phase. But since the controller does not do write completion polling, it does not know when the flash is busy and might send in writes while the flash is not ready. So, disable write completion polling and make writes go through indirect mode for DTR writes and let spi-mem take care of polling the SR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a6903aa7 |
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25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add a small delay before indirect writes Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
bd8c8dcd |
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25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Do not calibrate when device tree sets read delay If the device tree provides a read delay value, use that directly and do not perform the calibration procedure. This allows the device tree to over-ride the read delay value in cases where the read delay value obtained via calibration is incorrect. One such example is the Cypress Semper flash. It needs a read delay of 4 in octal DTR mode. But since the calibration procedure is run before the flash is switched in octal DTR mode, it yields a read delay of 2. A value of 4 works for both octal DTR and legacy modes. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8a8d24bd |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ffab2121 |
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26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
d6407720 |
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26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
64c7c8c9 |
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20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
ac7e14ae |
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01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
7eece328 |
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26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
15a70a5d |
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23-Jan-2018 |
Jason Rush <jarush@gmail.com> |
spi: cadence_spi: Sync DT bindings with Linux Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de> |
#
7d403f28 |
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28-Nov-2016 |
Phil Edworthy <PHIL.EDWORTHY@renesas.com> |
spi: cadence_qspi: Use spi mode at the point it is needed Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2372e14f |
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05-Jul-2016 |
Vignesh R <vigneshr@ti.com> |
spi: cadence_quadspi: Enable QUAD mode based on DT data Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
98fbd71d |
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17-Oct-2015 |
Chin Liang See <clsee@altera.com> |
spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
90a2f717 |
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02-Jul-2015 |
Vikas Manocha <vikas.manocha@st.com> |
spi: cadence_qspi: get sram size from device tree sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com> |
#
10e8bf88 |
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06-Nov-2014 |
Stefan Roese <sr@denx.de> |
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> |
#
c77efca2 |
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12-Sep-2023 |
Udit Kumar <u-kumar1@ti.com> |
spi: cadence_qspi: Select flash subnode at runtime Currently spi driver gets flash parameter from first subnode. Few boards have more than one flash with different parameters and selection of flash is done by on board switch settings. In such case, uboot needs to be recompiled with updated device tree to align with board switch settings. This patch allows to select flash node at runtime. Boards those are supporting multiple flashes needs to implement cadence_qspi_get_subnode function and return correct flash node. Cc: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f7d4cab1 |
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24-Aug-2022 |
Ashok Reddy Soma <ashok.reddy.soma@amd.com> |
spi: cadence-qspi: Use priv instead of plat across the driver As per driver model we should enumerate plat structure only in of_to_plat() and should be used only in probe(). Copy required plat structure info into priv structure in probe() and use priv structure across the driver. So replace plat with priv structure across the driver. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
248fe9f3 |
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12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence_qspi: Enable apb linear mode for apb read & write operations On versal platform, enable apb linear mode for apb read and write execute operations amd disable it when using dma reads. This is done by xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled, else we use direct raw reads and writes in case of mini U-Boot. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
bf8dae5f |
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12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence-qspi: reset qspi flash for versal platform When flash operated at non default mode like DDR, flash need to be reset to operate in SDR mode to read flash ids by spi-nor framework. Reset the flash to the default state before using the flash. This reset is handled by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we do raw read and write access by the registers. Versal platform utilizes spi calibration for read delay programming, so incase by default read delay property is set in DT. We make sure not to use read delay from DT by overwriting read_delay with -1. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
cf553bf2 |
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12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
arm64: versal: Add versal specific cadence ospi driver Add support for cadence ospi driver for Versal platform. This driver provides support for DMA read operation which utilizes cadence qspi driver. If "cdns,is-dma" DT property is specified use dma for read operation from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in cadence_ospi_versal driver add a weak function defination in cadence_qspi driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
1e2b8139 |
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12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence-qspi: move cadence qspi macros to header file Move all the cadence macros from cadence_qspi_apb.c to cadence_qspi.h file. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
55b3ba4c |
|
30-Mar-2022 |
Tom Rini <trini@konsulko.com> |
spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e145606f |
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22-Feb-2022 |
Christian Gmeiner <christian.gmeiner@gmail.com> |
spi: cadence-qspi: Make reset control optional In the TI am65 device tree files there is no reset defined. Also the Linux kernel driver uses devm_reset_control_get_optional_exclusive(..) to get the reset. Lets do the same as the kernel does and make thr reset optinal. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
38b0852b |
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25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add support for octal DTR flashes Set up opcode extension and enable/disable DTR mode based on whether the command is DTR or not. xSPI flashes can have a 4-byte dummy address associated with some commands like the Read Status Register command in octal DTR mode. Since the flash does not support sending the dummy address, we can not use automatic write completion polling in DTR mode. Further, no write completion polling makes it impossible to use DAC mode for DTR writes. In that mode, the controller does not know beforehand how long a write will be and so it can de-assert Chip Select (CS#) at any time. Once CS# is de-assert, the flash will go into burning phase. But since the controller does not do write completion polling, it does not know when the flash is busy and might send in writes while the flash is not ready. So, disable write completion polling and make writes go through indirect mode for DTR writes and let spi-mem take care of polling the SR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a6903aa7 |
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25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add a small delay before indirect writes Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
bd8c8dcd |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Do not calibrate when device tree sets read delay If the device tree provides a read delay value, use that directly and do not perform the calibration procedure. This allows the device tree to over-ride the read delay value in cases where the read delay value obtained via calibration is incorrect. One such example is the Cypress Semper flash. It needs a read delay of 4 in octal DTR mode. But since the calibration procedure is run before the flash is switched in octal DTR mode, it yields a read delay of 2. A value of 4 works for both octal DTR and legacy modes. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ffab2121 |
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26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
15a70a5d |
|
23-Jan-2018 |
Jason Rush <jarush@gmail.com> |
spi: cadence_spi: Sync DT bindings with Linux Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de> |
#
7d403f28 |
|
28-Nov-2016 |
Phil Edworthy <PHIL.EDWORTHY@renesas.com> |
spi: cadence_qspi: Use spi mode at the point it is needed Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2372e14f |
|
05-Jul-2016 |
Vignesh R <vigneshr@ti.com> |
spi: cadence_quadspi: Enable QUAD mode based on DT data Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
98fbd71d |
|
17-Oct-2015 |
Chin Liang See <clsee@altera.com> |
spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
90a2f717 |
|
02-Jul-2015 |
Vikas Manocha <vikas.manocha@st.com> |
spi: cadence_qspi: get sram size from device tree sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com> |
#
10e8bf88 |
|
06-Nov-2014 |
Stefan Roese <sr@denx.de> |
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> |
#
f7d4cab1 |
|
24-Aug-2022 |
Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> |
spi: cadence-qspi: Use priv instead of plat across the driver As per driver model we should enumerate plat structure only in of_to_plat() and should be used only in probe(). Copy required plat structure info into priv structure in probe() and use priv structure across the driver. So replace plat with priv structure across the driver. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
248fe9f3 |
|
12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence_qspi: Enable apb linear mode for apb read & write operations On versal platform, enable apb linear mode for apb read and write execute operations amd disable it when using dma reads. This is done by xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled, else we use direct raw reads and writes in case of mini U-Boot. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
bf8dae5f |
|
12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence-qspi: reset qspi flash for versal platform When flash operated at non default mode like DDR, flash need to be reset to operate in SDR mode to read flash ids by spi-nor framework. Reset the flash to the default state before using the flash. This reset is handled by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we do raw read and write access by the registers. Versal platform utilizes spi calibration for read delay programming, so incase by default read delay property is set in DT. We make sure not to use read delay from DT by overwriting read_delay with -1. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
cf553bf2 |
|
12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
arm64: versal: Add versal specific cadence ospi driver Add support for cadence ospi driver for Versal platform. This driver provides support for DMA read operation which utilizes cadence qspi driver. If "cdns,is-dma" DT property is specified use dma for read operation from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in cadence_ospi_versal driver add a weak function defination in cadence_qspi driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
1e2b8139 |
|
12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence-qspi: move cadence qspi macros to header file Move all the cadence macros from cadence_qspi_apb.c to cadence_qspi.h file. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
55b3ba4c |
|
30-Mar-2022 |
Tom Rini <trini@konsulko.com> |
spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e145606f |
|
22-Feb-2022 |
Christian Gmeiner <christian.gmeiner@gmail.com> |
spi: cadence-qspi: Make reset control optional In the TI am65 device tree files there is no reset defined. Also the Linux kernel driver uses devm_reset_control_get_optional_exclusive(..) to get the reset. Lets do the same as the kernel does and make thr reset optinal. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
38b0852b |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add support for octal DTR flashes Set up opcode extension and enable/disable DTR mode based on whether the command is DTR or not. xSPI flashes can have a 4-byte dummy address associated with some commands like the Read Status Register command in octal DTR mode. Since the flash does not support sending the dummy address, we can not use automatic write completion polling in DTR mode. Further, no write completion polling makes it impossible to use DAC mode for DTR writes. In that mode, the controller does not know beforehand how long a write will be and so it can de-assert Chip Select (CS#) at any time. Once CS# is de-assert, the flash will go into burning phase. But since the controller does not do write completion polling, it does not know when the flash is busy and might send in writes while the flash is not ready. So, disable write completion polling and make writes go through indirect mode for DTR writes and let spi-mem take care of polling the SR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a6903aa7 |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add a small delay before indirect writes Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
bd8c8dcd |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Do not calibrate when device tree sets read delay If the device tree provides a read delay value, use that directly and do not perform the calibration procedure. This allows the device tree to over-ride the read delay value in cases where the read delay value obtained via calibration is incorrect. One such example is the Cypress Semper flash. It needs a read delay of 4 in octal DTR mode. But since the calibration procedure is run before the flash is switched in octal DTR mode, it yields a read delay of 2. A value of 4 works for both octal DTR and legacy modes. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
15a70a5d |
|
23-Jan-2018 |
Jason Rush <jarush@gmail.com> |
spi: cadence_spi: Sync DT bindings with Linux Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de> |
#
7d403f28 |
|
28-Nov-2016 |
Phil Edworthy <PHIL.EDWORTHY@renesas.com> |
spi: cadence_qspi: Use spi mode at the point it is needed Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2372e14f |
|
05-Jul-2016 |
Vignesh R <vigneshr@ti.com> |
spi: cadence_quadspi: Enable QUAD mode based on DT data Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
98fbd71d |
|
17-Oct-2015 |
Chin Liang See <clsee@altera.com> |
spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
90a2f717 |
|
02-Jul-2015 |
Vikas Manocha <vikas.manocha@st.com> |
spi: cadence_qspi: get sram size from device tree sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com> |
#
10e8bf88 |
|
06-Nov-2014 |
Stefan Roese <sr@denx.de> |
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> |
#
248fe9f3 |
|
12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence_qspi: Enable apb linear mode for apb read & write operations On versal platform, enable apb linear mode for apb read and write execute operations amd disable it when using dma reads. This is done by xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled, else we use direct raw reads and writes in case of mini U-Boot. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
bf8dae5f |
|
12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence-qspi: reset qspi flash for versal platform When flash operated at non default mode like DDR, flash need to be reset to operate in SDR mode to read flash ids by spi-nor framework. Reset the flash to the default state before using the flash. This reset is handled by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we do raw read and write access by the registers. Versal platform utilizes spi calibration for read delay programming, so incase by default read delay property is set in DT. We make sure not to use read delay from DT by overwriting read_delay with -1. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
cf553bf2 |
|
12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
arm64: versal: Add versal specific cadence ospi driver Add support for cadence ospi driver for Versal platform. This driver provides support for DMA read operation which utilizes cadence qspi driver. If "cdns,is-dma" DT property is specified use dma for read operation from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in cadence_ospi_versal driver add a weak function defination in cadence_qspi driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
1e2b8139 |
|
12-May-2022 |
T Karthik Reddy <t.karthik.reddy@xilinx.com> |
spi: cadence-qspi: move cadence qspi macros to header file Move all the cadence macros from cadence_qspi_apb.c to cadence_qspi.h file. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
55b3ba4c |
|
30-Mar-2022 |
Tom Rini <trini@konsulko.com> |
spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e145606f |
|
22-Feb-2022 |
Christian Gmeiner <christian.gmeiner@gmail.com> |
spi: cadence-qspi: Make reset control optional In the TI am65 device tree files there is no reset defined. Also the Linux kernel driver uses devm_reset_control_get_optional_exclusive(..) to get the reset. Lets do the same as the kernel does and make thr reset optinal. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
38b0852b |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add support for octal DTR flashes Set up opcode extension and enable/disable DTR mode based on whether the command is DTR or not. xSPI flashes can have a 4-byte dummy address associated with some commands like the Read Status Register command in octal DTR mode. Since the flash does not support sending the dummy address, we can not use automatic write completion polling in DTR mode. Further, no write completion polling makes it impossible to use DAC mode for DTR writes. In that mode, the controller does not know beforehand how long a write will be and so it can de-assert Chip Select (CS#) at any time. Once CS# is de-assert, the flash will go into burning phase. But since the controller does not do write completion polling, it does not know when the flash is busy and might send in writes while the flash is not ready. So, disable write completion polling and make writes go through indirect mode for DTR writes and let spi-mem take care of polling the SR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a6903aa7 |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add a small delay before indirect writes Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
bd8c8dcd |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Do not calibrate when device tree sets read delay If the device tree provides a read delay value, use that directly and do not perform the calibration procedure. This allows the device tree to over-ride the read delay value in cases where the read delay value obtained via calibration is incorrect. One such example is the Cypress Semper flash. It needs a read delay of 4 in octal DTR mode. But since the calibration procedure is run before the flash is switched in octal DTR mode, it yields a read delay of 2. A value of 4 works for both octal DTR and legacy modes. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
15a70a5d |
|
23-Jan-2018 |
Jason Rush <jarush@gmail.com> |
spi: cadence_spi: Sync DT bindings with Linux Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de> |
#
7d403f28 |
|
28-Nov-2016 |
Phil Edworthy <PHIL.EDWORTHY@renesas.com> |
spi: cadence_qspi: Use spi mode at the point it is needed Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2372e14f |
|
05-Jul-2016 |
Vignesh R <vigneshr@ti.com> |
spi: cadence_quadspi: Enable QUAD mode based on DT data Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
98fbd71d |
|
17-Oct-2015 |
Chin Liang See <clsee@altera.com> |
spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
90a2f717 |
|
02-Jul-2015 |
Vikas Manocha <vikas.manocha@st.com> |
spi: cadence_qspi: get sram size from device tree sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com> |
#
10e8bf88 |
|
06-Nov-2014 |
Stefan Roese <sr@denx.de> |
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> |
#
55b3ba4c |
|
30-Mar-2022 |
Tom Rini <trini@konsulko.com> |
spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e145606f |
|
22-Feb-2022 |
Christian Gmeiner <christian.gmeiner@gmail.com> |
spi: cadence-qspi: Make reset control optional In the TI am65 device tree files there is no reset defined. Also the Linux kernel driver uses devm_reset_control_get_optional_exclusive(..) to get the reset. Lets do the same as the kernel does and make thr reset optinal. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
38b0852b |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add support for octal DTR flashes Set up opcode extension and enable/disable DTR mode based on whether the command is DTR or not. xSPI flashes can have a 4-byte dummy address associated with some commands like the Read Status Register command in octal DTR mode. Since the flash does not support sending the dummy address, we can not use automatic write completion polling in DTR mode. Further, no write completion polling makes it impossible to use DAC mode for DTR writes. In that mode, the controller does not know beforehand how long a write will be and so it can de-assert Chip Select (CS#) at any time. Once CS# is de-assert, the flash will go into burning phase. But since the controller does not do write completion polling, it does not know when the flash is busy and might send in writes while the flash is not ready. So, disable write completion polling and make writes go through indirect mode for DTR writes and let spi-mem take care of polling the SR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a6903aa7 |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add a small delay before indirect writes Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
bd8c8dcd |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Do not calibrate when device tree sets read delay If the device tree provides a read delay value, use that directly and do not perform the calibration procedure. This allows the device tree to over-ride the read delay value in cases where the read delay value obtained via calibration is incorrect. One such example is the Cypress Semper flash. It needs a read delay of 4 in octal DTR mode. But since the calibration procedure is run before the flash is switched in octal DTR mode, it yields a read delay of 2. A value of 4 works for both octal DTR and legacy modes. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
15a70a5d |
|
23-Jan-2018 |
Jason Rush <jarush@gmail.com> |
spi: cadence_spi: Sync DT bindings with Linux Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de> |
#
7d403f28 |
|
28-Nov-2016 |
Phil Edworthy <PHIL.EDWORTHY@renesas.com> |
spi: cadence_qspi: Use spi mode at the point it is needed Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2372e14f |
|
05-Jul-2016 |
Vignesh R <vigneshr@ti.com> |
spi: cadence_quadspi: Enable QUAD mode based on DT data Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
98fbd71d |
|
17-Oct-2015 |
Chin Liang See <clsee@altera.com> |
spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
90a2f717 |
|
02-Jul-2015 |
Vikas Manocha <vikas.manocha@st.com> |
spi: cadence_qspi: get sram size from device tree sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com> |
#
10e8bf88 |
|
06-Nov-2014 |
Stefan Roese <sr@denx.de> |
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> |
#
e145606f |
|
22-Feb-2022 |
Christian Gmeiner <christian.gmeiner@gmail.com> |
spi: cadence-qspi: Make reset control optional In the TI am65 device tree files there is no reset defined. Also the Linux kernel driver uses devm_reset_control_get_optional_exclusive(..) to get the reset. Lets do the same as the kernel does and make thr reset optinal. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
38b0852b |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add support for octal DTR flashes Set up opcode extension and enable/disable DTR mode based on whether the command is DTR or not. xSPI flashes can have a 4-byte dummy address associated with some commands like the Read Status Register command in octal DTR mode. Since the flash does not support sending the dummy address, we can not use automatic write completion polling in DTR mode. Further, no write completion polling makes it impossible to use DAC mode for DTR writes. In that mode, the controller does not know beforehand how long a write will be and so it can de-assert Chip Select (CS#) at any time. Once CS# is de-assert, the flash will go into burning phase. But since the controller does not do write completion polling, it does not know when the flash is busy and might send in writes while the flash is not ready. So, disable write completion polling and make writes go through indirect mode for DTR writes and let spi-mem take care of polling the SR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a6903aa7 |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add a small delay before indirect writes Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
bd8c8dcd |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Do not calibrate when device tree sets read delay If the device tree provides a read delay value, use that directly and do not perform the calibration procedure. This allows the device tree to over-ride the read delay value in cases where the read delay value obtained via calibration is incorrect. One such example is the Cypress Semper flash. It needs a read delay of 4 in octal DTR mode. But since the calibration procedure is run before the flash is switched in octal DTR mode, it yields a read delay of 2. A value of 4 works for both octal DTR and legacy modes. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
15a70a5d |
|
23-Jan-2018 |
Jason Rush <jarush@gmail.com> |
spi: cadence_spi: Sync DT bindings with Linux Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de> |
#
7d403f28 |
|
28-Nov-2016 |
Phil Edworthy <PHIL.EDWORTHY@renesas.com> |
spi: cadence_qspi: Use spi mode at the point it is needed Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2372e14f |
|
05-Jul-2016 |
Vignesh R <vigneshr@ti.com> |
spi: cadence_quadspi: Enable QUAD mode based on DT data Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
98fbd71d |
|
17-Oct-2015 |
Chin Liang See <clsee@altera.com> |
spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
90a2f717 |
|
02-Jul-2015 |
Vikas Manocha <vikas.manocha@st.com> |
spi: cadence_qspi: get sram size from device tree sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com> |
#
10e8bf88 |
|
06-Nov-2014 |
Stefan Roese <sr@denx.de> |
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> |
#
38b0852b |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add support for octal DTR flashes Set up opcode extension and enable/disable DTR mode based on whether the command is DTR or not. xSPI flashes can have a 4-byte dummy address associated with some commands like the Read Status Register command in octal DTR mode. Since the flash does not support sending the dummy address, we can not use automatic write completion polling in DTR mode. Further, no write completion polling makes it impossible to use DAC mode for DTR writes. In that mode, the controller does not know beforehand how long a write will be and so it can de-assert Chip Select (CS#) at any time. Once CS# is de-assert, the flash will go into burning phase. But since the controller does not do write completion polling, it does not know when the flash is busy and might send in writes while the flash is not ready. So, disable write completion polling and make writes go through indirect mode for DTR writes and let spi-mem take care of polling the SR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a6903aa7 |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Add a small delay before indirect writes Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
bd8c8dcd |
|
25-Jun-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-qspi: Do not calibrate when device tree sets read delay If the device tree provides a read delay value, use that directly and do not perform the calibration procedure. This allows the device tree to over-ride the read delay value in cases where the read delay value obtained via calibration is incorrect. One such example is the Cypress Semper flash. It needs a read delay of 4 in octal DTR mode. But since the calibration procedure is run before the flash is switched in octal DTR mode, it yields a read delay of 2. A value of 4 works for both octal DTR and legacy modes. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> |
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
15a70a5d |
|
23-Jan-2018 |
Jason Rush <jarush@gmail.com> |
spi: cadence_spi: Sync DT bindings with Linux Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de> |
#
7d403f28 |
|
28-Nov-2016 |
Phil Edworthy <PHIL.EDWORTHY@renesas.com> |
spi: cadence_qspi: Use spi mode at the point it is needed Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2372e14f |
|
05-Jul-2016 |
Vignesh R <vigneshr@ti.com> |
spi: cadence_quadspi: Enable QUAD mode based on DT data Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
98fbd71d |
|
17-Oct-2015 |
Chin Liang See <clsee@altera.com> |
spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> |
#
90a2f717 |
|
02-Jul-2015 |
Vikas Manocha <vikas.manocha@st.com> |
spi: cadence_qspi: get sram size from device tree sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com> |
#
10e8bf88 |
|
06-Nov-2014 |
Stefan Roese <sr@denx.de> |
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ffab2121 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence-qspi: Add direct mode support Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
d6407720 |
|
26-Jan-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: cadence_qspi: Move to spi-mem framework Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
64c7c8c9 |
|
20-Nov-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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#
ac7e14ae |
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01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
|
#
ac7e14ae |
|
01-Mar-2019 |
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
spi: cadence_qspi: add reset handling This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
|
#
7eece328 |
|
26-Feb-2019 |
Ley Foon Tan <ley.foon.tan@intel.com> |
spi: cadence_qspi: Add quad write support Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
15a70a5d |
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23-Jan-2018 |
Jason Rush <jarush@gmail.com> |
spi: cadence_spi: Sync DT bindings with Linux Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
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#
7d403f28 |
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28-Nov-2016 |
Phil Edworthy <PHIL.EDWORTHY@renesas.com> |
spi: cadence_qspi: Use spi mode at the point it is needed Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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#
2372e14f |
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05-Jul-2016 |
Vignesh R <vigneshr@ti.com> |
spi: cadence_quadspi: Enable QUAD mode based on DT data Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
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#
98fbd71d |
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17-Oct-2015 |
Chin Liang See <clsee@altera.com> |
spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
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#
90a2f717 |
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02-Jul-2015 |
Vikas Manocha <vikas.manocha@st.com> |
spi: cadence_qspi: get sram size from device tree sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
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#
10e8bf88 |
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06-Nov-2014 |
Stefan Roese <sr@denx.de> |
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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