1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 6 */ 7 8#include <dm.h> 9#include <dm/device_compat.h> 10#include <dm/devres.h> 11#include <div64.h> 12#include <generic-phy.h> 13#include <linux/kernel.h> 14#include <linux/iopoll.h> 15#include <linux/clk-provider.h> 16#include <linux/delay.h> 17#include <linux/math64.h> 18#include <linux/time.h> 19#include <phy-mipi-dphy.h> 20#include <reset.h> 21 22#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 23 24/* 25 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5 26 * is the first address, the other from the bit4 to bit0 is the second address. 27 * when you configure the registers, you must set both of them. The Clock Lane 28 * and Data Lane use the same registers with the same second address, but the 29 * first address is different. 30 */ 31#define FIRST_ADDRESS(x) (((x) & 0x7) << 5) 32#define SECOND_ADDRESS(x) (((x) & 0x1f) << 0) 33#define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ 34 SECOND_ADDRESS(second)) 35 36/* Analog Register Part: reg00 */ 37#define BANDGAP_POWER_MASK BIT(7) 38#define BANDGAP_POWER_DOWN BIT(7) 39#define BANDGAP_POWER_ON 0 40#define LANE_EN_MASK GENMASK(6, 2) 41#define LANE_EN_CK BIT(6) 42#define LANE_EN_3 BIT(5) 43#define LANE_EN_2 BIT(4) 44#define LANE_EN_1 BIT(3) 45#define LANE_EN_0 BIT(2) 46#define POWER_WORK_MASK GENMASK(1, 0) 47#define POWER_WORK_ENABLE UPDATE(1, 1, 0) 48#define POWER_WORK_DISABLE UPDATE(2, 1, 0) 49/* Analog Register Part: reg01 */ 50#define REG_SYNCRST_MASK BIT(2) 51#define REG_SYNCRST_RESET BIT(2) 52#define REG_SYNCRST_NORMAL 0 53#define REG_LDOPD_MASK BIT(1) 54#define REG_LDOPD_POWER_DOWN BIT(1) 55#define REG_LDOPD_POWER_ON 0 56#define REG_PLLPD_MASK BIT(0) 57#define REG_PLLPD_POWER_DOWN BIT(0) 58#define REG_PLLPD_POWER_ON 0 59/* Analog Register Part: reg03 */ 60#define REG_FBDIV_HI_MASK BIT(5) 61#define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5) 62#define REG_PREDIV_MASK GENMASK(4, 0) 63#define REG_PREDIV(x) UPDATE(x, 4, 0) 64/* Analog Register Part: reg04 */ 65#define REG_FBDIV_LO_MASK GENMASK(7, 0) 66#define REG_FBDIV_LO(x) UPDATE(x, 7, 0) 67/* Analog Register Part: reg05 */ 68#define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4) 69#define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4) 70#define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0) 71#define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0) 72/* Analog Register Part: reg06 */ 73#define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4) 74#define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4) 75#define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0) 76#define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0) 77/* Analog Register Part: reg07 */ 78#define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4) 79#define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4) 80#define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0) 81#define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0) 82/* Analog Register Part: reg08 */ 83#define PLL_POST_DIV_ENABLE_MASK BIT(5) 84#define PLL_POST_DIV_ENABLE BIT(5) 85#define SAMPLE_CLOCK_DIRECTION_MASK BIT(4) 86#define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4) 87#define SAMPLE_CLOCK_DIRECTION_FORWARD 0 88#define LOWFRE_EN_MASK BIT(5) 89#define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0 90#define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1 91/* Analog Register Part: reg0b */ 92#define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0) 93#define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0) 94#define VOD_MIN_RANGE 0x1 95#define VOD_MID_RANGE 0x3 96#define VOD_BIG_RANGE 0x7 97#define VOD_MAX_RANGE 0xf 98/* Analog Register Part: reg1E */ 99#define PLL_MODE_SEL_MASK GENMASK(6, 5) 100#define PLL_MODE_SEL_LVDS_MODE 0 101#define PLL_MODE_SEL_MIPI_MODE BIT(5) 102/* Digital Register Part: reg00 */ 103#define REG_DIG_RSTN_MASK BIT(0) 104#define REG_DIG_RSTN_NORMAL BIT(0) 105#define REG_DIG_RSTN_RESET 0 106/* Digital Register Part: reg01 */ 107#define INVERT_TXCLKESC_MASK BIT(1) 108#define INVERT_TXCLKESC_ENABLE BIT(1) 109#define INVERT_TXCLKESC_DISABLE 0 110#define INVERT_TXBYTECLKHS_MASK BIT(0) 111#define INVERT_TXBYTECLKHS_ENABLE BIT(0) 112#define INVERT_TXBYTECLKHS_DISABLE 0 113/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */ 114#define T_LPX_CNT_MASK GENMASK(5, 0) 115#define T_LPX_CNT(x) UPDATE(x, 5, 0) 116/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */ 117#define T_HS_ZERO_CNT_HI_MASK BIT(7) 118#define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7) 119#define T_HS_PREPARE_CNT_MASK GENMASK(6, 0) 120#define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0) 121/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */ 122#define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0) 123#define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0) 124/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */ 125#define T_HS_TRAIL_CNT_MASK GENMASK(6, 0) 126#define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0) 127/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */ 128#define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0) 129#define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0) 130/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */ 131#define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0) 132#define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0) 133/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */ 134#define LPDT_TX_PPI_SYNC_MASK BIT(2) 135#define LPDT_TX_PPI_SYNC_ENABLE BIT(2) 136#define LPDT_TX_PPI_SYNC_DISABLE 0 137#define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0) 138#define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0) 139/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */ 140#define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0) 141#define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0) 142/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */ 143#define T_CLK_PRE_CNT_MASK GENMASK(3, 0) 144#define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0) 145/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */ 146#define T_CLK_POST_CNT_HI_MASK GENMASK(7, 6) 147#define T_CLK_POST_CNT_HI(x) UPDATE(x, 7, 6) 148#define T_TA_GO_CNT_MASK GENMASK(5, 0) 149#define T_TA_GO_CNT(x) UPDATE(x, 5, 0) 150/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */ 151#define T_HS_EXIT_CNT_HI_MASK BIT(6) 152#define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6) 153#define T_TA_SURE_CNT_MASK GENMASK(5, 0) 154#define T_TA_SURE_CNT(x) UPDATE(x, 5, 0) 155/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */ 156#define T_TA_WAIT_CNT_MASK GENMASK(5, 0) 157#define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0) 158/* LVDS Register Part: reg00 */ 159#define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2) 160#define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2) 161#define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0 162/* LVDS Register Part: reg01 */ 163#define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7) 164#define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7) 165#define LVDS_DIGITAL_INTERNAL_DISABLE 0 166/* LVDS Register Part: reg03 */ 167#define MODE_ENABLE_MASK GENMASK(2, 0) 168#define TTL_MODE_ENABLE BIT(2) 169#define LVDS_MODE_ENABLE BIT(1) 170#define MIPI_MODE_ENABLE BIT(0) 171/* LVDS Register Part: reg0b */ 172#define LVDS_LANE_EN_MASK GENMASK(7, 3) 173#define LVDS_DATA_LANE0_EN BIT(7) 174#define LVDS_DATA_LANE1_EN BIT(6) 175#define LVDS_DATA_LANE2_EN BIT(5) 176#define LVDS_DATA_LANE3_EN BIT(4) 177#define LVDS_CLK_LANE_EN BIT(3) 178#define LVDS_PLL_POWER_MASK BIT(2) 179#define LVDS_PLL_POWER_OFF BIT(2) 180#define LVDS_PLL_POWER_ON 0 181#define LVDS_BANDGAP_POWER_MASK BIT(0) 182#define LVDS_BANDGAP_POWER_DOWN BIT(0) 183#define LVDS_BANDGAP_POWER_ON 0 184 185#define DSI_PHY_RSTZ 0xa0 186#define PHY_ENABLECLK BIT(2) 187#define DSI_PHY_STATUS 0xb0 188#define PHY_LOCK BIT(0) 189 190#define msleep(a) udelay(a * 1000) 191 192enum phy_max_rate { 193 MAX_1GHZ, 194 MAX_2_5GHZ, 195}; 196 197struct clk_hw { 198 struct clk_core *core; 199 struct clk *clk; 200 const struct clk_init_data *init; 201}; 202 203struct inno_video_phy_plat_data { 204 const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table; 205 const unsigned int num_timings; 206 enum phy_max_rate max_rate; 207}; 208 209struct inno_dsidphy { 210 struct udevice *dev; 211 struct clk *ref_clk; 212 struct clk *pclk_phy; 213 struct clk *pclk_host; 214 const struct inno_video_phy_plat_data *pdata; 215 void __iomem *phy_base; 216 void __iomem *host_base; 217 struct reset_ctl *rst; 218 struct phy_configure_opts_mipi_dphy dphy_cfg; 219 220 struct clk *pll_clk; 221 struct { 222 struct clk_hw hw; 223 u8 prediv; 224 u16 fbdiv; 225 unsigned long rate; 226 } pll; 227}; 228 229enum { 230 REGISTER_PART_ANALOG, 231 REGISTER_PART_DIGITAL, 232 REGISTER_PART_CLOCK_LANE, 233 REGISTER_PART_DATA0_LANE, 234 REGISTER_PART_DATA1_LANE, 235 REGISTER_PART_DATA2_LANE, 236 REGISTER_PART_DATA3_LANE, 237 REGISTER_PART_LVDS, 238}; 239 240struct inno_mipi_dphy_timing { 241 unsigned long rate; 242 u8 lpx; 243 u8 hs_prepare; 244 u8 clk_lane_hs_zero; 245 u8 data_lane_hs_zero; 246 u8 hs_trail; 247}; 248 249static const 250struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = { 251 { 110000000, 0x0, 0x20, 0x16, 0x02, 0x22}, 252 { 150000000, 0x0, 0x06, 0x16, 0x03, 0x45}, 253 { 200000000, 0x0, 0x18, 0x17, 0x04, 0x0b}, 254 { 250000000, 0x0, 0x05, 0x17, 0x05, 0x16}, 255 { 300000000, 0x0, 0x51, 0x18, 0x06, 0x2c}, 256 { 400000000, 0x0, 0x64, 0x19, 0x07, 0x33}, 257 { 500000000, 0x0, 0x20, 0x1b, 0x07, 0x4e}, 258 { 600000000, 0x0, 0x6a, 0x1d, 0x08, 0x3a}, 259 { 700000000, 0x0, 0x3e, 0x1e, 0x08, 0x6a}, 260 { 800000000, 0x0, 0x21, 0x1f, 0x09, 0x29}, 261 {1000000000, 0x0, 0x09, 0x20, 0x09, 0x27}, 262}; 263 264static const 265struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = { 266 { 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02}, 267 { 150000000, 0x02, 0x7f, 0x16, 0x03, 0x02}, 268 { 200000000, 0x02, 0x7f, 0x17, 0x04, 0x02}, 269 { 250000000, 0x02, 0x7f, 0x17, 0x05, 0x04}, 270 { 300000000, 0x02, 0x7f, 0x18, 0x06, 0x04}, 271 { 400000000, 0x03, 0x7e, 0x19, 0x07, 0x04}, 272 { 500000000, 0x03, 0x7c, 0x1b, 0x07, 0x08}, 273 { 600000000, 0x03, 0x70, 0x1d, 0x08, 0x10}, 274 { 700000000, 0x05, 0x40, 0x1e, 0x08, 0x30}, 275 { 800000000, 0x05, 0x02, 0x1f, 0x09, 0x30}, 276 {1000000000, 0x05, 0x08, 0x20, 0x09, 0x30}, 277 {1200000000, 0x06, 0x03, 0x32, 0x14, 0x0f}, 278 {1400000000, 0x09, 0x03, 0x32, 0x14, 0x0f}, 279 {1600000000, 0x0d, 0x42, 0x36, 0x0e, 0x0f}, 280 {1800000000, 0x0e, 0x47, 0x7a, 0x0e, 0x0f}, 281 {2000000000, 0x11, 0x64, 0x7a, 0x0e, 0x0b}, 282 {2200000000, 0x13, 0x64, 0x7e, 0x15, 0x0b}, 283 {2400000000, 0x13, 0x33, 0x7f, 0x15, 0x6a}, 284 {2500000000, 0x15, 0x54, 0x7f, 0x15, 0x6a}, 285}; 286 287static void phy_update_bits(struct inno_dsidphy *inno, 288 u8 first, u8 second, u8 mask, u8 val) 289{ 290 u32 reg = PHY_REG(first, second) << 2; 291 unsigned int tmp, orig; 292 293 orig = readl(inno->phy_base + reg); 294 tmp = orig & ~mask; 295 tmp |= val & mask; 296 writel(tmp, inno->phy_base + reg); 297} 298 299static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno, 300 unsigned long rate) 301{ 302 unsigned long prate; 303 unsigned long best_freq = 0; 304 unsigned long fref, fout; 305 u8 min_prediv, max_prediv; 306 u8 _prediv, best_prediv = 1; 307 u16 _fbdiv, best_fbdiv = 1; 308 u32 min_delta = UINT_MAX; 309 310 /* 311 * Upstream Linux tries to read the ref_clk, while the BSP 312 * U-Boot hard-codes this as 24MHz. Try the first, and if that 313 * fails do the second. 314 */ 315 prate = clk_get_rate(inno->ref_clk); 316 if (IS_ERR_VALUE(prate)) 317 prate = 24000000; 318 319 /* 320 * The PLL output frequency can be calculated using a simple formula: 321 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2 322 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 323 */ 324 fref = prate / 2; 325 if (rate > 1000000000UL) 326 fout = 1000000000UL; 327 else 328 fout = rate; 329 330 /* 5Mhz < Fref / prediv < 40MHz */ 331 min_prediv = DIV_ROUND_UP(fref, 40000000); 332 max_prediv = fref / 5000000; 333 334 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 335 u64 tmp; 336 u32 delta; 337 338 tmp = (u64)fout * _prediv; 339 do_div(tmp, fref); 340 _fbdiv = tmp; 341 342 /* 343 * The possible settings of feedback divider are 344 * 12, 13, 14, 16, ~ 511 345 */ 346 if (_fbdiv == 15) 347 continue; 348 349 if (_fbdiv < 12 || _fbdiv > 511) 350 continue; 351 352 tmp = (u64)_fbdiv * fref; 353 do_div(tmp, _prediv); 354 355 delta = abs(fout - tmp); 356 if (!delta) { 357 best_prediv = _prediv; 358 best_fbdiv = _fbdiv; 359 best_freq = tmp; 360 break; 361 } else if (delta < min_delta) { 362 best_prediv = _prediv; 363 best_fbdiv = _fbdiv; 364 best_freq = tmp; 365 min_delta = delta; 366 } 367 } 368 369 if (best_freq) { 370 inno->pll.prediv = best_prediv; 371 inno->pll.fbdiv = best_fbdiv; 372 inno->pll.rate = best_freq; 373 } 374 375 return best_freq; 376} 377 378static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) 379{ 380 struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg; 381 const struct inno_mipi_dphy_timing *timings; 382 u32 t_txbyteclkhs, t_txclkesc; 383 u32 txbyteclkhs, txclkesc, esc_clk_div; 384 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; 385 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; 386 unsigned int i; 387 388 timings = inno->pdata->inno_mipi_dphy_timing_table; 389 390 inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate); 391 392 /* Select MIPI mode */ 393 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 394 MODE_ENABLE_MASK, MIPI_MODE_ENABLE); 395 /* Configure PLL */ 396 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 397 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); 398 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 399 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); 400 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 401 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); 402 if (inno->pdata->max_rate == MAX_2_5GHZ) { 403 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, 404 PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE); 405 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, 406 CLOCK_LANE_VOD_RANGE_SET_MASK, 407 CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); 408 } 409 /* Enable PLL and LDO */ 410 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 411 REG_LDOPD_MASK | REG_PLLPD_MASK, 412 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON); 413 /* Reset analog */ 414 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 415 REG_SYNCRST_MASK, REG_SYNCRST_RESET); 416 udelay(1); 417 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 418 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL); 419 /* Reset digital */ 420 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 421 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET); 422 udelay(1); 423 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 424 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL); 425 426 txbyteclkhs = inno->pll.rate / 8; 427 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs); 428 429 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000); 430 txclkesc = txbyteclkhs / esc_clk_div; 431 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc); 432 433 /* 434 * The value of counter for HS Ths-exit 435 * Ths-exit = Tpin_txbyteclkhs * value 436 */ 437 hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs); 438 /* 439 * The value of counter for HS Tclk-post 440 * Tclk-post = Tpin_txbyteclkhs * value 441 */ 442 clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs); 443 /* 444 * The value of counter for HS Tclk-pre 445 * Tclk-pre = Tpin_txbyteclkhs * value 446 */ 447 clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE); 448 449 /* 450 * The value of counter for HS Tta-go 451 * Tta-go for turnaround 452 * Tta-go = Ttxclkesc * value 453 */ 454 ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc); 455 /* 456 * The value of counter for HS Tta-sure 457 * Tta-sure for turnaround 458 * Tta-sure = Ttxclkesc * value 459 */ 460 ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc); 461 /* 462 * The value of counter for HS Tta-wait 463 * Tta-wait for turnaround 464 * Tta-wait = Ttxclkesc * value 465 */ 466 ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc); 467 468 for (i = 0; i < inno->pdata->num_timings; i++) 469 if (inno->pll.rate <= timings[i].rate) 470 break; 471 472 if (i == inno->pdata->num_timings) 473 --i; 474 475 /* 476 * The value of counter for HS Tlpx Time 477 * Tlpx = Tpin_txbyteclkhs * (2 + value) 478 */ 479 if (inno->pdata->max_rate == MAX_1GHZ) { 480 lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs); 481 if (lpx >= 2) 482 lpx -= 2; 483 } else { 484 lpx = timings[i].lpx; 485 } 486 487 hs_prepare = timings[i].hs_prepare; 488 hs_trail = timings[i].hs_trail; 489 clk_lane_hs_zero = timings[i].clk_lane_hs_zero; 490 data_lane_hs_zero = timings[i].data_lane_hs_zero; 491 wakeup = 0x3ff; 492 493 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) { 494 if (i == REGISTER_PART_CLOCK_LANE) 495 hs_zero = clk_lane_hs_zero; 496 else 497 hs_zero = data_lane_hs_zero; 498 499 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK, 500 T_LPX_CNT(lpx)); 501 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK, 502 T_HS_PREPARE_CNT(hs_prepare)); 503 if (inno->pdata->max_rate == MAX_2_5GHZ) 504 phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK, 505 T_HS_ZERO_CNT_HI(hs_zero >> 6)); 506 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK, 507 T_HS_ZERO_CNT_LO(hs_zero)); 508 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK, 509 T_HS_TRAIL_CNT(hs_trail)); 510 if (inno->pdata->max_rate == MAX_2_5GHZ) 511 phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK, 512 T_HS_EXIT_CNT_HI(hs_exit >> 5)); 513 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK, 514 T_HS_EXIT_CNT_LO(hs_exit)); 515 if (inno->pdata->max_rate == MAX_2_5GHZ) 516 phy_update_bits(inno, i, 0x10, T_CLK_POST_CNT_HI_MASK, 517 T_CLK_POST_CNT_HI(clk_post >> 4)); 518 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK, 519 T_CLK_POST_CNT_LO(clk_post)); 520 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK, 521 T_CLK_PRE_CNT(clk_pre)); 522 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK, 523 T_WAKEUP_CNT_HI(wakeup >> 8)); 524 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK, 525 T_WAKEUP_CNT_LO(wakeup)); 526 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK, 527 T_TA_GO_CNT(ta_go)); 528 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK, 529 T_TA_SURE_CNT(ta_sure)); 530 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK, 531 T_TA_WAIT_CNT(ta_wait)); 532 } 533 534 /* Enable all lanes on analog part */ 535 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 536 LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | 537 LANE_EN_1 | LANE_EN_0); 538} 539 540static int inno_dsidphy_power_on(struct phy *phy) 541{ 542 struct inno_dsidphy *inno = dev_get_priv(phy->dev); 543 544 clk_prepare_enable(inno->pclk_phy); 545 clk_prepare_enable(inno->ref_clk); 546 547 /* Bandgap power on */ 548 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 549 BANDGAP_POWER_MASK, BANDGAP_POWER_ON); 550 /* Enable power work */ 551 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 552 POWER_WORK_MASK, POWER_WORK_ENABLE); 553 554 inno_dsidphy_mipi_mode_enable(inno); 555 556 return 0; 557} 558 559static int inno_dsidphy_power_off(struct phy *phy) 560{ 561 struct inno_dsidphy *inno = dev_get_priv(phy->dev); 562 563 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0); 564 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 565 REG_LDOPD_MASK | REG_PLLPD_MASK, 566 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN); 567 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 568 POWER_WORK_MASK, POWER_WORK_DISABLE); 569 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 570 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN); 571 572 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0); 573 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 574 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 575 LVDS_DIGITAL_INTERNAL_DISABLE); 576 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 577 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 578 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN); 579 580 clk_disable_unprepare(inno->ref_clk); 581 clk_disable_unprepare(inno->pclk_phy); 582 583 return 0; 584} 585 586static int inno_dsidphy_configure(struct phy *phy, void *params) 587{ 588 struct inno_dsidphy *inno = dev_get_priv(phy->dev); 589 struct phy_configure_opts_mipi_dphy *config = params; 590 int ret; 591 592 ret = phy_mipi_dphy_config_validate(config); 593 if (ret) 594 return ret; 595 596 memcpy(&inno->dphy_cfg, config, sizeof(inno->dphy_cfg)); 597 598 return 0; 599} 600 601static const struct phy_ops inno_dsidphy_ops = { 602 .configure = inno_dsidphy_configure, 603 .power_on = inno_dsidphy_power_on, 604 .power_off = inno_dsidphy_power_off, 605}; 606 607static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = { 608 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, 609 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), 610 .max_rate = MAX_1GHZ, 611}; 612 613static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = { 614 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, 615 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), 616 .max_rate = MAX_2_5GHZ, 617}; 618 619static int inno_dsidphy_probe(struct udevice *dev) 620{ 621 struct inno_dsidphy *inno = dev_get_priv(dev); 622 int ret; 623 624 inno->dev = dev; 625 inno->pdata = (const struct inno_video_phy_plat_data *)dev_get_driver_data(dev); 626 627 inno->phy_base = dev_read_addr_ptr(dev); 628 if (IS_ERR(inno->phy_base)) 629 return PTR_ERR(inno->phy_base); 630 631 inno->ref_clk = devm_clk_get(dev, "ref"); 632 if (IS_ERR(inno->ref_clk)) { 633 ret = PTR_ERR(inno->ref_clk); 634 dev_err(dev, "failed to get ref clock: %d\n", ret); 635 return ret; 636 } 637 638 inno->pclk_phy = devm_clk_get(dev, "pclk"); 639 if (IS_ERR(inno->pclk_phy)) { 640 ret = PTR_ERR(inno->pclk_phy); 641 dev_err(dev, "failed to get phy pclk: %d\n", ret); 642 return ret; 643 } 644 645 inno->rst = devm_reset_control_get(dev, "apb"); 646 if (IS_ERR(inno->rst)) { 647 ret = PTR_ERR(inno->rst); 648 dev_err(dev, "failed to get system reset control: %d\n", ret); 649 return ret; 650 } 651 652 return 0; 653} 654 655static const struct udevice_id inno_dsidphy_of_match[] = { 656 { 657 .compatible = "rockchip,px30-dsi-dphy", 658 .data = (long)&max_1ghz_video_phy_plat_data, 659 }, { 660 .compatible = "rockchip,rk3128-dsi-dphy", 661 .data = (long)&max_1ghz_video_phy_plat_data, 662 }, { 663 .compatible = "rockchip,rk3368-dsi-dphy", 664 .data = (long)&max_1ghz_video_phy_plat_data, 665 }, { 666 .compatible = "rockchip,rk3568-dsi-dphy", 667 .data = (long)&max_2_5ghz_video_phy_plat_data, 668 }, 669 {} 670}; 671 672U_BOOT_DRIVER(rockchip_inno_dsidphy) = { 673 .name = "rockchip-inno-dsidphy", 674 .id = UCLASS_PHY, 675 .of_match = inno_dsidphy_of_match, 676 .probe = inno_dsidphy_probe, 677 .ops = &inno_dsidphy_ops, 678 .priv_auto = sizeof(struct inno_dsidphy), 679}; 680