1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2007 4 * Sascha Hauer, Pengutronix 5 * 6 * (C) Copyright 2009 Freescale Semiconductor, Inc. 7 */ 8 9#include <common.h> 10#include <command.h> 11#include <log.h> 12#include <asm/io.h> 13#include <linux/errno.h> 14#include <asm/arch/imx-regs.h> 15#include <asm/arch/crm_regs.h> 16#include <asm/arch/clock.h> 17#include <div64.h> 18#include <asm/arch/sys_proto.h> 19 20enum pll_clocks { 21 PLL1_CLOCK = 0, 22 PLL2_CLOCK, 23 PLL3_CLOCK, 24#ifdef CONFIG_MX53 25 PLL4_CLOCK, 26#endif 27 PLL_CLOCKS, 28}; 29 30struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { 31 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR, 32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR, 33 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, 34#ifdef CONFIG_MX53 35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR, 36#endif 37}; 38 39#define AHB_CLK_ROOT 133333333 40#define SZ_DEC_1M 1000000 41#define PLL_PD_MAX 16 /* Actual pd+1 */ 42#define PLL_MFI_MAX 15 43#define PLL_MFI_MIN 5 44#define ARM_DIV_MAX 8 45#define IPG_DIV_MAX 4 46#define AHB_DIV_MAX 8 47#define EMI_DIV_MAX 8 48#define NFC_DIV_MAX 8 49 50#define MX5_CBCMR 0x00015154 51#define MX5_CBCDR 0x02888945 52 53struct fixed_pll_mfd { 54 u32 ref_clk_hz; 55 u32 mfd; 56}; 57 58const struct fixed_pll_mfd fixed_mfd[] = { 59 {MXC_HCLK, 24 * 16}, 60}; 61 62struct pll_param { 63 u32 pd; 64 u32 mfi; 65 u32 mfn; 66 u32 mfd; 67}; 68 69#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) 70#define PLL_FREQ_MIN(ref_clk) \ 71 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) 72#define MAX_DDR_CLK 420000000 73#define NFC_CLK_MAX 34000000 74 75struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; 76 77void set_usboh3_clk(void) 78{ 79 clrsetbits_le32(&mxc_ccm->cscmr1, 80 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK, 81 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1)); 82 clrsetbits_le32(&mxc_ccm->cscdr1, 83 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK | 84 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK, 85 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) | 86 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1)); 87} 88 89void enable_usboh3_clk(bool enable) 90{ 91 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; 92 93 clrsetbits_le32(&mxc_ccm->CCGR2, 94 MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK), 95 MXC_CCM_CCGR2_USBOH3_60M(cg)); 96} 97 98#ifdef CONFIG_SYS_I2C_MXC 99/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */ 100int enable_i2c_clk(unsigned char enable, unsigned i2c_num) 101{ 102 u32 mask; 103 104#if defined(CONFIG_MX51) 105 if (i2c_num > 1) 106#elif defined(CONFIG_MX53) 107 if (i2c_num > 2) 108#endif 109 return -EINVAL; 110 mask = MXC_CCM_CCGR_CG_MASK << 111 (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1)); 112 if (enable) 113 setbits_le32(&mxc_ccm->CCGR1, mask); 114 else 115 clrbits_le32(&mxc_ccm->CCGR1, mask); 116 return 0; 117} 118#endif 119 120void set_usb_phy_clk(void) 121{ 122 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); 123} 124 125#if defined(CONFIG_MX51) 126void enable_usb_phy1_clk(bool enable) 127{ 128 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; 129 130 clrsetbits_le32(&mxc_ccm->CCGR2, 131 MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK), 132 MXC_CCM_CCGR2_USB_PHY(cg)); 133} 134 135void enable_usb_phy2_clk(bool enable) 136{ 137 /* i.MX51 has a single USB PHY clock, so do nothing here. */ 138} 139#elif defined(CONFIG_MX53) 140void enable_usb_phy1_clk(bool enable) 141{ 142 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; 143 144 clrsetbits_le32(&mxc_ccm->CCGR4, 145 MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK), 146 MXC_CCM_CCGR4_USB_PHY1(cg)); 147} 148 149void enable_usb_phy2_clk(bool enable) 150{ 151 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; 152 153 clrsetbits_le32(&mxc_ccm->CCGR4, 154 MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK), 155 MXC_CCM_CCGR4_USB_PHY2(cg)); 156} 157#endif 158 159/* 160 * Calculate the frequency of PLLn. 161 */ 162static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) 163{ 164 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret; 165 uint64_t refclk, temp; 166 int32_t mfn_abs; 167 168 ctrl = readl(&pll->ctrl); 169 170 if (ctrl & MXC_DPLLC_CTL_HFSM) { 171 mfn = readl(&pll->hfs_mfn); 172 mfd = readl(&pll->hfs_mfd); 173 op = readl(&pll->hfs_op); 174 } else { 175 mfn = readl(&pll->mfn); 176 mfd = readl(&pll->mfd); 177 op = readl(&pll->op); 178 } 179 180 mfd &= MXC_DPLLC_MFD_MFD_MASK; 181 mfn &= MXC_DPLLC_MFN_MFN_MASK; 182 pdf = op & MXC_DPLLC_OP_PDF_MASK; 183 mfi = MXC_DPLLC_OP_MFI_RD(op); 184 185 /* 21.2.3 */ 186 if (mfi < 5) 187 mfi = 5; 188 189 /* Sign extend */ 190 if (mfn >= 0x04000000) { 191 mfn |= 0xfc000000; 192 mfn_abs = -mfn; 193 } else 194 mfn_abs = mfn; 195 196 refclk = infreq * 2; 197 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN) 198 refclk *= 2; 199 200 do_div(refclk, pdf + 1); 201 temp = refclk * mfn_abs; 202 do_div(temp, mfd + 1); 203 ret = refclk * mfi; 204 205 if ((int)mfn < 0) 206 ret -= temp; 207 else 208 ret += temp; 209 210 return ret; 211} 212 213#ifdef CONFIG_MX51 214/* 215 * This function returns the Frequency Pre-Multiplier clock. 216 */ 217static u32 get_fpm(void) 218{ 219 u32 mult; 220 u32 ccr = readl(&mxc_ccm->ccr); 221 222 if (ccr & MXC_CCM_CCR_FPM_MULT) 223 mult = 1024; 224 else 225 mult = 512; 226 227 return MXC_CLK32 * mult; 228} 229#endif 230 231/* 232 * This function returns the low power audio clock. 233 */ 234static u32 get_lp_apm(void) 235{ 236 u32 ret_val = 0; 237 u32 ccsr = readl(&mxc_ccm->ccsr); 238 239 if (ccsr & MXC_CCM_CCSR_LP_APM) 240#if defined(CONFIG_MX51) 241 ret_val = get_fpm(); 242#elif defined(CONFIG_MX53) 243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); 244#endif 245 else 246 ret_val = MXC_HCLK; 247 248 return ret_val; 249} 250 251/* 252 * Get mcu main rate 253 */ 254u32 get_mcu_main_clk(void) 255{ 256 u32 reg, freq; 257 258 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr)); 259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); 260 return freq / (reg + 1); 261} 262 263/* 264 * Get the rate of peripheral's root clock. 265 */ 266u32 get_periph_clk(void) 267{ 268 u32 reg; 269 270 reg = readl(&mxc_ccm->cbcdr); 271 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL)) 272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); 273 reg = readl(&mxc_ccm->cbcmr); 274 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) { 275 case 0: 276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); 277 case 1: 278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); 279 case 2: 280 return get_lp_apm(); 281 default: 282 return 0; 283 } 284 /* NOTREACHED */ 285} 286 287/* 288 * Get the rate of ipg clock. 289 */ 290static u32 get_ipg_clk(void) 291{ 292 uint32_t freq, reg, div; 293 294 freq = get_ahb_clk(); 295 296 reg = readl(&mxc_ccm->cbcdr); 297 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1; 298 299 return freq / div; 300} 301 302/* 303 * Get the rate of ipg_per clock. 304 */ 305static u32 get_ipg_per_clk(void) 306{ 307 u32 freq, pred1, pred2, podf; 308 309 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) 310 return get_ipg_clk(); 311 312 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) 313 freq = get_lp_apm(); 314 else 315 freq = get_periph_clk(); 316 podf = readl(&mxc_ccm->cbcdr); 317 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf); 318 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf); 319 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf); 320 return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); 321} 322 323/* Get the output clock rate of a standard PLL MUX for peripherals. */ 324static u32 get_standard_pll_sel_clk(u32 clk_sel) 325{ 326 u32 freq = 0; 327 328 switch (clk_sel & 0x3) { 329 case 0: 330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); 331 break; 332 case 1: 333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); 334 break; 335 case 2: 336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); 337 break; 338 case 3: 339 freq = get_lp_apm(); 340 break; 341 } 342 343 return freq; 344} 345 346/* 347 * Get the rate of uart clk. 348 */ 349static u32 get_uart_clk(void) 350{ 351 unsigned int clk_sel, freq, reg, pred, podf; 352 353 reg = readl(&mxc_ccm->cscmr1); 354 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg); 355 freq = get_standard_pll_sel_clk(clk_sel); 356 357 reg = readl(&mxc_ccm->cscdr1); 358 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg); 359 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg); 360 freq /= (pred + 1) * (podf + 1); 361 362 return freq; 363} 364 365/* 366 * get cspi clock rate. 367 */ 368static u32 imx_get_cspiclk(void) 369{ 370 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq; 371 u32 cscmr1 = readl(&mxc_ccm->cscmr1); 372 u32 cscdr2 = readl(&mxc_ccm->cscdr2); 373 374 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2); 375 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2); 376 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1); 377 freq = get_standard_pll_sel_clk(clk_sel); 378 ret_val = freq / ((pre_pdf + 1) * (pdf + 1)); 379 return ret_val; 380} 381 382/* 383 * get esdhc clock rate. 384 */ 385static u32 get_esdhc_clk(u32 port) 386{ 387 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0; 388 u32 cscmr1 = readl(&mxc_ccm->cscmr1); 389 u32 cscdr1 = readl(&mxc_ccm->cscdr1); 390 391 switch (port) { 392 case 0: 393 clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1); 394 pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1); 395 podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1); 396 break; 397 case 1: 398 clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1); 399 pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1); 400 podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1); 401 break; 402 case 2: 403 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL) 404 return get_esdhc_clk(1); 405 else 406 return get_esdhc_clk(0); 407 case 3: 408 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL) 409 return get_esdhc_clk(1); 410 else 411 return get_esdhc_clk(0); 412 default: 413 break; 414 } 415 416 freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1)); 417 return freq; 418} 419 420static u32 get_axi_a_clk(void) 421{ 422 u32 cbcdr = readl(&mxc_ccm->cbcdr); 423 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr); 424 425 return get_periph_clk() / (pdf + 1); 426} 427 428static u32 get_axi_b_clk(void) 429{ 430 u32 cbcdr = readl(&mxc_ccm->cbcdr); 431 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr); 432 433 return get_periph_clk() / (pdf + 1); 434} 435 436static u32 get_emi_slow_clk(void) 437{ 438 u32 cbcdr = readl(&mxc_ccm->cbcdr); 439 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; 440 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr); 441 442 if (emi_clk_sel) 443 return get_ahb_clk() / (pdf + 1); 444 445 return get_periph_clk() / (pdf + 1); 446} 447 448static u32 get_ddr_clk(void) 449{ 450 u32 ret_val = 0; 451 u32 cbcmr = readl(&mxc_ccm->cbcmr); 452 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); 453#ifdef CONFIG_MX51 454 u32 cbcdr = readl(&mxc_ccm->cbcdr); 455 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) { 456 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr); 457 458 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); 459 ret_val /= ddr_clk_podf + 1; 460 461 return ret_val; 462 } 463#endif 464 switch (ddr_clk_sel) { 465 case 0: 466 ret_val = get_axi_a_clk(); 467 break; 468 case 1: 469 ret_val = get_axi_b_clk(); 470 break; 471 case 2: 472 ret_val = get_emi_slow_clk(); 473 break; 474 case 3: 475 ret_val = get_ahb_clk(); 476 break; 477 default: 478 break; 479 } 480 481 return ret_val; 482} 483 484/* 485 * The API of get mxc clocks. 486 */ 487unsigned int mxc_get_clock(enum mxc_clock clk) 488{ 489 switch (clk) { 490 case MXC_ARM_CLK: 491 return get_mcu_main_clk(); 492 case MXC_AHB_CLK: 493 return get_ahb_clk(); 494 case MXC_IPG_CLK: 495 return get_ipg_clk(); 496 case MXC_IPG_PERCLK: 497 case MXC_I2C_CLK: 498 return get_ipg_per_clk(); 499 case MXC_UART_CLK: 500 return get_uart_clk(); 501 case MXC_CSPI_CLK: 502 return imx_get_cspiclk(); 503 case MXC_ESDHC_CLK: 504 return get_esdhc_clk(0); 505 case MXC_ESDHC2_CLK: 506 return get_esdhc_clk(1); 507 case MXC_ESDHC3_CLK: 508 return get_esdhc_clk(2); 509 case MXC_ESDHC4_CLK: 510 return get_esdhc_clk(3); 511 case MXC_FEC_CLK: 512 return get_ipg_clk(); 513 case MXC_SATA_CLK: 514 return get_ahb_clk(); 515 case MXC_DDR_CLK: 516 return get_ddr_clk(); 517 default: 518 break; 519 } 520 return -EINVAL; 521} 522 523u32 imx_get_uartclk(void) 524{ 525 return get_uart_clk(); 526} 527 528u32 imx_get_fecclk(void) 529{ 530 return get_ipg_clk(); 531} 532 533static int gcd(int m, int n) 534{ 535 int t; 536 while (m > 0) { 537 if (n > m) { 538 t = m; 539 m = n; 540 n = t; 541 } /* swap */ 542 m -= n; 543 } 544 return n; 545} 546 547/* 548 * This is to calculate various parameters based on reference clock and 549 * targeted clock based on the equation: 550 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1) 551 * This calculation is based on a fixed MFD value for simplicity. 552 */ 553static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) 554{ 555 u64 pd, mfi = 1, mfn, mfd, t1; 556 u32 n_target = target; 557 u32 n_ref = ref, i; 558 559 /* 560 * Make sure targeted freq is in the valid range. 561 * Otherwise the following calculation might be wrong!!! 562 */ 563 if (n_target < PLL_FREQ_MIN(ref) || 564 n_target > PLL_FREQ_MAX(ref)) { 565 printf("Targeted peripheral clock should be" 566 "within [%d - %d]\n", 567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, 568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); 569 return -EINVAL; 570 } 571 572 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) { 573 if (fixed_mfd[i].ref_clk_hz == ref) { 574 mfd = fixed_mfd[i].mfd; 575 break; 576 } 577 } 578 579 if (i == ARRAY_SIZE(fixed_mfd)) 580 return -EINVAL; 581 582 /* Use n_target and n_ref to avoid overflow */ 583 for (pd = 1; pd <= PLL_PD_MAX; pd++) { 584 t1 = n_target * pd; 585 do_div(t1, (4 * n_ref)); 586 mfi = t1; 587 if (mfi > PLL_MFI_MAX) 588 return -EINVAL; 589 else if (mfi < 5) 590 continue; 591 break; 592 } 593 /* 594 * Now got pd and mfi already 595 * 596 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; 597 */ 598 t1 = n_target * pd; 599 do_div(t1, 4); 600 t1 -= n_ref * mfi; 601 t1 *= mfd; 602 do_div(t1, n_ref); 603 mfn = t1; 604 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n", 605 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd); 606 i = 1; 607 if (mfn != 0) 608 i = gcd(mfd, mfn); 609 pll->pd = (u32)pd; 610 pll->mfi = (u32)mfi; 611 do_div(mfn, i); 612 pll->mfn = (u32)mfn; 613 do_div(mfd, i); 614 pll->mfd = (u32)mfd; 615 616 return 0; 617} 618 619#define calc_div(tgt_clk, src_clk, limit) ({ \ 620 u32 v = 0; \ 621 if (((src_clk) % (tgt_clk)) <= 100) \ 622 v = (src_clk) / (tgt_clk); \ 623 else \ 624 v = ((src_clk) / (tgt_clk)) + 1;\ 625 if (v > limit) \ 626 v = limit; \ 627 (v - 1); \ 628 }) 629 630#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \ 631 { \ 632 writel(0x1232, &pll->ctrl); \ 633 writel(0x2, &pll->config); \ 634 writel((((pd) - 1) << 0) | ((fi) << 4), \ 635 &pll->op); \ 636 writel(fn, &(pll->mfn)); \ 637 writel((fd) - 1, &pll->mfd); \ 638 writel((((pd) - 1) << 0) | ((fi) << 4), \ 639 &pll->hfs_op); \ 640 writel(fn, &pll->hfs_mfn); \ 641 writel((fd) - 1, &pll->hfs_mfd); \ 642 writel(0x1232, &pll->ctrl); \ 643 while (!readl(&pll->ctrl) & 0x1) \ 644 ;\ 645 } 646 647static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) 648{ 649 u32 ccsr = readl(&mxc_ccm->ccsr); 650 struct mxc_pll_reg *pll = mxc_plls[index]; 651 652 switch (index) { 653 case PLL1_CLOCK: 654 /* Switch ARM to PLL2 clock */ 655 writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL, 656 &mxc_ccm->ccsr); 657 CHANGE_PLL_SETTINGS(pll, pll_param->pd, 658 pll_param->mfi, pll_param->mfn, 659 pll_param->mfd); 660 /* Switch back */ 661 writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL, 662 &mxc_ccm->ccsr); 663 break; 664 case PLL2_CLOCK: 665 /* Switch to pll2 bypass clock */ 666 writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL, 667 &mxc_ccm->ccsr); 668 CHANGE_PLL_SETTINGS(pll, pll_param->pd, 669 pll_param->mfi, pll_param->mfn, 670 pll_param->mfd); 671 /* Switch back */ 672 writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL, 673 &mxc_ccm->ccsr); 674 break; 675 case PLL3_CLOCK: 676 /* Switch to pll3 bypass clock */ 677 writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL, 678 &mxc_ccm->ccsr); 679 CHANGE_PLL_SETTINGS(pll, pll_param->pd, 680 pll_param->mfi, pll_param->mfn, 681 pll_param->mfd); 682 /* Switch back */ 683 writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL, 684 &mxc_ccm->ccsr); 685 break; 686#ifdef CONFIG_MX53 687 case PLL4_CLOCK: 688 /* Switch to pll4 bypass clock */ 689 writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL, 690 &mxc_ccm->ccsr); 691 CHANGE_PLL_SETTINGS(pll, pll_param->pd, 692 pll_param->mfi, pll_param->mfn, 693 pll_param->mfd); 694 /* Switch back */ 695 writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL, 696 &mxc_ccm->ccsr); 697 break; 698#endif 699 default: 700 return -EINVAL; 701 } 702 703 return 0; 704} 705 706/* Config CPU clock */ 707static int config_core_clk(u32 ref, u32 freq) 708{ 709 int ret = 0; 710 struct pll_param pll_param; 711 712 memset(&pll_param, 0, sizeof(struct pll_param)); 713 714 /* The case that periph uses PLL1 is not considered here */ 715 ret = calc_pll_params(ref, freq, &pll_param); 716 if (ret != 0) { 717 printf("Error:Can't find pll parameters: %d\n", ret); 718 return ret; 719 } 720 721 return config_pll_clk(PLL1_CLOCK, &pll_param); 722} 723 724static int config_nfc_clk(u32 nfc_clk) 725{ 726 u32 parent_rate = get_emi_slow_clk(); 727 u32 div; 728 729 if (nfc_clk == 0) 730 return -EINVAL; 731 div = parent_rate / nfc_clk; 732 if (div == 0) 733 div++; 734 if (parent_rate / div > NFC_CLK_MAX) 735 div++; 736 clrsetbits_le32(&mxc_ccm->cbcdr, 737 MXC_CCM_CBCDR_NFC_PODF_MASK, 738 MXC_CCM_CBCDR_NFC_PODF(div - 1)); 739 while (readl(&mxc_ccm->cdhipr) != 0) 740 ; 741 return 0; 742} 743 744void enable_nfc_clk(unsigned char enable) 745{ 746 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; 747 748 clrsetbits_le32(&mxc_ccm->CCGR5, 749 MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK), 750 MXC_CCM_CCGR5_EMI_ENFC(cg)); 751} 752 753#ifdef CONFIG_FSL_IIM 754void enable_efuse_prog_supply(bool enable) 755{ 756 if (enable) 757 setbits_le32(&mxc_ccm->cgpr, 758 MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE); 759 else 760 clrbits_le32(&mxc_ccm->cgpr, 761 MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE); 762} 763#endif 764 765/* Config main_bus_clock for periphs */ 766static int config_periph_clk(u32 ref, u32 freq) 767{ 768 int ret = 0; 769 struct pll_param pll_param; 770 771 memset(&pll_param, 0, sizeof(struct pll_param)); 772 773 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { 774 ret = calc_pll_params(ref, freq, &pll_param); 775 if (ret != 0) { 776 printf("Error:Can't find pll parameters: %d\n", 777 ret); 778 return ret; 779 } 780 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD( 781 readl(&mxc_ccm->cbcmr))) { 782 case 0: 783 return config_pll_clk(PLL1_CLOCK, &pll_param); 784 break; 785 case 1: 786 return config_pll_clk(PLL3_CLOCK, &pll_param); 787 break; 788 default: 789 return -EINVAL; 790 } 791 } 792 793 return 0; 794} 795 796static int config_ddr_clk(u32 emi_clk) 797{ 798 u32 clk_src; 799 s32 shift = 0, clk_sel, div = 1; 800 u32 cbcmr = readl(&mxc_ccm->cbcmr); 801 802 if (emi_clk > MAX_DDR_CLK) { 803 printf("Warning:DDR clock should not exceed %d MHz\n", 804 MAX_DDR_CLK / SZ_DEC_1M); 805 emi_clk = MAX_DDR_CLK; 806 } 807 808 clk_src = get_periph_clk(); 809 /* Find DDR clock input */ 810 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); 811 switch (clk_sel) { 812 case 0: 813 shift = 16; 814 break; 815 case 1: 816 shift = 19; 817 break; 818 case 2: 819 shift = 22; 820 break; 821 case 3: 822 shift = 10; 823 break; 824 default: 825 return -EINVAL; 826 } 827 828 if ((clk_src % emi_clk) < 10000000) 829 div = clk_src / emi_clk; 830 else 831 div = (clk_src / emi_clk) + 1; 832 if (div > 8) 833 div = 8; 834 835 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift); 836 while (readl(&mxc_ccm->cdhipr) != 0) 837 ; 838 writel(0x0, &mxc_ccm->ccdr); 839 840 return 0; 841} 842 843#ifdef CONFIG_MX53 844static int config_ldb_clk(u32 ref, u32 freq) 845{ 846 int ret = 0; 847 struct pll_param pll_param; 848 849 memset(&pll_param, 0, sizeof(struct pll_param)); 850 851 ret = calc_pll_params(ref, freq, &pll_param); 852 if (ret != 0) { 853 printf("Error:Can't find pll parameters: %d\n", 854 ret); 855 return ret; 856 } 857 858 return config_pll_clk(PLL4_CLOCK, &pll_param); 859} 860#else 861static int config_ldb_clk(u32 ref, u32 freq) 862{ 863 /* Platform not supported */ 864 return -EINVAL; 865} 866#endif 867 868/* 869 * This function assumes the expected core clock has to be changed by 870 * modifying the PLL. This is NOT true always but for most of the times, 871 * it is. So it assumes the PLL output freq is the same as the expected 872 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. 873 * In the latter case, it will try to increase the presc value until 874 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to 875 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based 876 * on the targeted PLL and reference input clock to the PLL. Lastly, 877 * it sets the register based on these values along with the dividers. 878 * Note 1) There is no value checking for the passed-in divider values 879 * so the caller has to make sure those values are sensible. 880 * 2) Also adjust the NFC divider such that the NFC clock doesn't 881 * exceed NFC_CLK_MAX. 882 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to 883 * 177MHz for higher voltage, this function fixes the max to 133MHz. 884 * 4) This function should not have allowed diag_printf() calls since 885 * the serial driver has been stoped. But leave then here to allow 886 * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). 887 */ 888int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) 889{ 890 freq *= SZ_DEC_1M; 891 892 switch (clk) { 893 case MXC_ARM_CLK: 894 if (config_core_clk(ref, freq)) 895 return -EINVAL; 896 break; 897 case MXC_PERIPH_CLK: 898 if (config_periph_clk(ref, freq)) 899 return -EINVAL; 900 break; 901 case MXC_DDR_CLK: 902 if (config_ddr_clk(freq)) 903 return -EINVAL; 904 break; 905 case MXC_NFC_CLK: 906 if (config_nfc_clk(freq)) 907 return -EINVAL; 908 break; 909 case MXC_LDB_CLK: 910 if (config_ldb_clk(ref, freq)) 911 return -EINVAL; 912 break; 913 default: 914 printf("Warning:Unsupported or invalid clock type\n"); 915 } 916 917 return 0; 918} 919 920#ifdef CONFIG_MX53 921/* 922 * The clock for the external interface can be set to use internal clock 923 * if fuse bank 4, row 3, bit 2 is set. 924 * This is an undocumented feature and it was confirmed by Freescale's support: 925 * Fuses (but not pins) may be used to configure SATA clocks. 926 * Particularly the i.MX53 Fuse_Map contains the next information 927 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C) 928 * '00' - 100MHz (External) 929 * '01' - 50MHz (External) 930 * '10' - 120MHz, internal (USB PHY) 931 * '11' - Reserved 932*/ 933void mxc_set_sata_internal_clock(void) 934{ 935 u32 *tmp_base = 936 (u32 *)(IIM_BASE_ADDR + 0x180c); 937 938 set_usb_phy_clk(); 939 940 clrsetbits_le32(tmp_base, 0x6, 0x4); 941} 942#endif 943 944#ifndef CONFIG_SPL_BUILD 945/* 946 * Dump some core clockes. 947 */ 948static int do_mx5_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, 949 char *const argv[]) 950{ 951 u32 freq; 952 953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); 954 printf("PLL1 %8d MHz\n", freq / 1000000); 955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); 956 printf("PLL2 %8d MHz\n", freq / 1000000); 957 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); 958 printf("PLL3 %8d MHz\n", freq / 1000000); 959#ifdef CONFIG_MX53 960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); 961 printf("PLL4 %8d MHz\n", freq / 1000000); 962#endif 963 964 printf("\n"); 965 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); 966 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); 967 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); 968 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); 969#ifdef CONFIG_MXC_SPI 970 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); 971#endif 972 return 0; 973} 974 975/***************************************************/ 976 977U_BOOT_CMD( 978 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks, 979 "display clocks", 980 "" 981); 982#endif 983