Searched refs:pll_div (Results 1 - 23 of 23) sorted by relevance

/u-boot/arch/arm/mach-nexell/
H A Dclock.c362 static unsigned int pll_div(int dvo) function
374 ((pll_div(n) >> 0) & 0x3F))
376 ((pll_div(n) >> 0) & 0x3F) / \
377 ((pll_div(n) >> 8) & 0x3F))
380 ((pll_div(DIV_MEM) >> 0) & 0x3F) / \
381 ((pll_div(DIV_MEM) >> 8) & 0x3F))
384 ((pll_div(DIV_MEM) >> 0) & 0x3F))
387 ((pll_div(DIV_MEM) >> 0) & 0x3F) / \
388 ((pll_div(DIV_MEM) >> 8) & 0x3F) / \
389 ((pll_div(DIV_ME
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/u-boot/drivers/clk/imx/
H A Dclk-fracn-gppll.c156 u32 pll_numerator, pll_denominator, pll_div; local
168 pll_div = readl_relaxed(pll->base + PLL_DIV);
169 mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
171 rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
172 odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
229 u32 tmp, pll_div, ana_mfn; local
252 pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |
254 writel_relaxed(pll_div, pll->base + PLL_DIV);
H A Dclk-pll14xx.c134 u32 mdiv, pdiv, sdiv, pll_div; local
136 pll_div = readl(pll->base + 4);
137 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
138 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
139 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
171 u32 pll_div)
175 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
176 old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
170 clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate, u32 pll_div) argument
/u-boot/drivers/clk/ti/
H A Dclk-k3.c305 int pll_div = 0; local
317 pll_div = 1;
319 for (pll_div = 2; pll_div < PLL_MAX_DIV; pll_div++) {
320 pll_tgt = rate / div * pll_div;
327 pll_div = rate / div / osc_freq;
331 (u32)pll_tgt, (u32)rate, pll_div);
/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c34 struct pll_div { struct
55 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
56 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
94 const struct pll_div *div)
289 const struct pll_div *dpll_cfg = NULL;
293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
295 static const struct pll_div dpll_160
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H A Dclk_rk3399.c40 struct pll_div { struct
57 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
58 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
60 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
63 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
64 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
66 static const struct pll_div *apll_l_cfgs[] = {
71 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
72 static const struct pll_div *apll_b_cfgs[] = {
325 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *di
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H A Dclk_rk322x.c43 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
44 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
47 const struct pll_div *div)
326 struct pll_div dpll_cfg;
331 dpll_cfg = (struct pll_div)
335 dpll_cfg = (struct pll_div)
339 dpll_cfg = (struct pll_div)
H A Dclk_rk3066.c37 struct pll_div { struct
81 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
82 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
85 const struct pll_div *div)
118 static const struct pll_div dpll_cfg[] = {
164 static const struct pll_div apll_cfg[] = {
H A Dclk_rk3188.c40 struct pll_div { struct
85 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
86 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
90 const struct pll_div *div, bool has_bwadj)
126 static const struct pll_div dpll_cfg[] = {
172 static const struct pll_div apll_cfg[] = {
H A Dclk_rk3288.c40 struct pll_div { struct
146 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
147 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
148 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
151 const struct pll_div *div)
184 static const struct pll_div dpll_cfg[] = {
233 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
345 struct pll_div npll_config = {0};
H A Dclk_rk3128.c38 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
39 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
42 const struct pll_div *div)
79 static int pll_para_config(u32 freq_hz, struct pll_div *div)
422 struct pll_div cpll_config = {0};
H A Dclk_rk3328.c24 struct pll_div { struct
41 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
42 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
44 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
45 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
47 static const struct pll_div *apll_cfgs[] = {
215 const struct pll_div *div)
H A Dclk_rk3036.c45 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
46 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
49 const struct pll_div *div)
H A Dclk_rv1108.c45 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
46 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
71 const struct pll_div *div)
/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c779 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, argument
786 pll_div, pll_num, pll_denom);
800 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
806 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
812 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
818 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
825 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
902 u32 pll_div, pll_num, pll_denom, post_div = 0; local
946 pll_div = best / hck;
948 pll_num = (best - hck * pll_div) * pll_deno
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/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3036.h58 struct pll_div { struct
H A Dcru_rv1108.h55 struct pll_div { struct
H A Dcru_rk322x.h59 struct pll_div { struct
H A Dcru_rk3128.h65 struct pll_div { struct
/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c611 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, argument
618 pll_div, pll_num, pll_denom);
630 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
635 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
640 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
686 u32 pll_div, pll_num, pll_denom, post_div = 1; local
757 pll_div = best / hck;
759 pll_num = (best - hck * pll_div) * pll_denom / hck;
763 * (24MHz * (pll_div + --------- ))
770 if (enable_pll_video(pll_div, pll_nu
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/u-boot/arch/mips/mach-octeon/
H A Docteon_qlm.c1161 pmode_1.s.pll_div = 0x1e;
2617 .pll_div = 0x19 },
2636 .pll_div = 0x14 },
2655 .pll_div = 0x10 },
2680 .pll_div = 0x19 },
2699 .pll_div = 0x14 },
2718 .pll_div = 0x10 },
2743 .pll_div = 0x28 },
2762 .pll_div = 0x20 },
2785 .pll_div
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/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c40 const struct pll_div dpll_init_cfg = {1, 66, 2, 1};
/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-gserx-defs.h1998 u64 pll_div : 9; member in struct:cvmx_gserx_pll_px_mode_1::cvmx_gserx_pll_px_mode_1_s

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