1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * 5 * Author: 6 * Peng Fan <Peng.Fan@freescale.com> 7 */ 8 9#include <common.h> 10#include <clock_legacy.h> 11#include <command.h> 12#include <div64.h> 13#include <log.h> 14#include <asm/global_data.h> 15#include <asm/io.h> 16#include <linux/errno.h> 17#include <asm/arch/imx-regs.h> 18#include <asm/arch/crm_regs.h> 19#include <asm/arch/clock.h> 20#include <asm/arch/sys_proto.h> 21 22struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) 23 ANATOP_BASE_ADDR; 24struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 25 26#ifdef CONFIG_FSL_ESDHC_IMX 27DECLARE_GLOBAL_DATA_PTR; 28#endif 29 30int get_clocks(void) 31{ 32#ifdef CONFIG_FSL_ESDHC_IMX 33#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR 34 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 35#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR 36 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 37#else 38 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 39#endif 40#endif 41 return 0; 42} 43 44u32 get_ahb_clk(void) 45{ 46 return get_root_clk(AHB_CLK_ROOT); 47} 48 49static u32 get_ipg_clk(void) 50{ 51 /* 52 * The AHB and IPG are fixed at 2:1 ratio, and synchronized to 53 * each other. 54 */ 55 return get_ahb_clk() / 2; 56} 57 58u32 imx_get_uartclk(void) 59{ 60 return get_root_clk(UART_CLK_ROOT); 61} 62 63u32 imx_get_fecclk(void) 64{ 65 return get_root_clk(ENET_AXI_CLK_ROOT); 66} 67 68#ifdef CONFIG_MXC_OCOTP 69void enable_ocotp_clk(unsigned char enable) 70{ 71 clock_enable(CCGR_OCOTP, enable); 72} 73 74void enable_thermal_clk(void) 75{ 76 enable_ocotp_clk(1); 77} 78#endif 79 80void enable_usboh3_clk(unsigned char enable) 81{ 82 u32 target; 83 84 if (enable) { 85 /* disable the clock gate first */ 86 clock_enable(CCGR_USB_HSIC, 0); 87 88 /* 120Mhz */ 89 target = CLK_ROOT_ON | 90 USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK | 91 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 92 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 93 clock_set_target_val(USB_HSIC_CLK_ROOT, target); 94 95 /* enable the clock gate */ 96 clock_enable(CCGR_USB_CTRL, 1); 97 clock_enable(CCGR_USB_HSIC, 1); 98 clock_enable(CCGR_USB_PHY1, 1); 99 clock_enable(CCGR_USB_PHY2, 1); 100 } else { 101 clock_enable(CCGR_USB_CTRL, 0); 102 clock_enable(CCGR_USB_HSIC, 0); 103 clock_enable(CCGR_USB_PHY1, 0); 104 clock_enable(CCGR_USB_PHY2, 0); 105 } 106} 107 108static u32 decode_pll(enum pll_clocks pll, u32 infreq) 109{ 110 u32 reg, div_sel; 111 u32 num, denom; 112 113 /* 114 * Alought there are four choices for the bypass src, 115 * we choose OSC_24M which is the default set in ROM. 116 */ 117 switch (pll) { 118 case PLL_CORE: 119 reg = readl(&ccm_anatop->pll_arm); 120 121 if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) 122 return 0; 123 124 if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK) 125 return MXC_HCLK; 126 127 div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> 128 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT; 129 130 return (infreq * div_sel) / 2; 131 132 case PLL_SYS: 133 reg = readl(&ccm_anatop->pll_480); 134 135 if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK) 136 return 0; 137 138 if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK) 139 return MXC_HCLK; 140 141 if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >> 142 CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0) 143 return 480000000u; 144 else 145 return 528000000u; 146 147 case PLL_ENET: 148 reg = readl(&ccm_anatop->pll_enet); 149 150 if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) 151 return 0; 152 153 if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK) 154 return MXC_HCLK; 155 156 return 1000000000u; 157 158 case PLL_DDR: 159 reg = readl(&ccm_anatop->pll_ddr); 160 161 if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK) 162 return 0; 163 164 num = ccm_anatop->pll_ddr_num; 165 denom = ccm_anatop->pll_ddr_denom; 166 167 if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK) 168 return MXC_HCLK; 169 170 div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >> 171 CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT; 172 173 return infreq * (div_sel + num / denom); 174 175 case PLL_USB: 176 return 480000000u; 177 178 default: 179 printf("Unsupported pll clocks %d\n", pll); 180 break; 181 } 182 183 return 0; 184} 185 186static u32 mxc_get_pll_sys_derive(int derive) 187{ 188 u32 freq, div, frac; 189 u32 reg; 190 191 div = 1; 192 reg = readl(&ccm_anatop->pll_480); 193 freq = decode_pll(PLL_SYS, MXC_HCLK); 194 195 switch (derive) { 196 case PLL_SYS_MAIN_480M_CLK: 197 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK) 198 return 0; 199 else 200 return freq; 201 case PLL_SYS_MAIN_240M_CLK: 202 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK) 203 return 0; 204 else 205 return freq / 2; 206 case PLL_SYS_MAIN_120M_CLK: 207 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK) 208 return 0; 209 else 210 return freq / 4; 211 case PLL_SYS_PFD0_392M_CLK: 212 reg = readl(&ccm_anatop->pfd_480a); 213 if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK) 214 return 0; 215 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >> 216 CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT; 217 break; 218 case PLL_SYS_PFD0_196M_CLK: 219 if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK) 220 return 0; 221 reg = readl(&ccm_anatop->pfd_480a); 222 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >> 223 CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT; 224 div = 2; 225 break; 226 case PLL_SYS_PFD1_332M_CLK: 227 reg = readl(&ccm_anatop->pfd_480a); 228 if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK) 229 return 0; 230 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >> 231 CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT; 232 break; 233 case PLL_SYS_PFD1_166M_CLK: 234 if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK) 235 return 0; 236 reg = readl(&ccm_anatop->pfd_480a); 237 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >> 238 CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT; 239 div = 2; 240 break; 241 case PLL_SYS_PFD2_270M_CLK: 242 reg = readl(&ccm_anatop->pfd_480a); 243 if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK) 244 return 0; 245 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >> 246 CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT; 247 break; 248 case PLL_SYS_PFD2_135M_CLK: 249 if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK) 250 return 0; 251 reg = readl(&ccm_anatop->pfd_480a); 252 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >> 253 CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT; 254 div = 2; 255 break; 256 case PLL_SYS_PFD3_CLK: 257 reg = readl(&ccm_anatop->pfd_480a); 258 if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK) 259 return 0; 260 frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >> 261 CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT; 262 break; 263 case PLL_SYS_PFD4_CLK: 264 reg = readl(&ccm_anatop->pfd_480b); 265 if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK) 266 return 0; 267 frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >> 268 CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT; 269 break; 270 case PLL_SYS_PFD5_CLK: 271 reg = readl(&ccm_anatop->pfd_480b); 272 if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK) 273 return 0; 274 frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >> 275 CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT; 276 break; 277 case PLL_SYS_PFD6_CLK: 278 reg = readl(&ccm_anatop->pfd_480b); 279 if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK) 280 return 0; 281 frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >> 282 CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT; 283 break; 284 case PLL_SYS_PFD7_CLK: 285 reg = readl(&ccm_anatop->pfd_480b); 286 if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK) 287 return 0; 288 frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >> 289 CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT; 290 break; 291 default: 292 printf("Error derived pll_sys clock %d\n", derive); 293 return 0; 294 } 295 296 return ((freq / frac) * 18) / div; 297} 298 299static u32 mxc_get_pll_enet_derive(int derive) 300{ 301 u32 freq, reg; 302 303 freq = decode_pll(PLL_ENET, MXC_HCLK); 304 reg = readl(&ccm_anatop->pll_enet); 305 306 switch (derive) { 307 case PLL_ENET_MAIN_500M_CLK: 308 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK) 309 return freq / 2; 310 break; 311 case PLL_ENET_MAIN_250M_CLK: 312 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK) 313 return freq / 4; 314 break; 315 case PLL_ENET_MAIN_125M_CLK: 316 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK) 317 return freq / 8; 318 break; 319 case PLL_ENET_MAIN_100M_CLK: 320 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK) 321 return freq / 10; 322 break; 323 case PLL_ENET_MAIN_50M_CLK: 324 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK) 325 return freq / 20; 326 break; 327 case PLL_ENET_MAIN_40M_CLK: 328 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK) 329 return freq / 25; 330 break; 331 case PLL_ENET_MAIN_25M_CLK: 332 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK) 333 return freq / 40; 334 break; 335 default: 336 printf("Error derived pll_enet clock %d\n", derive); 337 break; 338 } 339 340 return 0; 341} 342 343static u32 mxc_get_pll_ddr_derive(int derive) 344{ 345 u32 freq, reg; 346 347 freq = decode_pll(PLL_DDR, MXC_HCLK); 348 reg = readl(&ccm_anatop->pll_ddr); 349 350 switch (derive) { 351 case PLL_DRAM_MAIN_1066M_CLK: 352 return freq; 353 case PLL_DRAM_MAIN_533M_CLK: 354 if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK) 355 return freq / 2; 356 break; 357 default: 358 printf("Error derived pll_ddr clock %d\n", derive); 359 break; 360 } 361 362 return 0; 363} 364 365static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive) 366{ 367 switch (pll) { 368 case PLL_SYS: 369 return mxc_get_pll_sys_derive(derive); 370 case PLL_ENET: 371 return mxc_get_pll_enet_derive(derive); 372 case PLL_DDR: 373 return mxc_get_pll_ddr_derive(derive); 374 default: 375 printf("Error pll.\n"); 376 return 0; 377 } 378} 379 380static u32 get_root_src_clk(enum clk_root_src root_src) 381{ 382 switch (root_src) { 383 case OSC_24M_CLK: 384 return 24000000u; 385 case PLL_ARM_MAIN_800M_CLK: 386 return decode_pll(PLL_CORE, MXC_HCLK); 387 388 case PLL_SYS_MAIN_480M_CLK: 389 case PLL_SYS_MAIN_240M_CLK: 390 case PLL_SYS_MAIN_120M_CLK: 391 case PLL_SYS_PFD0_392M_CLK: 392 case PLL_SYS_PFD0_196M_CLK: 393 case PLL_SYS_PFD1_332M_CLK: 394 case PLL_SYS_PFD1_166M_CLK: 395 case PLL_SYS_PFD2_270M_CLK: 396 case PLL_SYS_PFD2_135M_CLK: 397 case PLL_SYS_PFD3_CLK: 398 case PLL_SYS_PFD4_CLK: 399 case PLL_SYS_PFD5_CLK: 400 case PLL_SYS_PFD6_CLK: 401 case PLL_SYS_PFD7_CLK: 402 return mxc_get_pll_derive(PLL_SYS, root_src); 403 404 case PLL_ENET_MAIN_500M_CLK: 405 case PLL_ENET_MAIN_250M_CLK: 406 case PLL_ENET_MAIN_125M_CLK: 407 case PLL_ENET_MAIN_100M_CLK: 408 case PLL_ENET_MAIN_50M_CLK: 409 case PLL_ENET_MAIN_40M_CLK: 410 case PLL_ENET_MAIN_25M_CLK: 411 return mxc_get_pll_derive(PLL_ENET, root_src); 412 413 case PLL_DRAM_MAIN_1066M_CLK: 414 case PLL_DRAM_MAIN_533M_CLK: 415 return mxc_get_pll_derive(PLL_DDR, root_src); 416 417 case PLL_AUDIO_MAIN_CLK: 418 return decode_pll(PLL_AUDIO, MXC_HCLK); 419 case PLL_VIDEO_MAIN_CLK: 420 return decode_pll(PLL_VIDEO, MXC_HCLK); 421 422 case PLL_USB_MAIN_480M_CLK: 423 return decode_pll(PLL_USB, MXC_HCLK); 424 425 case REF_1M_CLK: 426 return 1000000; 427 case OSC_32K_CLK: 428 return MXC_CLK32; 429 430 case EXT_CLK_1: 431 case EXT_CLK_2: 432 case EXT_CLK_3: 433 case EXT_CLK_4: 434 printf("No EXT CLK supported??\n"); 435 break; 436 }; 437 438 return 0; 439} 440 441u32 get_root_clk(enum clk_root_index clock_id) 442{ 443 enum clk_root_src root_src; 444 u32 post_podf, pre_podf, auto_podf, root_src_clk; 445 int auto_en; 446 447 if (clock_root_enabled(clock_id) <= 0) 448 return 0; 449 450 if (clock_get_prediv(clock_id, &pre_podf) < 0) 451 return 0; 452 453 if (clock_get_postdiv(clock_id, &post_podf) < 0) 454 return 0; 455 456 if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0) 457 return 0; 458 459 if (auto_en == 0) 460 auto_podf = 0; 461 462 if (clock_get_src(clock_id, &root_src) < 0) 463 return 0; 464 465 root_src_clk = get_root_src_clk(root_src); 466 467 /* 468 * bypass clk is ignored. 469 */ 470 471 return root_src_clk / (post_podf + 1) / (pre_podf + 1) / 472 (auto_podf + 1); 473} 474 475static u32 get_ddrc_clk(void) 476{ 477 u32 reg, freq; 478 enum root_post_div post_div; 479 480 reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root); 481 if (reg & CLK_ROOT_MUX_MASK) 482 /* DRAM_ALT_CLK_ROOT */ 483 freq = get_root_clk(DRAM_ALT_CLK_ROOT); 484 else 485 /* PLL_DRAM_MAIN_1066M_CLK */ 486 freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK); 487 488 post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK; 489 490 return freq / (post_div + 1) / 2; 491} 492 493unsigned int mxc_get_clock(enum mxc_clock clk) 494{ 495 switch (clk) { 496 case MXC_ARM_CLK: 497 return get_root_clk(ARM_A7_CLK_ROOT); 498 case MXC_AXI_CLK: 499 return get_root_clk(MAIN_AXI_CLK_ROOT); 500 case MXC_AHB_CLK: 501 return get_root_clk(AHB_CLK_ROOT); 502 case MXC_IPG_CLK: 503 return get_ipg_clk(); 504 case MXC_I2C_CLK: 505 return 60000000; 506 case MXC_UART_CLK: 507 return get_root_clk(UART1_CLK_ROOT); 508 case MXC_CSPI_CLK: 509 return get_root_clk(ECSPI1_CLK_ROOT); 510 case MXC_DDR_CLK: 511 return get_ddrc_clk(); 512 case MXC_ESDHC_CLK: 513 return get_root_clk(USDHC1_CLK_ROOT); 514 case MXC_ESDHC2_CLK: 515 return get_root_clk(USDHC2_CLK_ROOT); 516 case MXC_ESDHC3_CLK: 517 return get_root_clk(USDHC3_CLK_ROOT); 518 default: 519 printf("Unsupported mxc_clock %d\n", clk); 520 break; 521 } 522 523 return 0; 524} 525 526#ifdef CONFIG_SYS_I2C_MXC 527/* i2c_num can be 0 - 3 */ 528int enable_i2c_clk(unsigned char enable, unsigned i2c_num) 529{ 530 u32 target; 531 532 if (i2c_num >= 4) 533 return -EINVAL; 534 535 if (enable) { 536 clock_enable(CCGR_I2C1 + i2c_num, 0); 537 538 /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */ 539 540 target = CLK_ROOT_ON | 541 I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK | 542 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 543 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 544 clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target); 545 546 clock_enable(CCGR_I2C1 + i2c_num, 1); 547 } else { 548 clock_enable(CCGR_I2C1 + i2c_num, 0); 549 } 550 551 return 0; 552} 553#endif 554 555static void init_clk_esdhc(void) 556{ 557 u32 target; 558 559 /* disable the clock gate first */ 560 clock_enable(CCGR_USDHC1, 0); 561 clock_enable(CCGR_USDHC2, 0); 562 clock_enable(CCGR_USDHC3, 0); 563 564 /* 196: 392/2 */ 565 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | 566 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 567 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 568 clock_set_target_val(USDHC1_CLK_ROOT, target); 569 570 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | 571 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 572 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 573 clock_set_target_val(USDHC2_CLK_ROOT, target); 574 575 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | 576 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 577 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 578 clock_set_target_val(USDHC3_CLK_ROOT, target); 579 580 /* enable the clock gate */ 581 clock_enable(CCGR_USDHC1, 1); 582 clock_enable(CCGR_USDHC2, 1); 583 clock_enable(CCGR_USDHC3, 1); 584} 585 586static void init_clk_uart(void) 587{ 588 u32 target; 589 590 /* disable the clock gate first */ 591 clock_enable(CCGR_UART1, 0); 592 clock_enable(CCGR_UART2, 0); 593 clock_enable(CCGR_UART3, 0); 594 clock_enable(CCGR_UART4, 0); 595 clock_enable(CCGR_UART5, 0); 596 clock_enable(CCGR_UART6, 0); 597 clock_enable(CCGR_UART7, 0); 598 599 /* 24Mhz */ 600 target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK | 601 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 602 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 603 clock_set_target_val(UART1_CLK_ROOT, target); 604 605 target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK | 606 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 607 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 608 clock_set_target_val(UART2_CLK_ROOT, target); 609 610 target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK | 611 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 612 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 613 clock_set_target_val(UART3_CLK_ROOT, target); 614 615 target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK | 616 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 617 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 618 clock_set_target_val(UART4_CLK_ROOT, target); 619 620 target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK | 621 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 622 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 623 clock_set_target_val(UART5_CLK_ROOT, target); 624 625 target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK | 626 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 627 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 628 clock_set_target_val(UART6_CLK_ROOT, target); 629 630 target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK | 631 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 632 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 633 clock_set_target_val(UART7_CLK_ROOT, target); 634 635 /* enable the clock gate */ 636 clock_enable(CCGR_UART1, 1); 637 clock_enable(CCGR_UART2, 1); 638 clock_enable(CCGR_UART3, 1); 639 clock_enable(CCGR_UART4, 1); 640 clock_enable(CCGR_UART5, 1); 641 clock_enable(CCGR_UART6, 1); 642 clock_enable(CCGR_UART7, 1); 643} 644 645static void init_clk_weim(void) 646{ 647 u32 target; 648 649 /* disable the clock gate first */ 650 clock_enable(CCGR_WEIM, 0); 651 652 /* 120Mhz */ 653 target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK | 654 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 655 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 656 clock_set_target_val(EIM_CLK_ROOT, target); 657 658 /* enable the clock gate */ 659 clock_enable(CCGR_WEIM, 1); 660} 661 662static void init_clk_ecspi(void) 663{ 664 u32 target; 665 666 /* disable the clock gate first */ 667 clock_enable(CCGR_ECSPI1, 0); 668 clock_enable(CCGR_ECSPI2, 0); 669 clock_enable(CCGR_ECSPI3, 0); 670 clock_enable(CCGR_ECSPI4, 0); 671 672 /* 60Mhz: 240/4 */ 673 target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | 674 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 675 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 676 clock_set_target_val(ECSPI1_CLK_ROOT, target); 677 678 target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | 679 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 680 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 681 clock_set_target_val(ECSPI2_CLK_ROOT, target); 682 683 target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | 684 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 685 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 686 clock_set_target_val(ECSPI3_CLK_ROOT, target); 687 688 target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | 689 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 690 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 691 clock_set_target_val(ECSPI4_CLK_ROOT, target); 692 693 /* enable the clock gate */ 694 clock_enable(CCGR_ECSPI1, 1); 695 clock_enable(CCGR_ECSPI2, 1); 696 clock_enable(CCGR_ECSPI3, 1); 697 clock_enable(CCGR_ECSPI4, 1); 698} 699 700static void init_clk_wdog(void) 701{ 702 u32 target; 703 704 /* disable the clock gate first */ 705 clock_enable(CCGR_WDOG1, 0); 706 clock_enable(CCGR_WDOG2, 0); 707 clock_enable(CCGR_WDOG3, 0); 708 clock_enable(CCGR_WDOG4, 0); 709 710 /* 24Mhz */ 711 target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK | 712 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 713 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 714 clock_set_target_val(WDOG_CLK_ROOT, target); 715 716 /* enable the clock gate */ 717 clock_enable(CCGR_WDOG1, 1); 718 clock_enable(CCGR_WDOG2, 1); 719 clock_enable(CCGR_WDOG3, 1); 720 clock_enable(CCGR_WDOG4, 1); 721} 722 723#ifdef CONFIG_MXC_EPDC 724static void init_clk_epdc(void) 725{ 726 u32 target; 727 728 /* disable the clock gate first */ 729 clock_enable(CCGR_EPDC, 0); 730 731 /* 24Mhz */ 732 target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK | 733 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 734 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12); 735 clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target); 736 737 /* enable the clock gate */ 738 clock_enable(CCGR_EPDC, 1); 739} 740#endif 741 742static int enable_pll_enet(void) 743{ 744 u32 reg; 745 s32 timeout = 100000; 746 747 reg = readl(&ccm_anatop->pll_enet); 748 /* If pll_enet powered up, no need to set it again */ 749 if (reg & ANADIG_PLL_ENET_PWDN_MASK) { 750 reg &= ~ANADIG_PLL_ENET_PWDN_MASK; 751 writel(reg, &ccm_anatop->pll_enet); 752 753 while (timeout--) { 754 if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK) 755 break; 756 } 757 758 if (timeout <= 0) { 759 /* If timeout, we set pwdn for pll_enet. */ 760 reg |= ANADIG_PLL_ENET_PWDN_MASK; 761 return -ETIME; 762 } 763 } 764 765 /* Clear bypass */ 766 writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr); 767 768 writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 769 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 770 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 771 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 772 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 773 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 774 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK), 775 &ccm_anatop->pll_enet_set); 776 777 return 0; 778} 779static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, 780 u32 post_div) 781{ 782 u32 reg = 0; 783 ulong start; 784 785 debug("pll5 div = %d, num = %d, denom = %d\n", 786 pll_div, pll_num, pll_denom); 787 788 /* Power up PLL5 video and disable its output */ 789 writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK | 790 CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK | 791 CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK | 792 CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK | 793 CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK | 794 CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK, 795 &ccm_anatop->pll_video_clr); 796 797 /* Set div, num and denom */ 798 switch (post_div) { 799 case 1: 800 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | 801 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) | 802 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0), 803 &ccm_anatop->pll_video_set); 804 break; 805 case 2: 806 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | 807 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) | 808 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0), 809 &ccm_anatop->pll_video_set); 810 break; 811 case 3: 812 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | 813 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) | 814 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1), 815 &ccm_anatop->pll_video_set); 816 break; 817 case 4: 818 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | 819 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) | 820 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3), 821 &ccm_anatop->pll_video_set); 822 break; 823 case 0: 824 default: 825 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | 826 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) | 827 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0), 828 &ccm_anatop->pll_video_set); 829 break; 830 } 831 832 writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num), 833 &ccm_anatop->pll_video_num); 834 835 writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom), 836 &ccm_anatop->pll_video_denom); 837 838 /* Wait PLL5 lock */ 839 start = get_timer(0); /* Get current timestamp */ 840 841 do { 842 reg = readl(&ccm_anatop->pll_video); 843 if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) { 844 /* Enable PLL out */ 845 writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK, 846 &ccm_anatop->pll_video_set); 847 return 0; 848 } 849 } while (get_timer(0) < (start + 10)); /* Wait 10ms */ 850 851 printf("Lock PLL5 timeout\n"); 852 853 return 1; 854} 855 856int set_clk_qspi(void) 857{ 858 u32 target; 859 860 /* disable the clock gate first */ 861 clock_enable(CCGR_QSPI, 0); 862 863 /* 49M: 392/2/4 */ 864 target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK | 865 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 866 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 867 clock_set_target_val(QSPI_CLK_ROOT, target); 868 869 /* enable the clock gate */ 870 clock_enable(CCGR_QSPI, 1); 871 872 return 0; 873} 874 875int set_clk_nand(void) 876{ 877 u32 target; 878 879 /* disable the clock gate first */ 880 clock_enable(CCGR_RAWNAND, 0); 881 882 enable_pll_enet(); 883 /* 100: 500/5 */ 884 target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK | 885 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 886 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5); 887 clock_set_target_val(NAND_CLK_ROOT, target); 888 889 /* enable the clock gate */ 890 clock_enable(CCGR_RAWNAND, 1); 891 892 return 0; 893} 894 895void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) 896{ 897 u32 hck = MXC_HCLK/1000; 898 u32 min = hck * 27; 899 u32 max = hck * 54; 900 u32 temp, best = 0; 901 u32 i, j, pred = 1, postd = 1; 902 u32 pll_div, pll_num, pll_denom, post_div = 0; 903 u32 target; 904 905 debug("mxs_set_lcdclk, freq = %d\n", freq); 906 907 clock_enable(CCGR_LCDIF, 0); 908 909 temp = (freq * 8 * 8); 910 if (temp < min) { 911 for (i = 1; i <= 4; i++) { 912 if ((temp * (1 << i)) > min) { 913 post_div = i; 914 freq = (freq * (1 << i)); 915 break; 916 } 917 } 918 919 if (5 == i) { 920 printf("Fail to set rate to %u kHz", freq); 921 return; 922 } 923 } 924 925 for (i = 1; i <= 8; i++) { 926 for (j = 1; j <= 8; j++) { 927 temp = freq * i * j; 928 if (temp > max || temp < min) 929 continue; 930 931 if (best == 0 || temp < best) { 932 best = temp; 933 pred = i; 934 postd = j; 935 } 936 } 937 } 938 939 if (best == 0) { 940 printf("Fail to set rate to %u kHz", freq); 941 return; 942 } 943 944 debug("best %d, pred = %d, postd = %d\n", best, pred, postd); 945 946 pll_div = best / hck; 947 pll_denom = 1000000; 948 pll_num = (best - hck * pll_div) * pll_denom / hck; 949 950 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) 951 return; 952 953 target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK | 954 CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1)); 955 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target); 956 957 clock_enable(CCGR_LCDIF, 1); 958} 959 960#ifdef CONFIG_FEC_MXC 961int set_clk_enet(enum enet_freq type) 962{ 963 u32 target; 964 int ret; 965 u32 enet1_ref, enet2_ref; 966 967 /* disable the clock first */ 968 clock_enable(CCGR_ENET1, 0); 969 clock_enable(CCGR_ENET2, 0); 970 971 switch (type) { 972 case ENET_125MHZ: 973 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; 974 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; 975 break; 976 case ENET_50MHZ: 977 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; 978 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; 979 break; 980 case ENET_25MHZ: 981 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; 982 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; 983 break; 984 default: 985 return -EINVAL; 986 } 987 988 ret = enable_pll_enet(); 989 if (ret != 0) 990 return ret; 991 992 /* set enet axi clock 196M: 392/2 */ 993 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK | 994 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 995 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); 996 clock_set_target_val(ENET_AXI_CLK_ROOT, target); 997 998 target = CLK_ROOT_ON | enet1_ref | 999 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 1000 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 1001 clock_set_target_val(ENET1_REF_CLK_ROOT, target); 1002 1003 target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | 1004 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 1005 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 1006 clock_set_target_val(ENET1_TIME_CLK_ROOT, target); 1007 1008 target = CLK_ROOT_ON | enet2_ref | 1009 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 1010 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 1011 clock_set_target_val(ENET2_REF_CLK_ROOT, target); 1012 1013 target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | 1014 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 1015 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 1016 clock_set_target_val(ENET2_TIME_CLK_ROOT, target); 1017 1018#ifdef CONFIG_FEC_MXC_25M_REF_CLK 1019 target = CLK_ROOT_ON | 1020 ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK | 1021 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 1022 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 1023 clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target); 1024#endif 1025 /* enable clock */ 1026 clock_enable(CCGR_ENET1, 1); 1027 clock_enable(CCGR_ENET2, 1); 1028 1029 return 0; 1030} 1031#endif 1032 1033/* Configure PLL/PFD freq */ 1034void clock_init(void) 1035{ 1036/* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET 1037 * In u-boot, we have to: 1038 * 1. Configure PFD3- PFD7 for freq we needed in u-boot 1039 * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate 1040 * interface. The clocks for these peripherals are enabled after this intialization. 1041 * 3. Other peripherals with set clock rate interface does not be set in this function. 1042 */ 1043 u32 reg; 1044 1045 /* 1046 * Configure PFD4 to 392M 1047 * 480M * 18 / 0x16 = 392M 1048 */ 1049 reg = readl(&ccm_anatop->pfd_480b); 1050 1051 reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK | 1052 CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK); 1053 reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL; 1054 1055 writel(reg, &ccm_anatop->pfd_480b); 1056 1057 init_clk_esdhc(); 1058 init_clk_uart(); 1059 init_clk_weim(); 1060 init_clk_ecspi(); 1061 init_clk_wdog(); 1062#ifdef CONFIG_MXC_EPDC 1063 init_clk_epdc(); 1064#endif 1065 1066 enable_usboh3_clk(1); 1067 1068 clock_enable(CCGR_SNVS, 1); 1069 1070#ifdef CONFIG_NAND_MXS 1071 clock_enable(CCGR_RAWNAND, 1); 1072#endif 1073 1074 if (IS_ENABLED(CONFIG_IMX_RDC)) { 1075 clock_enable(CCGR_RDC, 1); 1076 clock_enable(CCGR_SEMA1, 1); 1077 clock_enable(CCGR_SEMA2, 1); 1078 } 1079} 1080 1081#ifdef CONFIG_IMX_HAB 1082void hab_caam_clock_enable(unsigned char enable) 1083{ 1084 if (enable) 1085 clock_enable(CCGR_CAAM, 1); 1086 else 1087 clock_enable(CCGR_CAAM, 0); 1088} 1089#endif 1090 1091#ifdef CONFIG_MXC_EPDC 1092void epdc_clock_enable(void) 1093{ 1094 clock_enable(CCGR_EPDC, 1); 1095} 1096void epdc_clock_disable(void) 1097{ 1098 clock_enable(CCGR_EPDC, 0); 1099} 1100#endif 1101 1102#ifndef CONFIG_SPL_BUILD 1103/* 1104 * Dump some core clockes. 1105 */ 1106int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, 1107 char *const argv[]) 1108{ 1109 u32 freq; 1110 freq = decode_pll(PLL_CORE, MXC_HCLK); 1111 printf("PLL_CORE %8d MHz\n", freq / 1000000); 1112 freq = decode_pll(PLL_SYS, MXC_HCLK); 1113 printf("PLL_SYS %8d MHz\n", freq / 1000000); 1114 freq = decode_pll(PLL_ENET, MXC_HCLK); 1115 printf("PLL_NET %8d MHz\n", freq / 1000000); 1116 1117 printf("\n"); 1118 1119 printf("IPG %8u kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); 1120 printf("UART %8u kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); 1121#ifdef CONFIG_MXC_SPI 1122 printf("CSPI %8u kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); 1123#endif 1124 printf("AHB %8u kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); 1125 printf("AXI %8u kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); 1126 printf("DDR %8u kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); 1127 printf("USDHC1 %8u kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); 1128 printf("USDHC2 %8u kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); 1129 printf("USDHC3 %8u kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); 1130 1131 return 0; 1132} 1133 1134U_BOOT_CMD( 1135 clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks, 1136 "display clocks", 1137 "" 1138); 1139#endif 1140