Searched refs:mdio (Results 1 - 23 of 23) sorted by relevance

/u-boot/drivers/net/ti/
H A Dcpsw_mdio.c121 static void cpsw_mdio_disable(struct cpsw_mdio *mdio) argument
125 reg = readl(&mdio->regs->control);
128 writel(reg, &mdio->regs->control);
131 static void cpsw_mdio_enable_manual_mode(struct cpsw_mdio *mdio) argument
136 reg = readl(&mdio->regs->poll);
139 writel(reg, &mdio->regs->poll);
142 static void cpsw_mdio_sw_set_bit(struct cpsw_mdio *mdio, argument
147 reg = readl(&mdio->regs->manualif);
152 writel(reg, &mdio->regs->manualif);
156 writel(reg, &mdio
167 cpsw_mdio_sw_clr_bit(struct cpsw_mdio *mdio, enum cpsw_mdio_manual bit) argument
193 cpsw_mdio_test_man_bit(struct cpsw_mdio *mdio, enum cpsw_mdio_manual bit) argument
202 cpsw_mdio_toggle_man_bit(struct cpsw_mdio *mdio, enum cpsw_mdio_manual bit) argument
209 cpsw_mdio_man_send_pattern(struct cpsw_mdio *mdio, u32 bitrange, u32 val) argument
224 cpsw_mdio_sw_preamble(struct cpsw_mdio *mdio) argument
252 struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus); local
309 struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus); local
349 cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio) argument
359 struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus); local
385 struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus); local
407 struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus); local
473 struct cpsw_mdio *mdio = bus->priv; local
[all...]
H A Dkeystone_net.c572 mdio_bus = cpsw_mdio_init("ethernet-mdio",
676 ofnode phy, mdio; local
699 mdio = ofnode_get_parent(phy);
700 if (!ofnode_valid(mdio)) {
701 pr_err("mdio dt not found\n");
704 priv->mdio_base = ofnode_get_addr(mdio);
/u-boot/test/dm/
H A Dmdio_mux.c25 struct udevice *mdio_ch0, *mdio_ch1, *mdio; local
32 ut_assertok(uclass_get_device_by_name(UCLASS_MDIO_MUX, "mdio-mux-test",
35 ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-ch-test@0",
37 ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-ch-test@1",
40 ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-test", &mdio));
51 ops_parent = mdio_get_ops(mdio);
69 reg = dm_mdio_read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
74 reg = dm_mdio_read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
H A DMakefile67 obj-$(CONFIG_DM_MDIO) += mdio.o
/u-boot/drivers/net/
H A Dmdio_mux_sandbox.c22 struct udevice *mdio; local
26 * find the sandbox parent mdio and write a register on the PHY there
29 err = uclass_get_device_by_name(UCLASS_MDIO, "mdio-test", &mdio);
32 return dm_mdio_write(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
84 { .compatible = "sandbox,mdio-mux" },
H A DMakefile58 obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
H A Dfec_mxc.c1069 ofnode mdio; local
1075 ofnode_for_each_subnode(mdio, dev_ofnode(dev)) {
1076 name = ofnode_get_name(mdio);
1078 if (strcmp(name, "mdio"))
1082 name, mdio, &mdiodev);
1089 ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdiodev);
H A Dmt7620-eth.c27 #include <linux/mdio.h>
H A Dmtk_eth.c27 #include <linux/mdio.h>
1915 subnode = ofnode_find_subnode(dev_ofnode(dev), "mdio");
H A Dmvpp2.c45 #include <linux/mdio.h>
/u-boot/net/
H A DMakefile15 obj-$(CONFIG_DM_MDIO) += mdio-uclass.o
16 obj-$(CONFIG_DM_MDIO_MUX) += mdio-mux-uclass.o
H A Dmdio-uclass.c317 UCLASS_DRIVER(mdio) = { variable
319 .name = "mdio",
/u-boot/board/gdsys/common/
H A Dihs_mdio.c56 FPGA_GET_REG(info->fpga, mdio.control, &val);
66 FPGA_SET_REG(info->fpga, mdio.control, val);
75 FPGA_SET_REG(info->fpga, mdio.address_data, val);
85 FPGA_GET_REG(info->fpga, mdio.rx_data, &val);
/u-boot/drivers/pinctrl/renesas/
H A Dpinctrl-rzn1.c163 static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl_priv *priv, int mdio, argument
166 debug("setting mdio%d to %u\n", mdio, func);
168 level2_write(priv->regmap, l2_mdio[mdio], func);
/u-boot/drivers/net/fm/
H A Deth.c663 void *mdio; local
671 mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
672 debug("MDIO %d @ %p\n", fm_eth->num, mdio);
682 init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
685 init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
/u-boot/drivers/net/octeon/
H A Docteon_mdio.c21 #include <mach/cvmx-mdio.h>
200 debug("mdio clock phase: %d clocks\n", smi_clk.s.phase);
215 { .compatible = "cavium,octeon-3860-mdio" },
H A Docteon_eth.c58 #include <mach/cvmx-mdio.h>
/u-boot/include/
H A Dphy.h21 #include <linux/mdio.h>
/u-boot/cmd/
H A Dmdio.c318 mdio, 6, 1, do_mdio,
321 "mdio read <phydev> [<devad>.]<reg> - "
323 "mdio write <phydev> [<devad>.]<reg> <data> - "
325 "mdio rx <phydev> [<devad>.]<reg> - "
327 "mdio wx <phydev> [<devad>.]<reg> <data> - "
H A DMakefile116 obj-$(CONFIG_CMD_MDIO) += mdio.o
/u-boot/drivers/net/phy/
H A Dnxp-c45-tja11xx.c13 #include <linux/mdio.h>
/u-boot/drivers/pinctrl/qcom/
H A Dpinctrl-ipq4019.c99 QCA_PIN_FUNCTION(mdio),
147 PINGROUP(6, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
237 PINGROUP(53, qpic, mdio, i2s_tx, prng_rosc, NA, tm, wifi0, wifi1, NA,
/u-boot/arch/mips/mach-octeon/
H A Dcvmx-helper-board.c27 #include <mach/cvmx-mdio.h>
551 "mdio-parent-bus");
1068 "cavium,octeon-3860-mdio")) {
1304 "cavium,mdio-mux");
1309 printf("Error reading mdio mux information for ipd port %d\n",
1315 "cavium,octeon-3860-mdio");
1321 debug("ERROR : unable to get reg property in phy mdio\n");

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