1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 5 * (C) Copyright 2008 Armadeus Systems nc 6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 8 */ 9 10#include <cpu_func.h> 11#include <dm.h> 12#include <env.h> 13#include <log.h> 14#include <malloc.h> 15#include <memalign.h> 16#include <miiphy.h> 17#include <net.h> 18#include <netdev.h> 19#include <asm/cache.h> 20#include <asm/global_data.h> 21#include <linux/delay.h> 22#include <power/regulator.h> 23 24#include <asm/io.h> 25#include <linux/errno.h> 26#include <linux/compiler.h> 27 28#include <asm/arch/clock.h> 29#include <asm/arch/imx-regs.h> 30#include <asm/mach-imx/sys_proto.h> 31#include <asm-generic/gpio.h> 32#include <dm/device_compat.h> 33#include <dm/lists.h> 34 35#include "fec_mxc.h" 36#include <eth_phy.h> 37 38DECLARE_GLOBAL_DATA_PTR; 39 40/* 41 * Timeout the transfer after 5 mS. This is usually a bit more, since 42 * the code in the tightloops this timeout is used in adds some overhead. 43 */ 44#define FEC_XFER_TIMEOUT 5000 45 46/* 47 * The standard 32-byte DMA alignment does not work on mx6solox, which requires 48 * 64-byte alignment in the DMA RX FEC buffer. 49 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also 50 * satisfies the alignment on other SoCs (32-bytes) 51 */ 52#define FEC_DMA_RX_MINALIGN 64 53 54#ifndef CONFIG_MII 55#error "CONFIG_MII has to be defined!" 56#endif 57 58/* 59 * The i.MX28 operates with packets in big endian. We need to swap them before 60 * sending and after receiving. 61 */ 62#ifdef CONFIG_MX28 63#define CFG_FEC_MXC_SWAP_PACKET 64#endif 65 66#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) 67 68/* Check various alignment issues at compile time */ 69#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) 70#error "ARCH_DMA_MINALIGN must be multiple of 16!" 71#endif 72 73#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ 74 (PKTALIGN % ARCH_DMA_MINALIGN != 0)) 75#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" 76#endif 77 78#undef DEBUG 79 80#ifdef CFG_FEC_MXC_SWAP_PACKET 81static void swap_packet(uint32_t *packet, int length) 82{ 83 int i; 84 85 for (i = 0; i < DIV_ROUND_UP(length, 4); i++) 86 packet[i] = __swab32(packet[i]); 87} 88#endif 89 90/* MII-interface related functions */ 91static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr, 92 uint8_t regaddr) 93{ 94 uint32_t reg; /* convenient holder for the PHY register */ 95 uint32_t phy; /* convenient holder for the PHY */ 96 uint32_t start; 97 int val; 98 99 /* 100 * reading from any PHY's register is done by properly 101 * programming the FEC's MII data register. 102 */ 103 writel(FEC_IEVENT_MII, ð->ievent); 104 reg = regaddr << FEC_MII_DATA_RA_SHIFT; 105 phy = phyaddr << FEC_MII_DATA_PA_SHIFT; 106 107 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 108 phy | reg, ð->mii_data); 109 110 /* wait for the related interrupt */ 111 start = get_timer(0); 112 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 113 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 114 printf("Read MDIO failed...\n"); 115 return -1; 116 } 117 } 118 119 /* clear mii interrupt bit */ 120 writel(FEC_IEVENT_MII, ð->ievent); 121 122 /* it's now safe to read the PHY's register */ 123 val = (unsigned short)readl(ð->mii_data); 124 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, 125 regaddr, val); 126 return val; 127} 128 129#ifndef imx_get_fecclk 130u32 __weak imx_get_fecclk(void) 131{ 132 return 0; 133} 134#endif 135 136static int fec_get_clk_rate(void *udev, int idx) 137{ 138 struct fec_priv *fec; 139 struct udevice *dev; 140 int ret; 141 142 if (IS_ENABLED(CONFIG_IMX8) || 143 CONFIG_IS_ENABLED(CLK_CCF)) { 144 dev = udev; 145 if (!dev) { 146 ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev); 147 if (ret < 0) { 148 debug("Can't get FEC udev: %d\n", ret); 149 return ret; 150 } 151 } 152 153 fec = dev_get_priv(dev); 154 if (fec) 155 return fec->clk_rate; 156 157 return -EINVAL; 158 } else { 159 return imx_get_fecclk(); 160 } 161} 162 163static void fec_mii_setspeed(struct ethernet_regs *eth) 164{ 165 /* 166 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 167 * and do not drop the Preamble. 168 * 169 * The i.MX28 and i.MX6 types have another field in the MSCR (aka 170 * MII_SPEED) register that defines the MDIO output hold time. Earlier 171 * versions are RAZ there, so just ignore the difference and write the 172 * register always. 173 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 174 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 175 * output. 176 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 177 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 178 * holdtime cannot result in a value greater than 3. 179 */ 180 u32 pclk; 181 u32 speed; 182 u32 hold; 183 int ret; 184 185 ret = fec_get_clk_rate(NULL, 0); 186 if (ret < 0) { 187 printf("Can't find FEC0 clk rate: %d\n", ret); 188 return; 189 } 190 pclk = ret; 191 speed = DIV_ROUND_UP(pclk, 5000000); 192 hold = DIV_ROUND_UP(pclk, 100000000) - 1; 193 194#ifdef FEC_QUIRK_ENET_MAC 195 speed--; 196#endif 197 writel(speed << 1 | hold << 8, ð->mii_speed); 198 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); 199} 200 201static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr, 202 uint8_t regaddr, uint16_t data) 203{ 204 uint32_t reg; /* convenient holder for the PHY register */ 205 uint32_t phy; /* convenient holder for the PHY */ 206 uint32_t start; 207 208 reg = regaddr << FEC_MII_DATA_RA_SHIFT; 209 phy = phyaddr << FEC_MII_DATA_PA_SHIFT; 210 211 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 212 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); 213 214 /* wait for the MII interrupt */ 215 start = get_timer(0); 216 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 217 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 218 printf("Write MDIO failed...\n"); 219 return -1; 220 } 221 } 222 223 /* clear MII interrupt bit */ 224 writel(FEC_IEVENT_MII, ð->ievent); 225 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, 226 regaddr, data); 227 228 return 0; 229} 230 231static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr, 232 int regaddr) 233{ 234 return fec_mdio_read(bus->priv, phyaddr, regaddr); 235} 236 237static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr, 238 int regaddr, u16 data) 239{ 240 return fec_mdio_write(bus->priv, phyaddr, regaddr, data); 241} 242 243#ifndef CONFIG_PHYLIB 244static int miiphy_restart_aneg(struct eth_device *dev) 245{ 246 int ret = 0; 247#if !defined(CONFIG_FEC_MXC_NO_ANEG) 248 struct fec_priv *fec = (struct fec_priv *)dev->priv; 249 struct ethernet_regs *eth = fec->bus->priv; 250 251 /* 252 * Wake up from sleep if necessary 253 * Reset PHY, then delay 300ns 254 */ 255 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); 256 udelay(1000); 257 258 /* Set the auto-negotiation advertisement register bits */ 259 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, 260 LPA_100FULL | LPA_100HALF | LPA_10FULL | 261 LPA_10HALF | PHY_ANLPAR_PSB_802_3); 262 fec_mdio_write(eth, fec->phy_id, MII_BMCR, 263 BMCR_ANENABLE | BMCR_ANRESTART); 264 265 if (fec->mii_postcall) 266 ret = fec->mii_postcall(fec->phy_id); 267 268#endif 269 return ret; 270} 271 272static int miiphy_wait_aneg(struct eth_device *dev) 273{ 274 uint32_t start; 275 int status; 276 struct fec_priv *fec = (struct fec_priv *)dev->priv; 277 struct ethernet_regs *eth = fec->bus->priv; 278 279 /* Wait for AN completion */ 280 start = get_timer(0); 281 do { 282 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 283 printf("%s: Autonegotiation timeout\n", dev->name); 284 return -1; 285 } 286 287 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); 288 if (status < 0) { 289 printf("%s: Autonegotiation failed. status: %d\n", 290 dev->name, status); 291 return -1; 292 } 293 } while (!(status & BMSR_LSTATUS)); 294 295 return 0; 296} 297#endif 298 299static int fec_rx_task_enable(struct fec_priv *fec) 300{ 301 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); 302 return 0; 303} 304 305static int fec_rx_task_disable(struct fec_priv *fec) 306{ 307 return 0; 308} 309 310static int fec_tx_task_enable(struct fec_priv *fec) 311{ 312 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); 313 return 0; 314} 315 316static int fec_tx_task_disable(struct fec_priv *fec) 317{ 318 return 0; 319} 320 321/** 322 * Initialize receive task's buffer descriptors 323 * @param[in] fec all we know about the device yet 324 * @param[in] count receive buffer count to be allocated 325 * @param[in] dsize desired size of each receive buffer 326 * Return: 0 on success 327 * 328 * Init all RX descriptors to default values. 329 */ 330static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) 331{ 332 uint32_t size; 333 ulong data; 334 int i; 335 336 /* 337 * Reload the RX descriptors with default values and wipe 338 * the RX buffers. 339 */ 340 size = roundup(dsize, ARCH_DMA_MINALIGN); 341 for (i = 0; i < count; i++) { 342 data = fec->rbd_base[i].data_pointer; 343 memset((void *)data, 0, dsize); 344 flush_dcache_range(data, data + size); 345 346 fec->rbd_base[i].status = FEC_RBD_EMPTY; 347 fec->rbd_base[i].data_length = 0; 348 } 349 350 /* Mark the last RBD to close the ring. */ 351 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; 352 fec->rbd_index = 0; 353 354 flush_dcache_range((ulong)fec->rbd_base, 355 (ulong)fec->rbd_base + size); 356} 357 358/** 359 * Initialize transmit task's buffer descriptors 360 * @param[in] fec all we know about the device yet 361 * 362 * Transmit buffers are created externally. We only have to init the BDs here.\n 363 * Note: There is a race condition in the hardware. When only one BD is in 364 * use it must be marked with the WRAP bit to use it for every transmitt. 365 * This bit in combination with the READY bit results into double transmit 366 * of each data buffer. It seems the state machine checks READY earlier then 367 * resetting it after the first transfer. 368 * Using two BDs solves this issue. 369 */ 370static void fec_tbd_init(struct fec_priv *fec) 371{ 372 ulong addr = (ulong)fec->tbd_base; 373 unsigned size = roundup(2 * sizeof(struct fec_bd), 374 ARCH_DMA_MINALIGN); 375 376 memset(fec->tbd_base, 0, size); 377 fec->tbd_base[0].status = 0; 378 fec->tbd_base[1].status = FEC_TBD_WRAP; 379 fec->tbd_index = 0; 380 flush_dcache_range(addr, addr + size); 381} 382 383/** 384 * Mark the given read buffer descriptor as free 385 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 386 * @param[in] prbd buffer descriptor to mark free again 387 */ 388static void fec_rbd_clean(int last, struct fec_bd *prbd) 389{ 390 unsigned short flags = FEC_RBD_EMPTY; 391 if (last) 392 flags |= FEC_RBD_WRAP; 393 writew(flags, &prbd->status); 394 writew(0, &prbd->data_length); 395} 396 397static int fec_get_hwaddr(int dev_id, unsigned char *mac) 398{ 399 imx_get_mac_from_fuse(dev_id, mac); 400 return !is_valid_ethaddr(mac); 401} 402 403static int fecmxc_set_hwaddr(struct udevice *dev) 404{ 405 struct fec_priv *fec = dev_get_priv(dev); 406 struct eth_pdata *pdata = dev_get_plat(dev); 407 uchar *mac = pdata->enetaddr; 408 409 writel(0, &fec->eth->iaddr1); 410 writel(0, &fec->eth->iaddr2); 411 writel(0, &fec->eth->gaddr1); 412 writel(0, &fec->eth->gaddr2); 413 414 /* Set physical address */ 415 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 416 &fec->eth->paddr1); 417 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 418 419 return 0; 420} 421 422/* Do initial configuration of the FEC registers */ 423static void fec_reg_setup(struct fec_priv *fec) 424{ 425 uint32_t rcntrl; 426 427 /* Set interrupt mask register */ 428 writel(0x00000000, &fec->eth->imask); 429 430 /* Clear FEC-Lite interrupt event register(IEVENT) */ 431 writel(0xffffffff, &fec->eth->ievent); 432 433 /* Set FEC-Lite receive control register(R_CNTRL): */ 434 435 /* Start with frame length = 1518, common for all modes. */ 436 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; 437 if (fec->xcv_type != SEVENWIRE) /* xMII modes */ 438 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; 439 if (fec->xcv_type == RGMII) 440 rcntrl |= FEC_RCNTRL_RGMII; 441 else if (fec->xcv_type == RMII) 442 rcntrl |= FEC_RCNTRL_RMII; 443 444 if (fec->promisc) 445 rcntrl |= 0x8; 446 447 writel(rcntrl, &fec->eth->r_cntrl); 448} 449 450/** 451 * Start the FEC engine 452 * @param[in] dev Our device to handle 453 */ 454static int fec_open(struct udevice *dev) 455{ 456 struct fec_priv *fec = dev_get_priv(dev); 457 int speed; 458 ulong addr, size; 459 int i; 460 461 debug("fec_open: fec_open(dev)\n"); 462 /* full-duplex, heartbeat disabled */ 463 writel(1 << 2, &fec->eth->x_cntrl); 464 fec->rbd_index = 0; 465 466 /* Invalidate all descriptors */ 467 for (i = 0; i < FEC_RBD_NUM - 1; i++) 468 fec_rbd_clean(0, &fec->rbd_base[i]); 469 fec_rbd_clean(1, &fec->rbd_base[i]); 470 471 /* Flush the descriptors into RAM */ 472 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), 473 ARCH_DMA_MINALIGN); 474 addr = (ulong)fec->rbd_base; 475 flush_dcache_range(addr, addr + size); 476 477#ifdef FEC_QUIRK_ENET_MAC 478 /* Enable ENET HW endian SWAP */ 479 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, 480 &fec->eth->ecntrl); 481 /* Enable ENET store and forward mode */ 482 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, 483 &fec->eth->x_wmrk); 484#endif 485 /* Enable FEC-Lite controller */ 486 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, 487 &fec->eth->ecntrl); 488 489#ifdef FEC_ENET_ENABLE_TXC_DELAY 490 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY, 491 &fec->eth->ecntrl); 492#endif 493 494#ifdef FEC_ENET_ENABLE_RXC_DELAY 495 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY, 496 &fec->eth->ecntrl); 497#endif 498 499#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL) 500 udelay(100); 501 502 /* setup the MII gasket for RMII mode */ 503 /* disable the gasket */ 504 writew(0, &fec->eth->miigsk_enr); 505 506 /* wait for the gasket to be disabled */ 507 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) 508 udelay(2); 509 510 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ 511 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); 512 513 /* re-enable the gasket */ 514 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); 515 516 /* wait until MII gasket is ready */ 517 int max_loops = 10; 518 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { 519 if (--max_loops <= 0) { 520 printf("WAIT for MII Gasket ready timed out\n"); 521 break; 522 } 523 } 524#endif 525 526#ifdef CONFIG_PHYLIB 527 { 528 /* Start up the PHY */ 529 int ret = phy_startup(fec->phydev); 530 531 if (ret) { 532 printf("Could not initialize PHY %s\n", 533 fec->phydev->dev->name); 534 return ret; 535 } 536 speed = fec->phydev->speed; 537 } 538#else 539 miiphy_wait_aneg(edev); 540 speed = miiphy_speed(edev->name, fec->phy_id); 541 miiphy_duplex(edev->name, fec->phy_id); 542#endif 543 544#ifdef FEC_QUIRK_ENET_MAC 545 { 546 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; 547 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; 548 if (speed == _1000BASET) 549 ecr |= FEC_ECNTRL_SPEED; 550 else if (speed != _100BASET) 551 rcr |= FEC_RCNTRL_RMII_10T; 552 writel(ecr, &fec->eth->ecntrl); 553 writel(rcr, &fec->eth->r_cntrl); 554 } 555#endif 556 debug("%s:Speed=%i\n", __func__, speed); 557 558 /* Enable SmartDMA receive task */ 559 fec_rx_task_enable(fec); 560 561 udelay(100000); 562 return 0; 563} 564 565static int fecmxc_init(struct udevice *dev) 566{ 567 struct fec_priv *fec = dev_get_priv(dev); 568 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop; 569 u8 *i; 570 ulong addr; 571 572 /* Initialize MAC address */ 573 fecmxc_set_hwaddr(dev); 574 575 /* Setup transmit descriptors, there are two in total. */ 576 fec_tbd_init(fec); 577 578 /* Setup receive descriptors. */ 579 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); 580 581 fec_reg_setup(fec); 582 583 if (fec->xcv_type != SEVENWIRE) 584 fec_mii_setspeed(fec->bus->priv); 585 586 /* Set Opcode/Pause Duration Register */ 587 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 588 writel(0x2, &fec->eth->x_wmrk); 589 590 /* Set multicast address filter */ 591 writel(0x00000000, &fec->eth->gaddr1); 592 writel(0x00000000, &fec->eth->gaddr2); 593 594 /* Do not access reserved register */ 595 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp() && 596 !is_imx93()) { 597 /* clear MIB RAM */ 598 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) 599 writel(0, i); 600 601 /* FIFO receive start register */ 602 writel(0x520, &fec->eth->r_fstart); 603 } 604 605 /* size and address of each buffer */ 606 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 607 608 addr = (ulong)fec->tbd_base; 609 writel((uint32_t)addr, &fec->eth->etdsr); 610 611 addr = (ulong)fec->rbd_base; 612 writel((uint32_t)addr, &fec->eth->erdsr); 613 614#ifndef CONFIG_PHYLIB 615 if (fec->xcv_type != SEVENWIRE) 616 miiphy_restart_aneg(dev); 617#endif 618 fec_open(dev); 619 return 0; 620} 621 622/** 623 * Halt the FEC engine 624 * @param[in] dev Our device to handle 625 */ 626static void fecmxc_halt(struct udevice *dev) 627{ 628 struct fec_priv *fec = dev_get_priv(dev); 629 int counter = 0xffff; 630 631 /* issue graceful stop command to the FEC transmitter if necessary */ 632 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), 633 &fec->eth->x_cntrl); 634 635 debug("eth_halt: wait for stop regs\n"); 636 /* wait for graceful stop to register */ 637 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 638 udelay(1); 639 640 /* Disable SmartDMA tasks */ 641 fec_tx_task_disable(fec); 642 fec_rx_task_disable(fec); 643 644 /* 645 * Disable the Ethernet Controller 646 * Note: this will also reset the BD index counter! 647 */ 648 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 649 &fec->eth->ecntrl); 650 fec->rbd_index = 0; 651 fec->tbd_index = 0; 652 debug("eth_halt: done\n"); 653} 654 655/** 656 * Transmit one frame 657 * @param[in] dev Our ethernet device to handle 658 * @param[in] packet Pointer to the data to be transmitted 659 * @param[in] length Data count in bytes 660 * Return: 0 on success 661 */ 662static int fecmxc_send(struct udevice *dev, void *packet, int length) 663{ 664 unsigned int status; 665 u32 size; 666 ulong addr, end; 667 int timeout = FEC_XFER_TIMEOUT; 668 int ret = 0; 669 670 /* 671 * This routine transmits one frame. This routine only accepts 672 * 6-byte Ethernet addresses. 673 */ 674 struct fec_priv *fec = dev_get_priv(dev); 675 676 /* 677 * Check for valid length of data. 678 */ 679 if ((length > 1500) || (length <= 0)) { 680 printf("Payload (%d) too large\n", length); 681 return -1; 682 } 683 684 /* 685 * Setup the transmit buffer. We are always using the first buffer for 686 * transmission, the second will be empty and only used to stop the DMA 687 * engine. We also flush the packet to RAM here to avoid cache trouble. 688 */ 689#ifdef CFG_FEC_MXC_SWAP_PACKET 690 swap_packet((uint32_t *)packet, length); 691#endif 692 693 addr = (ulong)packet; 694 end = roundup(addr + length, ARCH_DMA_MINALIGN); 695 addr &= ~(ARCH_DMA_MINALIGN - 1); 696 flush_dcache_range(addr, end); 697 698 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 699 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer); 700 701 /* 702 * update BD's status now 703 * This block: 704 * - is always the last in a chain (means no chain) 705 * - should transmitt the CRC 706 * - might be the last BD in the list, so the address counter should 707 * wrap (-> keep the WRAP flag) 708 */ 709 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 710 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 711 writew(status, &fec->tbd_base[fec->tbd_index].status); 712 713 /* 714 * Flush data cache. This code flushes both TX descriptors to RAM. 715 * After this code, the descriptors will be safely in RAM and we 716 * can start DMA. 717 */ 718 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); 719 addr = (ulong)fec->tbd_base; 720 flush_dcache_range(addr, addr + size); 721 722 /* 723 * Below we read the DMA descriptor's last four bytes back from the 724 * DRAM. This is important in order to make sure that all WRITE 725 * operations on the bus that were triggered by previous cache FLUSH 726 * have completed. 727 * 728 * Otherwise, on MX28, it is possible to observe a corruption of the 729 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM 730 * for the bus structure of MX28. The scenario is as follows: 731 * 732 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going 733 * to DRAM due to flush_dcache_range() 734 * 2) ARM core writes the FEC registers via AHB_ARB2 735 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 736 * 737 * Note that 2) does sometimes finish before 1) due to reordering of 738 * WRITE accesses on the AHB bus, therefore triggering 3) before the 739 * DMA descriptor is fully written into DRAM. This results in occasional 740 * corruption of the DMA descriptor. 741 */ 742 readl(addr + size - 4); 743 744 /* Enable SmartDMA transmit task */ 745 fec_tx_task_enable(fec); 746 747 /* 748 * Wait until frame is sent. On each turn of the wait cycle, we must 749 * invalidate data cache to see what's really in RAM. Also, we need 750 * barrier here. 751 */ 752 while (--timeout) { 753 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) 754 break; 755 } 756 757 if (!timeout) { 758 ret = -EINVAL; 759 goto out; 760 } 761 762 /* 763 * The TDAR bit is cleared when the descriptors are all out from TX 764 * but on mx6solox we noticed that the READY bit is still not cleared 765 * right after TDAR. 766 * These are two distinct signals, and in IC simulation, we found that 767 * TDAR always gets cleared prior than the READY bit of last BD becomes 768 * cleared. 769 * In mx6solox, we use a later version of FEC IP. It looks like that 770 * this intrinsic behaviour of TDAR bit has changed in this newer FEC 771 * version. 772 * 773 * Fix this by polling the READY bit of BD after the TDAR polling, 774 * which covers the mx6solox case and does not harm the other SoCs. 775 */ 776 timeout = FEC_XFER_TIMEOUT; 777 while (--timeout) { 778 invalidate_dcache_range(addr, addr + size); 779 if (!(readw(&fec->tbd_base[fec->tbd_index].status) & 780 FEC_TBD_READY)) 781 break; 782 } 783 784 if (!timeout) 785 ret = -EINVAL; 786 787out: 788 debug("fec_send: status 0x%x index %d ret %i\n", 789 readw(&fec->tbd_base[fec->tbd_index].status), 790 fec->tbd_index, ret); 791 /* for next transmission use the other buffer */ 792 if (fec->tbd_index) 793 fec->tbd_index = 0; 794 else 795 fec->tbd_index = 1; 796 797 return ret; 798} 799 800/** 801 * Pull one frame from the card 802 * @param[in] dev Our ethernet device to handle 803 * Return: Length of packet read 804 */ 805static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) 806{ 807 struct fec_priv *fec = dev_get_priv(dev); 808 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 809 unsigned long ievent; 810 int frame_length, len = 0; 811 uint16_t bd_status; 812 ulong addr, size, end; 813 int i; 814 815 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE); 816 if (*packetp == 0) { 817 printf("%s: error allocating packetp\n", __func__); 818 return -ENOMEM; 819 } 820 821 /* Check if any critical events have happened */ 822 ievent = readl(&fec->eth->ievent); 823 writel(ievent, &fec->eth->ievent); 824 debug("fec_recv: ievent 0x%lx\n", ievent); 825 if (ievent & FEC_IEVENT_BABR) { 826 fecmxc_halt(dev); 827 fecmxc_init(dev); 828 printf("some error: 0x%08lx\n", ievent); 829 return 0; 830 } 831 if (ievent & FEC_IEVENT_HBERR) { 832 /* Heartbeat error */ 833 writel(0x00000001 | readl(&fec->eth->x_cntrl), 834 &fec->eth->x_cntrl); 835 } 836 if (ievent & FEC_IEVENT_GRA) { 837 /* Graceful stop complete */ 838 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 839 fecmxc_halt(dev); 840 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 841 &fec->eth->x_cntrl); 842 fecmxc_init(dev); 843 } 844 } 845 846 /* 847 * Read the buffer status. Before the status can be read, the data cache 848 * must be invalidated, because the data in RAM might have been changed 849 * by DMA. The descriptors are properly aligned to cachelines so there's 850 * no need to worry they'd overlap. 851 * 852 * WARNING: By invalidating the descriptor here, we also invalidate 853 * the descriptors surrounding this one. Therefore we can NOT change the 854 * contents of this descriptor nor the surrounding ones. The problem is 855 * that in order to mark the descriptor as processed, we need to change 856 * the descriptor. The solution is to mark the whole cache line when all 857 * descriptors in the cache line are processed. 858 */ 859 addr = (ulong)rbd; 860 addr &= ~(ARCH_DMA_MINALIGN - 1); 861 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); 862 invalidate_dcache_range(addr, addr + size); 863 864 bd_status = readw(&rbd->status); 865 debug("fec_recv: status 0x%x\n", bd_status); 866 867 if (!(bd_status & FEC_RBD_EMPTY)) { 868 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 869 ((readw(&rbd->data_length) - 4) > 14)) { 870 /* Get buffer address and size */ 871 addr = readl(&rbd->data_pointer); 872 frame_length = readw(&rbd->data_length) - 4; 873 /* Invalidate data cache over the buffer */ 874 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); 875 addr &= ~(ARCH_DMA_MINALIGN - 1); 876 invalidate_dcache_range(addr, end); 877 878 /* Fill the buffer and pass it to upper layers */ 879#ifdef CFG_FEC_MXC_SWAP_PACKET 880 swap_packet((uint32_t *)addr, frame_length); 881#endif 882 883 memcpy(*packetp, (char *)addr, frame_length); 884 len = frame_length; 885 } else { 886 if (bd_status & FEC_RBD_ERR) 887 debug("error frame: 0x%08lx 0x%08x\n", 888 addr, bd_status); 889 } 890 891 /* 892 * Free the current buffer, restart the engine and move forward 893 * to the next buffer. Here we check if the whole cacheline of 894 * descriptors was already processed and if so, we mark it free 895 * as whole. 896 */ 897 size = RXDESC_PER_CACHELINE - 1; 898 if ((fec->rbd_index & size) == size) { 899 i = fec->rbd_index - size; 900 addr = (ulong)&fec->rbd_base[i]; 901 for (; i <= fec->rbd_index ; i++) { 902 fec_rbd_clean(i == (FEC_RBD_NUM - 1), 903 &fec->rbd_base[i]); 904 } 905 flush_dcache_range(addr, 906 addr + ARCH_DMA_MINALIGN); 907 } 908 909 fec_rx_task_enable(fec); 910 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 911 } 912 debug("fec_recv: stop\n"); 913 914 return len; 915} 916 917static void fec_set_dev_name(char *dest, int dev_id) 918{ 919 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); 920} 921 922static int fec_alloc_descs(struct fec_priv *fec) 923{ 924 unsigned int size; 925 int i; 926 uint8_t *data; 927 ulong addr; 928 929 /* Allocate TX descriptors. */ 930 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); 931 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); 932 if (!fec->tbd_base) 933 goto err_tx; 934 935 /* Allocate RX descriptors. */ 936 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); 937 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); 938 if (!fec->rbd_base) 939 goto err_rx; 940 941 memset(fec->rbd_base, 0, size); 942 943 /* Allocate RX buffers. */ 944 945 /* Maximum RX buffer size. */ 946 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); 947 for (i = 0; i < FEC_RBD_NUM; i++) { 948 data = memalign(FEC_DMA_RX_MINALIGN, size); 949 if (!data) { 950 printf("%s: error allocating rxbuf %d\n", __func__, i); 951 goto err_ring; 952 } 953 954 memset(data, 0, size); 955 956 addr = (ulong)data; 957 fec->rbd_base[i].data_pointer = (uint32_t)addr; 958 fec->rbd_base[i].status = FEC_RBD_EMPTY; 959 fec->rbd_base[i].data_length = 0; 960 /* Flush the buffer to memory. */ 961 flush_dcache_range(addr, addr + size); 962 } 963 964 /* Mark the last RBD to close the ring. */ 965 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; 966 967 fec->rbd_index = 0; 968 fec->tbd_index = 0; 969 970 return 0; 971 972err_ring: 973 for (; i >= 0; i--) { 974 addr = fec->rbd_base[i].data_pointer; 975 free((void *)addr); 976 } 977 free(fec->rbd_base); 978err_rx: 979 free(fec->tbd_base); 980err_tx: 981 return -ENOMEM; 982} 983 984static void fec_free_descs(struct fec_priv *fec) 985{ 986 int i; 987 ulong addr; 988 989 for (i = 0; i < FEC_RBD_NUM; i++) { 990 addr = fec->rbd_base[i].data_pointer; 991 free((void *)addr); 992 } 993 free(fec->rbd_base); 994 free(fec->tbd_base); 995} 996 997struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) 998{ 999 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; 1000 struct mii_dev *bus; 1001 int ret; 1002 1003 bus = mdio_alloc(); 1004 if (!bus) { 1005 printf("mdio_alloc failed\n"); 1006 return NULL; 1007 } 1008 bus->read = fec_phy_read; 1009 bus->write = fec_phy_write; 1010 bus->priv = eth; 1011 fec_set_dev_name(bus->name, dev_id); 1012 1013 ret = mdio_register(bus); 1014 if (ret) { 1015 printf("mdio_register failed\n"); 1016 free(bus); 1017 return NULL; 1018 } 1019 fec_mii_setspeed(eth); 1020 return bus; 1021} 1022 1023#ifdef CONFIG_DM_MDIO 1024struct dm_fec_mdio_priv { 1025 struct ethernet_regs *regs; 1026}; 1027 1028static int dm_fec_mdio_read(struct udevice *dev, int addr, int devad, int reg) 1029{ 1030 struct dm_fec_mdio_priv *priv = dev_get_priv(dev); 1031 1032 return fec_mdio_read(priv->regs, addr, reg); 1033} 1034 1035static int dm_fec_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 data) 1036{ 1037 struct dm_fec_mdio_priv *priv = dev_get_priv(dev); 1038 1039 return fec_mdio_write(priv->regs, addr, reg, data); 1040} 1041 1042static const struct mdio_ops dm_fec_mdio_ops = { 1043 .read = dm_fec_mdio_read, 1044 .write = dm_fec_mdio_write, 1045}; 1046 1047static int dm_fec_mdio_probe(struct udevice *dev) 1048{ 1049 struct dm_fec_mdio_priv *priv = dev_get_priv(dev); 1050 1051 priv->regs = (struct ethernet_regs *)ofnode_get_addr(dev_ofnode(dev->parent)); 1052 1053 return 0; 1054} 1055 1056U_BOOT_DRIVER(fec_mdio) = { 1057 .name = "fec_mdio", 1058 .id = UCLASS_MDIO, 1059 .probe = dm_fec_mdio_probe, 1060 .ops = &dm_fec_mdio_ops, 1061 .priv_auto = sizeof(struct dm_fec_mdio_priv), 1062}; 1063 1064static int dm_fec_bind_mdio(struct udevice *dev) 1065{ 1066 struct udevice *mdiodev; 1067 const char *name; 1068 ofnode mdio; 1069 int ret = -ENODEV; 1070 1071 /* for a UCLASS_MDIO driver we need to bind and probe manually 1072 * for an internal MDIO bus that has no dt compatible of its own 1073 */ 1074 ofnode_for_each_subnode(mdio, dev_ofnode(dev)) { 1075 name = ofnode_get_name(mdio); 1076 1077 if (strcmp(name, "mdio")) 1078 continue; 1079 1080 ret = device_bind_driver_to_node(dev, "fec_mdio", 1081 name, mdio, &mdiodev); 1082 if (ret) { 1083 printf("%s bind %s failed: %d\n", __func__, name, ret); 1084 break; 1085 } 1086 1087 /* need to probe it as there is no compatible to do so */ 1088 ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdiodev); 1089 if (!ret) 1090 return 0; 1091 printf("%s probe %s failed: %d\n", __func__, name, ret); 1092 } 1093 1094 return ret; 1095} 1096#endif 1097 1098static int fecmxc_read_rom_hwaddr(struct udevice *dev) 1099{ 1100 struct fec_priv *priv = dev_get_priv(dev); 1101 struct eth_pdata *pdata = dev_get_plat(dev); 1102 1103 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr); 1104} 1105 1106static int fecmxc_set_promisc(struct udevice *dev, bool enable) 1107{ 1108 struct fec_priv *priv = dev_get_priv(dev); 1109 1110 priv->promisc = enable; 1111 1112 return 0; 1113} 1114 1115static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length) 1116{ 1117 if (packet) 1118 free(packet); 1119 1120 return 0; 1121} 1122 1123static const struct eth_ops fecmxc_ops = { 1124 .start = fecmxc_init, 1125 .send = fecmxc_send, 1126 .recv = fecmxc_recv, 1127 .free_pkt = fecmxc_free_pkt, 1128 .stop = fecmxc_halt, 1129 .write_hwaddr = fecmxc_set_hwaddr, 1130 .read_rom_hwaddr = fecmxc_read_rom_hwaddr, 1131 .set_promisc = fecmxc_set_promisc, 1132}; 1133 1134static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev) 1135{ 1136 struct ofnode_phandle_args phandle_args; 1137 int reg, ret; 1138 1139 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, 1140 &phandle_args); 1141 if (ret) { 1142 priv->phy_of_node = ofnode_find_subnode(dev_ofnode(dev), 1143 "fixed-link"); 1144 if (ofnode_valid(priv->phy_of_node)) 1145 return 0; 1146 debug("Failed to find phy-handle (err = %d)\n", ret); 1147 return ret; 1148 } 1149 1150 if (!ofnode_is_enabled(phandle_args.node)) 1151 return -ENOENT; 1152 1153 priv->phy_of_node = phandle_args.node; 1154 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); 1155 1156 return reg; 1157} 1158 1159static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) 1160{ 1161 struct phy_device *phydev = NULL; 1162 int addr; 1163 1164 addr = device_get_phy_addr(priv, dev); 1165#ifdef CFG_FEC_MXC_PHYADDR 1166 addr = CFG_FEC_MXC_PHYADDR; 1167#endif 1168 1169 if (IS_ENABLED(CONFIG_DM_MDIO)) 1170 phydev = dm_eth_phy_connect(dev); 1171 if (!phydev) 1172 phydev = phy_connect(priv->bus, addr, dev, priv->interface); 1173 if (!phydev) 1174 return -ENODEV; 1175 1176 priv->phydev = phydev; 1177 priv->phydev->node = priv->phy_of_node; 1178 phy_config(phydev); 1179 1180 return 0; 1181} 1182 1183#if CONFIG_IS_ENABLED(DM_GPIO) 1184/* FEC GPIO reset */ 1185static void fec_gpio_reset(struct fec_priv *priv) 1186{ 1187 debug("fec_gpio_reset: fec_gpio_reset(dev)\n"); 1188 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) { 1189 dm_gpio_set_value(&priv->phy_reset_gpio, 1); 1190 mdelay(priv->reset_delay); 1191 dm_gpio_set_value(&priv->phy_reset_gpio, 0); 1192 if (priv->reset_post_delay) 1193 mdelay(priv->reset_post_delay); 1194 } 1195} 1196#endif 1197 1198static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface) 1199{ 1200 unsigned int freq; 1201 int ret; 1202 1203 if (!CONFIG_IS_ENABLED(CLK_CCF)) 1204 return 0; 1205 1206 if (interface == PHY_INTERFACE_MODE_MII) 1207 freq = 25000000; 1208 else if (interface == PHY_INTERFACE_MODE_RMII) 1209 freq = 50000000; 1210 else if (interface == PHY_INTERFACE_MODE_RGMII || 1211 interface == PHY_INTERFACE_MODE_RGMII_ID || 1212 interface == PHY_INTERFACE_MODE_RGMII_RXID || 1213 interface == PHY_INTERFACE_MODE_RGMII_TXID) 1214 freq = 125000000; 1215 else 1216 return -EINVAL; 1217 1218 ret = clk_set_rate(clk_ref, freq); 1219 if (ret < 0) 1220 return ret; 1221 1222 return 0; 1223} 1224 1225static int fecmxc_probe(struct udevice *dev) 1226{ 1227 bool dm_mii_bus = true; 1228 struct eth_pdata *pdata = dev_get_plat(dev); 1229 struct fec_priv *priv = dev_get_priv(dev); 1230 struct mii_dev *bus = NULL; 1231 uint32_t start; 1232 int ret; 1233 1234 ret = board_interface_eth_init(dev, pdata->phy_interface); 1235 if (ret) 1236 return ret; 1237 1238 if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) { 1239 if (enet_fused((ulong)priv->eth)) { 1240 printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth); 1241 return -ENODEV; 1242 } 1243 } 1244 1245 if (IS_ENABLED(CONFIG_IMX8)) { 1246 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); 1247 if (ret < 0) { 1248 debug("Can't get FEC ipg clk: %d\n", ret); 1249 return ret; 1250 } 1251 ret = clk_enable(&priv->ipg_clk); 1252 if (ret < 0) { 1253 debug("Can't enable FEC ipg clk: %d\n", ret); 1254 return ret; 1255 } 1256 1257 priv->clk_rate = clk_get_rate(&priv->ipg_clk); 1258 } else if (CONFIG_IS_ENABLED(CLK_CCF)) { 1259 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); 1260 if (ret < 0) { 1261 debug("Can't get FEC ipg clk: %d\n", ret); 1262 return ret; 1263 } 1264 ret = clk_enable(&priv->ipg_clk); 1265 if(ret) 1266 return ret; 1267 1268 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk); 1269 if (ret < 0) { 1270 debug("Can't get FEC ahb clk: %d\n", ret); 1271 return ret; 1272 } 1273 ret = clk_enable(&priv->ahb_clk); 1274 if (ret) 1275 return ret; 1276 1277 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out); 1278 if (!ret) { 1279 ret = clk_enable(&priv->clk_enet_out); 1280 if (ret) 1281 return ret; 1282 } 1283 1284 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref); 1285 if (!ret) { 1286 ret = fecmxc_set_ref_clk(&priv->clk_ref, 1287 pdata->phy_interface); 1288 if (ret) 1289 return ret; 1290 1291 ret = clk_enable(&priv->clk_ref); 1292 if (ret) 1293 return ret; 1294 } 1295 1296 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp); 1297 if (!ret) { 1298 ret = clk_enable(&priv->clk_ptp); 1299 if (ret) 1300 return ret; 1301 } 1302 1303 priv->clk_rate = clk_get_rate(&priv->ipg_clk); 1304 } 1305 1306 ret = fec_alloc_descs(priv); 1307 if (ret) 1308 return ret; 1309 1310#ifdef CONFIG_DM_REGULATOR 1311 if (priv->phy_supply) { 1312 ret = regulator_set_enable_if_allowed(priv->phy_supply, true); 1313 if (ret) { 1314 printf("%s: Error enabling phy supply\n", dev->name); 1315 return ret; 1316 } 1317 } 1318#endif 1319 1320#if CONFIG_IS_ENABLED(DM_GPIO) 1321 fec_gpio_reset(priv); 1322#endif 1323 /* Reset chip. */ 1324 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, 1325 &priv->eth->ecntrl); 1326 start = get_timer(0); 1327 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { 1328 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 1329 printf("FEC MXC: Timeout resetting chip\n"); 1330 goto err_timeout; 1331 } 1332 udelay(10); 1333 } 1334 1335 fec_reg_setup(priv); 1336 1337 priv->dev_id = dev_seq(dev); 1338 1339#ifdef CONFIG_DM_MDIO 1340 ret = dm_fec_bind_mdio(dev); 1341 if (ret && ret != -ENODEV) 1342 return ret; 1343#endif 1344 1345#ifdef CONFIG_DM_ETH_PHY 1346 bus = eth_phy_get_mdio_bus(dev); 1347#endif 1348 1349 if (!bus) { 1350 dm_mii_bus = false; 1351#ifdef CONFIG_FEC_MXC_MDIO_BASE 1352 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, 1353 dev_seq(dev)); 1354#else 1355 bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev)); 1356#endif 1357 } 1358 if (!bus) { 1359 ret = -ENOMEM; 1360 goto err_mii; 1361 } 1362 1363#ifdef CONFIG_DM_ETH_PHY 1364 eth_phy_set_mdio_bus(dev, bus); 1365#endif 1366 1367 priv->bus = bus; 1368 priv->interface = pdata->phy_interface; 1369 switch (priv->interface) { 1370 case PHY_INTERFACE_MODE_MII: 1371 priv->xcv_type = MII100; 1372 break; 1373 case PHY_INTERFACE_MODE_RMII: 1374 priv->xcv_type = RMII; 1375 break; 1376 case PHY_INTERFACE_MODE_RGMII: 1377 case PHY_INTERFACE_MODE_RGMII_ID: 1378 case PHY_INTERFACE_MODE_RGMII_RXID: 1379 case PHY_INTERFACE_MODE_RGMII_TXID: 1380 priv->xcv_type = RGMII; 1381 break; 1382 default: 1383 priv->xcv_type = MII100; 1384 printf("Unsupported interface type %d defaulting to MII100\n", 1385 priv->interface); 1386 break; 1387 } 1388 1389 ret = fec_phy_init(priv, dev); 1390 if (ret) 1391 goto err_phy; 1392 1393 return 0; 1394 1395err_phy: 1396 if (!dm_mii_bus) { 1397 mdio_unregister(bus); 1398 free(bus); 1399 } 1400err_mii: 1401err_timeout: 1402 fec_free_descs(priv); 1403 return ret; 1404} 1405 1406static int fecmxc_remove(struct udevice *dev) 1407{ 1408 struct fec_priv *priv = dev_get_priv(dev); 1409 1410 free(priv->phydev); 1411 fec_free_descs(priv); 1412 mdio_unregister(priv->bus); 1413 mdio_free(priv->bus); 1414 1415#ifdef CONFIG_DM_REGULATOR 1416 if (priv->phy_supply) 1417 regulator_set_enable(priv->phy_supply, false); 1418#endif 1419 1420 return 0; 1421} 1422 1423static int fecmxc_of_to_plat(struct udevice *dev) 1424{ 1425 int ret = 0; 1426 struct eth_pdata *pdata = dev_get_plat(dev); 1427 struct fec_priv *priv = dev_get_priv(dev); 1428 1429 pdata->iobase = dev_read_addr(dev); 1430 priv->eth = (struct ethernet_regs *)pdata->iobase; 1431 1432 pdata->phy_interface = dev_read_phy_mode(dev); 1433 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) 1434 return -EINVAL; 1435 1436#ifdef CONFIG_DM_REGULATOR 1437 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply); 1438#endif 1439 1440#if CONFIG_IS_ENABLED(DM_GPIO) 1441 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, 1442 &priv->phy_reset_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 1443 if (ret < 0) 1444 return 0; /* property is optional, don't return error! */ 1445 1446 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1); 1447 if (priv->reset_delay > 1000) { 1448 printf("FEC MXC: phy reset duration should be <= 1000ms\n"); 1449 /* property value wrong, use default value */ 1450 priv->reset_delay = 1; 1451 } 1452 1453 priv->reset_post_delay = dev_read_u32_default(dev, 1454 "phy-reset-post-delay", 1455 0); 1456 if (priv->reset_post_delay > 1000) { 1457 printf("FEC MXC: phy reset post delay should be <= 1000ms\n"); 1458 /* property value wrong, use default value */ 1459 priv->reset_post_delay = 0; 1460 } 1461#endif 1462 1463 return 0; 1464} 1465 1466static const struct udevice_id fecmxc_ids[] = { 1467 { .compatible = "fsl,imx28-fec" }, 1468 { .compatible = "fsl,imx6q-fec" }, 1469 { .compatible = "fsl,imx6sl-fec" }, 1470 { .compatible = "fsl,imx6sx-fec" }, 1471 { .compatible = "fsl,imx6ul-fec" }, 1472 { .compatible = "fsl,imx53-fec" }, 1473 { .compatible = "fsl,imx7d-fec" }, 1474 { .compatible = "fsl,mvf600-fec" }, 1475 { .compatible = "fsl,imx93-fec" }, 1476 { } 1477}; 1478 1479U_BOOT_DRIVER(fecmxc_gem) = { 1480 .name = "fecmxc", 1481 .id = UCLASS_ETH, 1482 .of_match = fecmxc_ids, 1483 .of_to_plat = fecmxc_of_to_plat, 1484 .probe = fecmxc_probe, 1485 .remove = fecmxc_remove, 1486 .ops = &fecmxc_ops, 1487 .priv_auto = sizeof(struct fec_priv), 1488 .plat_auto = sizeof(struct eth_pdata), 1489}; 1490