1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2014-2018 Renesas Electronics Europe Limited 4 * 5 * Phil Edworthy <phil.edworthy@renesas.com> 6 * Based on a driver originally written by Michel Pollet at Renesas. 7 */ 8 9#include <dt-bindings/pinctrl/rzn1-pinctrl.h> 10 11#include <dm/device.h> 12#include <dm/device_compat.h> 13#include <dm/pinctrl.h> 14#include <dm/read.h> 15#include <regmap.h> 16 17/* Field positions and masks in the pinmux registers */ 18#define RZN1_L1_PIN_DRIVE_STRENGTH 10 19#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0 20#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1 21#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2 22#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3 23#define RZN1_L1_PIN_PULL 8 24#define RZN1_L1_PIN_PULL_NONE 0 25#define RZN1_L1_PIN_PULL_UP 1 26#define RZN1_L1_PIN_PULL_DOWN 3 27#define RZN1_L1_FUNCTION 0 28#define RZN1_L1_FUNC_MASK 0xf 29#define RZN1_L1_FUNCTION_L2 0xf 30 31/* 32 * The hardware manual describes two levels of multiplexing, but it's more 33 * logical to think of the hardware as three levels, with level 3 consisting of 34 * the multiplexing for Ethernet MDIO signals. 35 * 36 * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying 37 * that level 2 functions are used instead. Level 2 has a lot more options, 38 * going from 0 to 61. Level 3 allows selection of MDIO functions which can be 39 * floating, or one of seven internal peripherals. Unfortunately, there are two 40 * level 2 functions that can select MDIO, and two MDIO channels so we have four 41 * sets of level 3 functions. 42 * 43 * For this driver, we've compounded the numbers together, so: 44 * 0 to 9 is level 1 45 * 10 to 71 is 10 + level 2 number 46 * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function. 47 * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function. 48 * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function. 49 * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function. 50 * Examples: 51 * Function 28 corresponds UART0 52 * Function 73 corresponds to MDIO0 to GMAC0 53 * 54 * There are 170 configurable pins (called PL_GPIO in the datasheet). 55 */ 56 57/* 58 * Structure detailing the HW registers on the RZ/N1 devices. 59 * Both the Level 1 mux registers and Level 2 mux registers have the same 60 * structure. The only difference is that Level 2 has additional MDIO registers 61 * at the end. 62 */ 63struct rzn1_pinctrl_regs { 64 u32 conf[170]; 65 u32 pad0[86]; 66 u32 status_protect; /* 0x400 */ 67 /* MDIO mux registers, level2 only */ 68 u32 l2_mdio[2]; 69}; 70 71#define NUM_CONF ARRAY_SIZE(((struct rzn1_pinctrl_regs *)0)->conf) 72 73#define level1_write(map, member, val) \ 74 regmap_range_set(map, 0, struct rzn1_pinctrl_regs, member, val) 75 76#define level1_read(map, member, valp) \ 77 regmap_range_get(map, 0, struct rzn1_pinctrl_regs, member, valp) 78 79#define level2_write(map, member, val) \ 80 regmap_range_set(map, 1, struct rzn1_pinctrl_regs, member, val) 81 82#define level2_read(map, member, valp) \ 83 regmap_range_get(map, 1, struct rzn1_pinctrl_regs, member, valp) 84 85/** 86 * struct rzn1_pmx_func - describes rzn1 pinmux functions 87 * @name: the name of this specific function 88 * @groups: corresponding pin groups 89 * @num_groups: the number of groups 90 */ 91struct rzn1_pmx_func { 92 const char *name; 93 const char **groups; 94 unsigned int num_groups; 95}; 96 97/** 98 * struct rzn1_pin_group - describes an rzn1 pin group 99 * @name: the name of this specific pin group 100 * @func: the name of the function selected by this group 101 * @npins: the number of pins in this group array, i.e. the number of 102 * elements in .pins so we can iterate over that array 103 * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins() 104 * @pin_ids: array of pin_ids, i.e. the value used to select the mux 105 */ 106struct rzn1_pin_group { 107 const char *name; 108 const char *func; 109 unsigned int npins; 110 unsigned int *pins; 111 u8 *pin_ids; 112}; 113 114struct rzn1_pinctrl { 115 struct device *dev; 116 struct clk *clk; 117 struct pinctrl_dev *pctl; 118 u32 lev1_protect_phys; 119 u32 lev2_protect_phys; 120 int mdio_func[2]; 121 122 struct rzn1_pin_group *groups; 123 unsigned int ngroups; 124 125 struct rzn1_pmx_func *functions; 126 unsigned int nfunctions; 127}; 128 129struct rzn1_pinctrl_priv { 130 struct regmap *regmap; 131 u32 lev1_protect_phys; 132 u32 lev2_protect_phys; 133 134 struct clk *clk; 135}; 136 137enum { 138 LOCK_LEVEL1 = 0x1, 139 LOCK_LEVEL2 = 0x2, 140 LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2, 141}; 142 143static void rzn1_hw_set_lock(struct rzn1_pinctrl_priv *priv, u8 lock, u8 value) 144{ 145 /* 146 * The pinmux configuration is locked by writing the physical address of 147 * the status_protect register to itself. It is unlocked by writing the 148 * address | 1. 149 */ 150 if (lock & LOCK_LEVEL1) { 151 u32 val = priv->lev1_protect_phys | !(value & LOCK_LEVEL1); 152 153 level1_write(priv->regmap, status_protect, val); 154 } 155 156 if (lock & LOCK_LEVEL2) { 157 u32 val = priv->lev2_protect_phys | !(value & LOCK_LEVEL2); 158 159 level2_write(priv->regmap, status_protect, val); 160 } 161} 162 163static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl_priv *priv, int mdio, 164 u32 func) 165{ 166 debug("setting mdio%d to %u\n", mdio, func); 167 168 level2_write(priv->regmap, l2_mdio[mdio], func); 169} 170 171/* 172 * Using a composite pin description, set the hardware pinmux registers 173 * with the corresponding values. 174 * Make sure to unlock write protection and reset it afterward. 175 * 176 * NOTE: There is no protection for potential concurrency, it is assumed these 177 * calls are serialized already. 178 */ 179static int rzn1_set_hw_pin_func(struct rzn1_pinctrl_priv *priv, 180 unsigned int pin, unsigned int func) 181{ 182 u32 l1_cache; 183 u32 l2_cache; 184 u32 l1; 185 u32 l2; 186 187 /* Level 3 MDIO multiplexing */ 188 if (func >= RZN1_FUNC_MDIO0_HIGHZ && 189 func <= RZN1_FUNC_MDIO1_E1_SWITCH) { 190 int mdio_channel; 191 u32 mdio_func; 192 193 if (func <= RZN1_FUNC_MDIO1_HIGHZ) 194 mdio_channel = 0; 195 else 196 mdio_channel = 1; 197 198 /* Get MDIO func, and convert the func to the level 2 number */ 199 if (func <= RZN1_FUNC_MDIO0_SWITCH) { 200 mdio_func = func - RZN1_FUNC_MDIO0_HIGHZ; 201 func = RZN1_FUNC_ETH_MDIO; 202 } else if (func <= RZN1_FUNC_MDIO0_E1_SWITCH) { 203 mdio_func = func - RZN1_FUNC_MDIO0_E1_HIGHZ; 204 func = RZN1_FUNC_ETH_MDIO_E1; 205 } else if (func <= RZN1_FUNC_MDIO1_SWITCH) { 206 mdio_func = func - RZN1_FUNC_MDIO1_HIGHZ; 207 func = RZN1_FUNC_ETH_MDIO; 208 } else { 209 mdio_func = func - RZN1_FUNC_MDIO1_E1_HIGHZ; 210 func = RZN1_FUNC_ETH_MDIO_E1; 211 } 212 rzn1_pinctrl_mdio_select(priv, mdio_channel, mdio_func); 213 } 214 215 /* Note here, we do not allow anything past the MDIO Mux values */ 216 if (pin >= NUM_CONF || func >= RZN1_FUNC_MDIO0_HIGHZ) 217 return -EINVAL; 218 219 level1_read(priv->regmap, conf[pin], &l1); 220 l1_cache = l1; 221 level2_read(priv->regmap, conf[pin], &l2); 222 l2_cache = l2; 223 224 debug("setting func for pin %u to %u\n", pin, func); 225 226 l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION); 227 228 if (func < RZN1_FUNC_L2_OFFSET) { 229 l1 |= (func << RZN1_L1_FUNCTION); 230 } else { 231 l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION); 232 233 l2 = func - RZN1_FUNC_L2_OFFSET; 234 } 235 236 /* If either configuration changes, we update both anyway */ 237 if (l1 != l1_cache || l2 != l2_cache) { 238 level1_write(priv->regmap, conf[pin], l1); 239 level2_write(priv->regmap, conf[pin], l2); 240 } 241 242 return 0; 243} 244 245static int rzn1_pinconf_set(struct rzn1_pinctrl_priv *priv, unsigned int pin, 246 unsigned int bias, unsigned int strength) 247{ 248 u32 l1, l1_cache; 249 u32 drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA; 250 251 level1_read(priv->regmap, conf[pin], &l1); 252 l1_cache = l1; 253 254 switch (bias) { 255 case PIN_CONFIG_BIAS_PULL_UP: 256 debug("set pin %d pull up\n", pin); 257 l1 &= ~(0x3 << RZN1_L1_PIN_PULL); 258 l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL); 259 break; 260 case PIN_CONFIG_BIAS_PULL_DOWN: 261 debug("set pin %d pull down\n", pin); 262 l1 &= ~(0x3 << RZN1_L1_PIN_PULL); 263 l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL); 264 break; 265 case PIN_CONFIG_BIAS_DISABLE: 266 debug("set pin %d bias off\n", pin); 267 l1 &= ~(0x3 << RZN1_L1_PIN_PULL); 268 l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL); 269 break; 270 } 271 272 switch (strength) { 273 case 4: 274 drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA; 275 break; 276 case 6: 277 drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA; 278 break; 279 case 8: 280 drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA; 281 break; 282 case 12: 283 drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA; 284 break; 285 } 286 287 debug("set pin %d drv %umA\n", pin, drv); 288 289 l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH); 290 l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH); 291 292 if (l1 != l1_cache) 293 level1_write(priv->regmap, conf[pin], l1); 294 295 return 0; 296} 297 298static int rzn1_pinctrl_set_state(struct udevice *dev, struct udevice *config) 299{ 300 struct rzn1_pinctrl_priv *priv = dev_get_priv(dev); 301 int size; 302 int ret; 303 u32 val; 304 u32 bias; 305 306 /* Pullup/down bias, common to all pins in group */ 307 bias = PIN_CONFIG_BIAS_PULL_UP; 308 if (dev_read_bool(config, "bias-disable")) 309 bias = PIN_CONFIG_BIAS_DISABLE; 310 else if (dev_read_bool(config, "bias-pull-up")) 311 bias = PIN_CONFIG_BIAS_PULL_UP; 312 else if (dev_read_bool(config, "bias-pull-down")) 313 bias = PIN_CONFIG_BIAS_PULL_DOWN; 314 315 /* Drive strength, common to all pins in group */ 316 u32 strength = dev_read_u32_default(config, "drive-strength", 8); 317 318 /* Number of pins */ 319 ret = dev_read_size(config, "pinmux"); 320 if (ret < 0) 321 return ret; 322 323 size = ret / sizeof(val); 324 325 for (int i = 0; i < size; i++) { 326 ret = dev_read_u32_index(config, "pinmux", i, &val); 327 if (ret) 328 return ret; 329 unsigned int pin = val & 0xff; 330 unsigned int func = val >> 8; 331 332 debug("%s pin %d func %d bias %d strength %d\n", 333 config->name, pin, func, bias, strength); 334 335 rzn1_hw_set_lock(priv, LOCK_ALL, LOCK_ALL); 336 rzn1_set_hw_pin_func(priv, pin, func); 337 rzn1_pinconf_set(priv, pin, bias, strength); 338 rzn1_hw_set_lock(priv, LOCK_ALL, 0); 339 } 340 341 return 0; 342} 343 344static struct pinctrl_ops rzn1_pinctrl_ops = { 345 .set_state = rzn1_pinctrl_set_state, 346}; 347 348static int rzn1_pinctrl_probe(struct udevice *dev) 349{ 350 struct rzn1_pinctrl_priv *priv = dev_get_priv(dev); 351 ofnode node = dev_ofnode(dev); 352 int ret; 353 354 ret = regmap_init_mem(node, &priv->regmap); 355 if (ret) 356 return ret; 357 358 priv->lev1_protect_phys = (u32)regmap_get_range(priv->regmap, 0) + 359 offsetof(struct rzn1_pinctrl_regs, status_protect); 360 priv->lev2_protect_phys = (u32)regmap_get_range(priv->regmap, 1) + 361 offsetof(struct rzn1_pinctrl_regs, status_protect); 362 363 return 0; 364} 365 366static const struct udevice_id rzn1_pinctrl_ids[] = { 367 { .compatible = "renesas,rzn1-pinctrl", }, 368 { }, 369}; 370 371U_BOOT_DRIVER(pinctrl_rzn1) = { 372 .name = "rzn1-pinctrl", 373 .id = UCLASS_PINCTRL, 374 .of_match = rzn1_pinctrl_ids, 375 .priv_auto = sizeof(struct rzn1_pinctrl_priv), 376 .ops = &rzn1_pinctrl_ops, 377 .probe = rzn1_pinctrl_probe, 378 .flags = DM_FLAG_PRE_RELOC, 379}; 380