#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
8c4c6a26 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: support all pin functions Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
1dd073b3 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
c88f0b12 |
|
22-Apr-2024 |
Robert Marko <robert.marko@sartura.hr> |
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
493f0690 |
|
11-Mar-2024 |
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> |
pinctrl: qcom: pass pin number to get_function_mux callback This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
a245aece |
|
26-Feb-2024 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
2c2cc3e9 |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: make compatible with linux DTs The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
#
24d2908e |
|
13-Nov-2023 |
Caleb Connolly <caleb.connolly@linaro.org> |
pinctrl: qcom: move ipq4019 driver from mach-ipq40xx Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|