Searched refs:intr (Results 1 - 25 of 30) sorted by relevance

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/u-boot/drivers/ram/k3-ddrss/
H A Dlpddr4_am6x_sanity.h19 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
20 static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
21 static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
22 static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
29 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus) argument
38 (intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) &&
39 (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) &&
40 (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) &&
41 (intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) &&
42 (intr !
97 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr) argument
163 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus) argument
209 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr) argument
[all...]
H A Dlpddr4_j721e_sanity.h16 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
17 static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
18 static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
19 static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
26 static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus) argument
35 (intr != LPDDR4_INTR_RESET_DONE) &&
36 (intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
37 (intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
38 (intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
39 (intr !
88 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr) argument
148 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus) argument
183 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr) argument
[all...]
H A Dlpddr4_am6x.c70 static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
71 static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
72 static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
73 static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
74 static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
75 static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
125 static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, argument
128 if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE))
130 else if ((intr >
140 lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag) argument
151 lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag) argument
168 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus) argument
197 lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr) argument
215 lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr) argument
232 lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr) argument
247 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr) argument
[all...]
H A Dlpddr4_obj_if.h45 u32 (*checkctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
47 u32 (*ackctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
53 u32 (*checkphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
55 u32 (*ackphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
H A Dlpddr4_j721e.c74 u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus) argument
80 result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
84 if ((u32)intr >= (u32)WORD_SHIFT) {
86 fieldshift = (u32)intr - ((u32)WORD_SHIFT);
89 fieldshift = (u32)intr;
102 u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr) argument
106 u32 localinterrupt = (u32)intr;
108 result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
H A Dlpddr4_if.h108 u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
110 u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
116 u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
118 u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
H A Dlpddr4.c473 u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus) argument
478 result = LPDDR4_INTR_CheckPhyIndepIntSF(pd, intr, irqstatus);
479 if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) {
483 *irqstatus = (bool)(((phyindepirqstatus >> (u32)intr) & LPDDR4_BIT_MASK) > 0U);
488 u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr) argument
493 result = LPDDR4_INTR_AckPhyIndepIntSF(pd, intr);
494 if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) {
497 regval = ((u32)LPDDR4_BIT_MASK << (u32)intr);
/u-boot/tools/
H A Djtagconsole34 trap "stty icanon echo opost intr ^C" 0 2 3 5 10 13 15
37 stty -icanon -echo -opost intr ^T
H A Dnetconsole41 trap "stty icanon echo intr ^C" 0 2 3 5 10 13 15
44 stty -icanon -echo intr ^T
/u-boot/drivers/net/
H A De1000_spi.c21 * This may be interrupted with Ctrl-C if "intr" is true, otherwise it will
25 const void *dout_mem, void *din_mem, bool intr)
40 if (intr && ctrlc())
172 static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, bool intr) argument
176 return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
184 bool intr)
188 return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
192 u8 status, bool intr)
196 return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
199 static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr) argument
24 e1000_spi_xfer(struct e1000_hw *hw, unsigned int bitlen, const void *dout_mem, void *din_mem, bool intr) argument
183 e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr) argument
191 e1000_spi_eeprom_write_status(struct e1000_hw *hw, u8 status, bool intr) argument
208 e1000_spi_eeprom_write_page(struct e1000_hw *hw, const void *data, u16 off, u16 len, bool intr) argument
226 e1000_spi_eeprom_read_page(struct e1000_hw *hw, void *data, u16 off, u16 len, bool intr) argument
244 e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, bool intr) argument
254 e1000_spi_eeprom_dump(struct e1000_hw *hw, void *data, u16 off, unsigned int len, bool intr) argument
283 e1000_spi_eeprom_program(struct e1000_hw *hw, const void *data, u16 off, u16 len, bool intr) argument
[all...]
/u-boot/drivers/pci/
H A Dpci_gt64120.c52 u32 intr; local
100 intr = readl(&gt->regs->intrcause);
101 if (intr & GT_INTRCAUSE_ABORT_BITS) {
/u-boot/drivers/bios_emulator/x86emu/
H A Ddecode.c53 if (M.x86.intr & INTR_SYNCH) {
65 M.x86.intr = 0;
82 M.x86.intr |= INTR_SYNCH;
95 M.x86.intr = 0;
104 if (M.x86.intr) {
105 if (M.x86.intr & INTR_HALTED) {
116 if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) ||
136 M.x86.intr |= INTR_HALTED;
H A Dsys.c329 M.x86.intr = 0;
/u-boot/drivers/ram/
H A Dimxrt_sdram.c51 u32 intr; member in struct:imxrt_semc_regs
196 readl(&regs->intr);
198 if (regs->intr & SEMC_INTR_IPCMDDONE)
200 if (regs->intr & SEMC_INTR_IPCMDERR)
/u-boot/drivers/rng/
H A Djh7110_rng.c166 u32 mode, intr = 0; local
175 intr |= STARFIVE_IE_ALL;
176 writel(intr, trng->base + STARFIVE_IE);
/u-boot/drivers/usb/musb/
H A Dmusb_udc.c161 /* Read intr to clear */
706 static void musb_peri_rx(u16 intr) argument
713 if ((1 << ep) & intr)
718 static void musb_peri_tx(u16 intr) argument
723 if (0x01 & intr)
727 if ((1 << ep) & intr)
/u-boot/arch/m68k/include/asm/coldfire/
H A Dedma.h33 u16 intr; /* 0x26 Interrupt Request */ member in struct:edma_ctrl
/u-boot/drivers/spi/
H A Dmxc_spi.c33 u32 intr; member in struct:cspi_regs
64 u32 intr; member in struct:cspi_regs
296 reg_write(&regs->intr, 0);
472 reg_write(&regs->intr, 0);
/u-boot/drivers/i2c/
H A Di2c-uniphier-f.c34 u32 intr; /* interrupt status */ member in struct:uniphier_fi2c_regs
123 ret = readl_poll_timeout(&priv->regs->intr, irq, irq & flags,
/u-boot/drivers/bios_emulator/include/x86emu/
H A Dregs.h284 volatile int intr; /* mask of pending interrupts */ member in struct:__anon51
/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-npei-defs.h2164 u64 intr : 64; member in struct:cvmx_npei_msi_rcv0::cvmx_npei_msi_rcv0_s
2184 u64 intr : 64; member in struct:cvmx_npei_msi_rcv1::cvmx_npei_msi_rcv1_s
2204 u64 intr : 64; member in struct:cvmx_npei_msi_rcv2::cvmx_npei_msi_rcv2_s
2224 u64 intr : 64; member in struct:cvmx_npei_msi_rcv3::cvmx_npei_msi_rcv3_s
2463 u64 intr : 8; member in struct:cvmx_npei_pcie_msi_rcv::cvmx_npei_pcie_msi_rcv_s
2484 u64 intr : 8; member in struct:cvmx_npei_pcie_msi_rcv_b1::cvmx_npei_pcie_msi_rcv_b1_s
2506 u64 intr : 8; member in struct:cvmx_npei_pcie_msi_rcv_b2::cvmx_npei_pcie_msi_rcv_b2_s
2528 u64 intr : 8; member in struct:cvmx_npei_pcie_msi_rcv_b3::cvmx_npei_pcie_msi_rcv_b3_s
H A Dcvmx-sli-defs.h3495 u64 intr : 64; member in struct:cvmx_sli_msi_rcv0::cvmx_sli_msi_rcv0_s
3523 u64 intr : 64; member in struct:cvmx_sli_msi_rcv1::cvmx_sli_msi_rcv1_s
3551 u64 intr : 64; member in struct:cvmx_sli_msi_rcv2::cvmx_sli_msi_rcv2_s
3579 u64 intr : 64; member in struct:cvmx_sli_msi_rcv3::cvmx_sli_msi_rcv3_s
4049 u64 intr : 8; member in struct:cvmx_sli_pcie_msi_rcv::cvmx_sli_pcie_msi_rcv_s
4078 u64 intr : 8; member in struct:cvmx_sli_pcie_msi_rcv_b1::cvmx_sli_pcie_msi_rcv_b1_s
4108 u64 intr : 8; member in struct:cvmx_sli_pcie_msi_rcv_b2::cvmx_sli_pcie_msi_rcv_b2_s
4138 u64 intr : 8; member in struct:cvmx_sli_pcie_msi_rcv_b3::cvmx_sli_pcie_msi_rcv_b3_s
/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/
H A Dcsrs-npa.h2044 u64 intr : 1; member in struct:npa_lf_qintx_ena_w1c::npa_lf_qintx_ena_w1c_s
2066 u64 intr : 1; member in struct:npa_lf_qintx_ena_w1s::npa_lf_qintx_ena_w1s_s
2087 u64 intr : 1; member in struct:npa_lf_qintx_int::npa_lf_qintx_int_s
2108 u64 intr : 1; member in struct:npa_lf_qintx_int_w1s::npa_lf_qintx_int_w1s_s
/u-boot/arch/m68k/include/asm/
H A Dimmap_5329.h338 u32 intr; /* 0x148 USB Interrupt Enable */ member in struct:usb_otg
/u-boot/arch/mips/mach-octeon/
H A Dcvmx-pko.c237 config.s.intr = __cvmx_pko_int(interface, index);

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