1/* SPDX-License-Identifier: BSD-3-Clause */ 2/* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2022 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9#ifndef LPDDR4_AM6X_SANITY_H 10#define LPDDR4_AM6X_SANITY_H 11 12#include <errno.h> 13#include <linux/types.h> 14#include <lpddr4_if.h> 15#include <lpddr4_if.h> 16#include <lpddr4_if.h> 17#include <lpddr4_if.h> 18 19static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus); 20static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr); 21static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus); 22static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr); 23 24#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1 25#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2 26#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3 27#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4 28 29static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus) 30{ 31 u32 ret = 0; 32 33 if (pd == NULL) { 34 ret = EINVAL; 35 } else if (irqstatus == NULL) { 36 ret = EINVAL; 37 } else if ( 38 (intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) && 39 (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) && 40 (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) && 41 (intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) && 42 (intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) && 43 (intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) && 44 (intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) && 45 (intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) && 46 (intr != LPDDR4_INTR_ECC_ERROR) && 47 (intr != LPDDR4_INTR_LP_DONE) && 48 (intr != LPDDR4_INTR_LP_TIMEOUT) && 49 (intr != LPDDR4_INTR_PORT_TIMEOUT) && 50 (intr != LPDDR4_INTR_RFIFO_TIMEOUT) && 51 (intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) && 52 (intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) && 53 (intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) && 54 (intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) && 55 (intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) && 56 (intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && 57 (intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) && 58 (intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) && 59 (intr != LPDDR4_INTR_USERIF_WRAP) && 60 (intr != LPDDR4_INTR_USERIF_INVAL_SETTING) && 61 (intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) && 62 (intr != LPDDR4_INTR_MISC_SW_REQ_MODE) && 63 (intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) && 64 (intr != LPDDR4_INTR_MISC_TEMP_ALERT) && 65 (intr != LPDDR4_INTR_MISC_REFRESH_STATUS) && 66 (intr != LPDDR4_INTR_BIST_DONE) && 67 (intr != LPDDR4_INTR_CRC) && 68 (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) && 69 (intr != LPDDR4_INTR_DFI_PHY_ERROR) && 70 (intr != LPDDR4_INTR_DFI_BUS_ERROR) && 71 (intr != LPDDR4_INTR_DFI_STATE_CHANGE) && 72 (intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) && 73 (intr != LPDDR4_INTR_DFI_TIMEOUT) && 74 (intr != LPDDR4_INTR_DIMM) && 75 (intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && 76 (intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) && 77 (intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) && 78 (intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) && 79 (intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) && 80 (intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) && 81 (intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) && 82 (intr != LPDDR4_INTR_MC_INIT_DONE) && 83 (intr != LPDDR4_INTR_INIT_POWER_ON_STATE) && 84 (intr != LPDDR4_INTR_MRR_ERROR) && 85 (intr != LPDDR4_INTR_MR_READ_DONE) && 86 (intr != LPDDR4_INTR_MR_WRITE_DONE) && 87 (intr != LPDDR4_INTR_PARITY_ERROR) && 88 (intr != LPDDR4_INTR_LOR_BITS) 89 ) { 90 ret = EINVAL; 91 } else { 92 } 93 94 return ret; 95} 96 97static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr) 98{ 99 u32 ret = 0; 100 101 if (pd == NULL) { 102 ret = EINVAL; 103 } else if ( 104 (intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) && 105 (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) && 106 (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) && 107 (intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) && 108 (intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) && 109 (intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) && 110 (intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) && 111 (intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) && 112 (intr != LPDDR4_INTR_ECC_ERROR) && 113 (intr != LPDDR4_INTR_LP_DONE) && 114 (intr != LPDDR4_INTR_LP_TIMEOUT) && 115 (intr != LPDDR4_INTR_PORT_TIMEOUT) && 116 (intr != LPDDR4_INTR_RFIFO_TIMEOUT) && 117 (intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) && 118 (intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) && 119 (intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) && 120 (intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) && 121 (intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) && 122 (intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && 123 (intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) && 124 (intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) && 125 (intr != LPDDR4_INTR_USERIF_WRAP) && 126 (intr != LPDDR4_INTR_USERIF_INVAL_SETTING) && 127 (intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) && 128 (intr != LPDDR4_INTR_MISC_SW_REQ_MODE) && 129 (intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) && 130 (intr != LPDDR4_INTR_MISC_TEMP_ALERT) && 131 (intr != LPDDR4_INTR_MISC_REFRESH_STATUS) && 132 (intr != LPDDR4_INTR_BIST_DONE) && 133 (intr != LPDDR4_INTR_CRC) && 134 (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) && 135 (intr != LPDDR4_INTR_DFI_PHY_ERROR) && 136 (intr != LPDDR4_INTR_DFI_BUS_ERROR) && 137 (intr != LPDDR4_INTR_DFI_STATE_CHANGE) && 138 (intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) && 139 (intr != LPDDR4_INTR_DFI_TIMEOUT) && 140 (intr != LPDDR4_INTR_DIMM) && 141 (intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && 142 (intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) && 143 (intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) && 144 (intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) && 145 (intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) && 146 (intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) && 147 (intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) && 148 (intr != LPDDR4_INTR_MC_INIT_DONE) && 149 (intr != LPDDR4_INTR_INIT_POWER_ON_STATE) && 150 (intr != LPDDR4_INTR_MRR_ERROR) && 151 (intr != LPDDR4_INTR_MR_READ_DONE) && 152 (intr != LPDDR4_INTR_MR_WRITE_DONE) && 153 (intr != LPDDR4_INTR_PARITY_ERROR) && 154 (intr != LPDDR4_INTR_LOR_BITS) 155 ) { 156 ret = EINVAL; 157 } else { 158 } 159 160 return ret; 161} 162 163static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus) 164{ 165 u32 ret = 0; 166 167 if (pd == NULL) { 168 ret = EINVAL; 169 } else if (irqstatus == NULL) { 170 ret = EINVAL; 171 } else if ( 172 (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) && 173 (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) && 174 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) && 175 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) && 176 (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) && 177 (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) && 178 (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) && 179 (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) && 180 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) && 181 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) && 182 (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) && 183 (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) && 184 (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) && 185 (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) && 186 (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) && 187 (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) && 188 (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) && 189 (intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) && 190 (intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) && 191 (intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) && 192 (intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) && 193 (intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) && 194 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) && 195 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) && 196 (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) && 197 (intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) && 198 (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) && 199 (intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) && 200 (intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT) 201 ) { 202 ret = EINVAL; 203 } else { 204 } 205 206 return ret; 207} 208 209static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr) 210{ 211 u32 ret = 0; 212 213 if (pd == NULL) { 214 ret = EINVAL; 215 } else if ( 216 (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) && 217 (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) && 218 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) && 219 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) && 220 (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) && 221 (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) && 222 (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) && 223 (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) && 224 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) && 225 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) && 226 (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) && 227 (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) && 228 (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) && 229 (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) && 230 (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) && 231 (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) && 232 (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) && 233 (intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) && 234 (intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) && 235 (intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) && 236 (intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) && 237 (intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) && 238 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) && 239 (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) && 240 (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) && 241 (intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) && 242 (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) && 243 (intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) && 244 (intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT) 245 ) { 246 ret = EINVAL; 247 } else { 248 } 249 250 return ret; 251} 252 253#endif /* LPDDR4_AM6X_SANITY_H */ 254