1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 4 */ 5 6#include <common.h> 7#include <clk.h> 8#include <dm.h> 9#include <log.h> 10#include <malloc.h> 11#include <spi.h> 12#include <asm/global_data.h> 13#include <dm/device_compat.h> 14#include <linux/bitops.h> 15#include <linux/delay.h> 16#include <linux/errno.h> 17#include <asm/io.h> 18#include <asm/gpio.h> 19#include <asm/arch/imx-regs.h> 20#include <asm/arch/clock.h> 21#include <asm/mach-imx/spi.h> 22#include <linux/printk.h> 23 24DECLARE_GLOBAL_DATA_PTR; 25 26/* MX35 and older is CSPI */ 27#if defined(CONFIG_MX31) 28#define MXC_CSPI 29struct cspi_regs { 30 u32 rxdata; 31 u32 txdata; 32 u32 ctrl; 33 u32 intr; 34 u32 dma; 35 u32 stat; 36 u32 period; 37 u32 test; 38}; 39 40#define MXC_CSPICTRL_EN BIT(0) 41#define MXC_CSPICTRL_MODE BIT(1) 42#define MXC_CSPICTRL_XCH BIT(2) 43#define MXC_CSPICTRL_SMC BIT(3) 44#define MXC_CSPICTRL_POL BIT(4) 45#define MXC_CSPICTRL_PHA BIT(5) 46#define MXC_CSPICTRL_SSCTL BIT(6) 47#define MXC_CSPICTRL_SSPOL BIT(7) 48#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 49#define MXC_CSPICTRL_RXOVF BIT(6) 50#define MXC_CSPIPERIOD_32KHZ BIT(15) 51#define MAX_SPI_BYTES 4 52#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) 53#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) 54#define MXC_CSPICTRL_TC BIT(8) 55#define MXC_CSPICTRL_MAXBITS 0x1f 56 57#else /* MX51 and newer is ECSPI */ 58#define MXC_ECSPI 59struct cspi_regs { 60 u32 rxdata; 61 u32 txdata; 62 u32 ctrl; 63 u32 cfg; 64 u32 intr; 65 u32 dma; 66 u32 stat; 67 u32 period; 68}; 69 70#define MXC_CSPICTRL_EN BIT(0) 71#define MXC_CSPICTRL_MODE BIT(1) 72#define MXC_CSPICTRL_XCH BIT(2) 73#define MXC_CSPICTRL_MODE_MASK (0xf << 4) 74#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 75#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 76#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 77#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 78#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 79#define MXC_CSPICTRL_MAXBITS 0xfff 80#define MXC_CSPICTRL_TC BIT(7) 81#define MXC_CSPICTRL_RXOVF BIT(6) 82#define MXC_CSPIPERIOD_32KHZ BIT(15) 83#define MAX_SPI_BYTES 32 84 85/* Bit position inside CTRL register to be associated with SS */ 86#define MXC_CSPICTRL_CHAN 18 87 88/* Bit position inside CON register to be associated with SS */ 89#define MXC_CSPICON_PHA 0 /* SCLK phase control */ 90#define MXC_CSPICON_POL 4 /* SCLK polarity */ 91#define MXC_CSPICON_SSPOL 12 /* SS polarity */ 92#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 93#endif 94 95__weak int board_spi_cs_gpio(unsigned bus, unsigned cs) 96{ 97 return -1; 98} 99 100#define OUT MXC_GPIO_DIRECTION_OUT 101 102#define reg_read readl 103#define reg_write(a, v) writel(v, a) 104 105#if !defined(CFG_SYS_SPI_MXC_WAIT) 106#define CFG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ 107#endif 108 109#define MAX_CS_COUNT 4 110 111struct mxc_spi_slave { 112 struct spi_slave slave; 113 unsigned long base; 114 u32 ctrl_reg; 115#if defined(MXC_ECSPI) 116 u32 cfg_reg; 117#endif 118 int gpio; 119 int ss_pol; 120 unsigned int max_hz; 121 unsigned int mode; 122 struct gpio_desc ss; 123 struct gpio_desc cs_gpios[MAX_CS_COUNT]; 124 struct udevice *dev; 125}; 126 127static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 128{ 129 return container_of(slave, struct mxc_spi_slave, slave); 130} 131 132static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs) 133{ 134#if CONFIG_IS_ENABLED(DM_SPI) 135 struct udevice *dev = mxcs->dev; 136 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 137 138 u32 cs = slave_plat->cs; 139 140 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs])) 141 return; 142 143 dm_gpio_set_value(&mxcs->cs_gpios[cs], 1); 144#else 145 if (mxcs->gpio > 0) 146 gpio_set_value(mxcs->gpio, mxcs->ss_pol); 147#endif 148} 149 150static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs) 151{ 152#if CONFIG_IS_ENABLED(DM_SPI) 153 struct udevice *dev = mxcs->dev; 154 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 155 156 u32 cs = slave_plat->cs; 157 158 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs])) 159 return; 160 161 dm_gpio_set_value(&mxcs->cs_gpios[cs], 0); 162#else 163 if (mxcs->gpio > 0) 164 gpio_set_value(mxcs->gpio, !(mxcs->ss_pol)); 165#endif 166} 167 168u32 get_cspi_div(u32 div) 169{ 170 int i; 171 172 for (i = 0; i < 8; i++) { 173 if (div <= (4 << i)) 174 return i; 175 } 176 return i; 177} 178 179#ifdef MXC_CSPI 180static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) 181{ 182 unsigned int ctrl_reg; 183 u32 clk_src; 184 u32 div; 185 unsigned int max_hz = mxcs->max_hz; 186 unsigned int mode = mxcs->mode; 187 188 clk_src = mxc_get_clock(MXC_CSPI_CLK); 189 190 div = DIV_ROUND_UP(clk_src, max_hz); 191 div = get_cspi_div(div); 192 193 debug("clk %d Hz, div %d, real clk %d Hz\n", 194 max_hz, div, clk_src / (4 << div)); 195 196 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 197 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | 198 MXC_CSPICTRL_DATARATE(div) | 199 MXC_CSPICTRL_EN | 200 MXC_CSPICTRL_MODE; 201 202 if (mode & SPI_CPHA) 203 ctrl_reg |= MXC_CSPICTRL_PHA; 204 if (mode & SPI_CPOL) 205 ctrl_reg |= MXC_CSPICTRL_POL; 206 if (mode & SPI_CS_HIGH) 207 ctrl_reg |= MXC_CSPICTRL_SSPOL; 208 mxcs->ctrl_reg = ctrl_reg; 209 210 return 0; 211} 212#endif 213 214#ifdef MXC_ECSPI 215static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) 216{ 217 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 218 s32 reg_ctrl, reg_config; 219 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; 220 u32 pre_div = 0, post_div = 0; 221 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 222 unsigned int max_hz = mxcs->max_hz; 223 unsigned int mode = mxcs->mode; 224 225 /* 226 * Reset SPI and set all CSs to master mode, if toggling 227 * between slave and master mode we might see a glitch 228 * on the clock line 229 */ 230 reg_ctrl = MXC_CSPICTRL_MODE_MASK; 231 reg_write(®s->ctrl, reg_ctrl); 232 reg_ctrl |= MXC_CSPICTRL_EN; 233 reg_write(®s->ctrl, reg_ctrl); 234 235 if (clk_src > max_hz) { 236 pre_div = (clk_src - 1) / max_hz; 237 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */ 238 post_div = fls(pre_div); 239 if (post_div > 4) { 240 post_div -= 4; 241 if (post_div >= 16) { 242 printf("Error: no divider for the freq: %d\n", 243 max_hz); 244 return -1; 245 } 246 pre_div >>= post_div; 247 } else { 248 post_div = 0; 249 } 250 } 251 252 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 253 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 254 MXC_CSPICTRL_SELCHAN(cs); 255 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 256 MXC_CSPICTRL_PREDIV(pre_div); 257 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 258 MXC_CSPICTRL_POSTDIV(post_div); 259 260 if (mode & SPI_CS_HIGH) 261 ss_pol = 1; 262 263 if (mode & SPI_CPOL) { 264 sclkpol = 1; 265 sclkctl = 1; 266 } 267 268 if (mode & SPI_CPHA) 269 sclkpha = 1; 270 271 reg_config = reg_read(®s->cfg); 272 273 /* 274 * Configuration register setup 275 * The MX51 supports different setup for each SS 276 */ 277 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 278 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 279 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 280 (sclkpol << (cs + MXC_CSPICON_POL)); 281 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | 282 (sclkctl << (cs + MXC_CSPICON_CTL)); 283 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 284 (sclkpha << (cs + MXC_CSPICON_PHA)); 285 286 debug("reg_ctrl = 0x%x\n", reg_ctrl); 287 reg_write(®s->ctrl, reg_ctrl); 288 debug("reg_config = 0x%x\n", reg_config); 289 reg_write(®s->cfg, reg_config); 290 291 /* save config register and control register */ 292 mxcs->ctrl_reg = reg_ctrl; 293 mxcs->cfg_reg = reg_config; 294 295 /* clear interrupt reg */ 296 reg_write(®s->intr, 0); 297 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 298 299 return 0; 300} 301#endif 302 303int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen, 304 const u8 *dout, u8 *din, unsigned long flags) 305{ 306 int nbytes = DIV_ROUND_UP(bitlen, 8); 307 u32 data, cnt, i; 308 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 309 u32 ts; 310 int status; 311 312 debug("%s: bitlen %d dout 0x%lx din 0x%lx\n", 313 __func__, bitlen, (ulong)dout, (ulong)din); 314 315 mxcs->ctrl_reg = (mxcs->ctrl_reg & 316 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 317 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 318 319 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 320#ifdef MXC_ECSPI 321 reg_write(®s->cfg, mxcs->cfg_reg); 322#endif 323 324 /* Clear interrupt register */ 325 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 326 327 /* 328 * The SPI controller works only with words, 329 * check if less than a word is sent. 330 * Access to the FIFO is only 32 bit 331 */ 332 if (bitlen % 32) { 333 data = 0; 334 cnt = (bitlen % 32) / 8; 335 if (dout) { 336 for (i = 0; i < cnt; i++) { 337 data = (data << 8) | (*dout++ & 0xFF); 338 } 339 } 340 debug("Sending SPI 0x%x\n", data); 341 342 reg_write(®s->txdata, data); 343 nbytes -= cnt; 344 } 345 346 data = 0; 347 348 while (nbytes > 0) { 349 data = 0; 350 if (dout) { 351 /* Buffer is not 32-bit aligned */ 352 if ((unsigned long)dout & 0x03) { 353 data = 0; 354 for (i = 0; i < 4; i++) 355 data = (data << 8) | (*dout++ & 0xFF); 356 } else { 357 data = *(u32 *)dout; 358 data = cpu_to_be32(data); 359 dout += 4; 360 } 361 } 362 debug("Sending SPI 0x%x\n", data); 363 reg_write(®s->txdata, data); 364 nbytes -= 4; 365 } 366 367 /* FIFO is written, now starts the transfer setting the XCH bit */ 368 reg_write(®s->ctrl, mxcs->ctrl_reg | 369 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 370 371 ts = get_timer(0); 372 status = reg_read(®s->stat); 373 /* Wait until the TC (Transfer completed) bit is set */ 374 while ((status & MXC_CSPICTRL_TC) == 0) { 375 if (get_timer(ts) > CFG_SYS_SPI_MXC_WAIT) { 376 printf("spi_xchg_single: Timeout!\n"); 377 return -1; 378 } 379 status = reg_read(®s->stat); 380 } 381 382 /* Transfer completed, clear any pending request */ 383 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 384 385 nbytes = DIV_ROUND_UP(bitlen, 8); 386 387 if (bitlen % 32) { 388 data = reg_read(®s->rxdata); 389 cnt = (bitlen % 32) / 8; 390 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); 391 debug("SPI Rx unaligned: 0x%x\n", data); 392 if (din) { 393 memcpy(din, &data, cnt); 394 din += cnt; 395 } 396 nbytes -= cnt; 397 } 398 399 while (nbytes > 0) { 400 u32 tmp; 401 tmp = reg_read(®s->rxdata); 402 data = cpu_to_be32(tmp); 403 debug("SPI Rx: 0x%x 0x%x\n", tmp, data); 404 cnt = min_t(u32, nbytes, sizeof(data)); 405 if (din) { 406 memcpy(din, &data, cnt); 407 din += cnt; 408 } 409 nbytes -= cnt; 410 } 411 412 return 0; 413 414} 415 416static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs, 417 unsigned int bitlen, const void *dout, 418 void *din, unsigned long flags) 419{ 420 int n_bytes = DIV_ROUND_UP(bitlen, 8); 421 int n_bits; 422 int ret; 423 u32 blk_size; 424 u8 *p_outbuf = (u8 *)dout; 425 u8 *p_inbuf = (u8 *)din; 426 427 if (!mxcs) 428 return -EINVAL; 429 430 if (flags & SPI_XFER_BEGIN) 431 mxc_spi_cs_activate(mxcs); 432 433 while (n_bytes > 0) { 434 if (n_bytes < MAX_SPI_BYTES) 435 blk_size = n_bytes; 436 else 437 blk_size = MAX_SPI_BYTES; 438 439 n_bits = blk_size * 8; 440 441 ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0); 442 443 if (ret) 444 return ret; 445 if (dout) 446 p_outbuf += blk_size; 447 if (din) 448 p_inbuf += blk_size; 449 n_bytes -= blk_size; 450 } 451 452 if (flags & SPI_XFER_END) { 453 mxc_spi_cs_deactivate(mxcs); 454 } 455 456 return 0; 457} 458 459static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs) 460{ 461 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 462 int ret; 463 464 reg_write(®s->rxdata, 1); 465 udelay(1); 466 ret = spi_cfg_mxc(mxcs, cs); 467 if (ret) { 468 printf("mxc_spi: cannot setup SPI controller\n"); 469 return ret; 470 } 471 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); 472 reg_write(®s->intr, 0); 473 474 return 0; 475} 476 477#if !CONFIG_IS_ENABLED(DM_SPI) 478int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 479 void *din, unsigned long flags) 480{ 481 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 482 483 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags); 484} 485 486/* 487 * Some SPI devices require active chip-select over multiple 488 * transactions, we achieve this using a GPIO. Still, the SPI 489 * controller has to be configured to use one of its own chipselects. 490 * To use this feature you have to implement board_spi_cs_gpio() to assign 491 * a gpio value for each cs (-1 if cs doesn't need to use gpio). 492 * You must use some unused on this SPI controller cs between 0 and 3. 493 */ 494static int setup_cs_gpio(struct mxc_spi_slave *mxcs, 495 unsigned int bus, unsigned int cs) 496{ 497 int ret; 498 499 mxcs->gpio = board_spi_cs_gpio(bus, cs); 500 if (mxcs->gpio == -1) 501 return 0; 502 503 gpio_request(mxcs->gpio, "spi-cs"); 504 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); 505 if (ret) { 506 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 507 return -EINVAL; 508 } 509 510 return 0; 511} 512 513static unsigned long spi_bases[] = { 514 MXC_SPI_BASE_ADDRESSES 515}; 516 517struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 518 unsigned int max_hz, unsigned int mode) 519{ 520 struct mxc_spi_slave *mxcs; 521 int ret; 522 523 if (bus >= ARRAY_SIZE(spi_bases)) 524 return NULL; 525 526 if (max_hz == 0) { 527 printf("Error: desired clock is 0\n"); 528 return NULL; 529 } 530 531 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); 532 if (!mxcs) { 533 puts("mxc_spi: SPI Slave not allocated !\n"); 534 return NULL; 535 } 536 537 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 538 539 ret = setup_cs_gpio(mxcs, bus, cs); 540 if (ret < 0) { 541 free(mxcs); 542 return NULL; 543 } 544 545 mxcs->base = spi_bases[bus]; 546 mxcs->max_hz = max_hz; 547 mxcs->mode = mode; 548 549 return &mxcs->slave; 550} 551 552void spi_free_slave(struct spi_slave *slave) 553{ 554 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 555 556 free(mxcs); 557} 558 559int spi_claim_bus(struct spi_slave *slave) 560{ 561 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 562 563 return mxc_spi_claim_bus_internal(mxcs, slave->cs); 564} 565 566void spi_release_bus(struct spi_slave *slave) 567{ 568 /* TODO: Shut the controller down */ 569} 570#else 571 572static int mxc_spi_probe(struct udevice *bus) 573{ 574 struct mxc_spi_slave *mxcs = dev_get_plat(bus); 575 int ret; 576 int i; 577 578 ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios, 579 ARRAY_SIZE(mxcs->cs_gpios), 0); 580 if (ret < 0) { 581 pr_err("Can't get %s gpios! Error: %d", bus->name, ret); 582 return ret; 583 } 584 585 for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) { 586 if (!dm_gpio_is_valid(&mxcs->cs_gpios[i])) 587 continue; 588 589 ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i], 590 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); 591 if (ret) { 592 dev_err(bus, "Setting cs %d error\n", i); 593 return ret; 594 } 595 } 596 597 mxcs->base = dev_read_addr(bus); 598 if (mxcs->base == FDT_ADDR_T_NONE) 599 return -ENODEV; 600 601#if CONFIG_IS_ENABLED(CLK) 602 struct clk clk; 603 ret = clk_get_by_index(bus, 0, &clk); 604 if (ret) 605 return ret; 606 607 clk_enable(&clk); 608 609 mxcs->max_hz = clk_get_rate(&clk); 610#else 611 int node = dev_of_offset(bus); 612 const void *blob = gd->fdt_blob; 613 mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 614 20000000); 615#endif 616 617 return 0; 618} 619 620static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen, 621 const void *dout, void *din, unsigned long flags) 622{ 623 struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent); 624 625 626 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags); 627} 628 629static int mxc_spi_claim_bus(struct udevice *dev) 630{ 631 struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent); 632 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 633 634 mxcs->dev = dev; 635 636 return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs); 637} 638 639static int mxc_spi_release_bus(struct udevice *dev) 640{ 641 return 0; 642} 643 644static int mxc_spi_set_speed(struct udevice *bus, uint speed) 645{ 646 struct mxc_spi_slave *mxcs = dev_get_plat(bus); 647 648 mxcs->max_hz = speed; 649 650 return 0; 651} 652 653static int mxc_spi_set_mode(struct udevice *bus, uint mode) 654{ 655 struct mxc_spi_slave *mxcs = dev_get_plat(bus); 656 657 mxcs->mode = mode; 658 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 659 660 return 0; 661} 662 663static const struct dm_spi_ops mxc_spi_ops = { 664 .claim_bus = mxc_spi_claim_bus, 665 .release_bus = mxc_spi_release_bus, 666 .xfer = mxc_spi_xfer, 667 .set_speed = mxc_spi_set_speed, 668 .set_mode = mxc_spi_set_mode, 669}; 670 671static const struct udevice_id mxc_spi_ids[] = { 672 { .compatible = "fsl,imx51-ecspi" }, 673 { .compatible = "fsl,imx6ul-ecspi" }, 674 { } 675}; 676 677U_BOOT_DRIVER(mxc_spi) = { 678 .name = "mxc_spi", 679 .id = UCLASS_SPI, 680 .of_match = mxc_spi_ids, 681 .ops = &mxc_spi_ops, 682 .plat_auto = sizeof(struct mxc_spi_slave), 683 .probe = mxc_spi_probe, 684}; 685#endif 686