1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2022 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9#include <errno.h> 10 11#include "cps_drv_lpddr4.h" 12#include "lpddr4_ctl_regs.h" 13#include "lpddr4_if.h" 14#include "lpddr4.h" 15#include "lpddr4_structs_if.h" 16 17static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound); 18 19u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd) 20{ 21 u32 result = 0U; 22 u32 regval = 0U; 23 24 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 25 26 regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG))); 27 regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval); 28 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval); 29 return result; 30} 31 32u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask) 33{ 34 u32 result = 0U; 35 u32 lowermask = 0U; 36 37 result = lpddr4_getctlinterruptmasksf(pd, mask); 38 if (result == (u32)0) { 39 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 40 lowermask = (u32)(CPS_FLD_READ(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG)))); 41 *mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG)))); 42 *mask = (u64)((*mask << WORD_SHIFT) | lowermask); 43 } 44 return result; 45} 46 47u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask) 48{ 49 u32 result; 50 u32 regval = 0; 51 const u64 ui64one = 1ULL; 52 const u32 ui32irqcount = (u32)LPDDR4_INTR_LOR_BITS + 1U; 53 54 result = lpddr4_setctlinterruptmasksf(pd, mask); 55 if ((result == (u32)0) && (ui32irqcount < 64U)) { 56 if (*mask >= (ui64one << ui32irqcount)) 57 result = (u32)EINVAL; 58 } 59 60 if (result == (u32)0) { 61 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 62 63 regval = (u32)(*mask & WORD_MASK); 64 regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG)), regval); 65 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval); 66 67 regval = (u32)((*mask >> WORD_SHIFT) & WORD_MASK); 68 regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG)), regval); 69 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval); 70 } 71 return result; 72} 73 74u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus) 75{ 76 u32 result; 77 u32 ctlirqstatus = 0; 78 u32 fieldshift = 0; 79 80 result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus); 81 if (result == (u32)0) { 82 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 83 84 if ((u32)intr >= (u32)WORD_SHIFT) { 85 ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_1__REG)); 86 fieldshift = (u32)intr - ((u32)WORD_SHIFT); 87 } else { 88 ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_0__REG)); 89 fieldshift = (u32)intr; 90 } 91 92 if (fieldshift < WORD_SHIFT) { 93 if (((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) > 0U) 94 *irqstatus = true; 95 else 96 *irqstatus = false; 97 } 98 } 99 return result; 100} 101 102u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr) 103{ 104 u32 result = 0; 105 u32 regval = 0; 106 u32 localinterrupt = (u32)intr; 107 108 result = LPDDR4_INTR_AckCtlIntSF(pd, intr); 109 if (result == (u32)0) { 110 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 111 112 if (localinterrupt > WORD_SHIFT) { 113 localinterrupt = (localinterrupt - (u32)WORD_SHIFT); 114 regval = ((u32)LPDDR4_BIT_MASK << localinterrupt); 115 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), regval); 116 } else { 117 regval = ((u32)LPDDR4_BIT_MASK << localinterrupt); 118 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), regval); 119 } 120 } 121 122 return result; 123} 124 125void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr) 126{ 127 u32 regval; 128 u32 errbitmask = 0U; 129 u32 snum; 130 volatile u32 *regaddress; 131 132 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG)); 133 errbitmask = (LPDDR4_BIT_MASK << 1) | (LPDDR4_BIT_MASK); 134 for (snum = 0U; snum < DSLICE_NUM; snum++) { 135 regval = CPS_REG_READ(regaddress); 136 if ((regval & errbitmask) != 0U) { 137 debuginfo->wrlvlerror = CDN_TRUE; 138 *errfoundptr = true; 139 } 140 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); 141 } 142} 143 144static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound) 145{ 146 volatile u32 *regaddress; 147 u32 snum = 0U; 148 u32 errbitmask = 0U; 149 u32 regval = 0U; 150 151 if (*errorfound == (bool)false) { 152 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG)); 153 errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK); 154 for (snum = (u32)0U; snum < DSLICE_NUM; snum++) { 155 regval = CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD, CPS_REG_READ(regaddress)); 156 if ((regval & errbitmask) != RX_CAL_DONE) { 157 debuginfo->rxoffseterror = (u8)true; 158 *errorfound = true; 159 } 160 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); 161 } 162 } 163} 164 165u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo) 166{ 167 u32 result = 0U; 168 bool errorfound = false; 169 170 result = lpddr4_getdebuginitinfosf(pd, debuginfo); 171 if (result == (u32)0) { 172 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 173 lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound); 174 lpddr4_setsettings(ctlregbase, errorfound); 175 lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound); 176 errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound); 177 } 178 179 if (errorfound == (bool)true) 180 result = (u32)EPROTO; 181 182 return result; 183} 184 185u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam) 186{ 187 u32 result = 0U; 188 u32 fldval = 0U; 189 190 result = lpddr4_geteccenablesf(pd, eccparam); 191 if (result == (u32)0) { 192 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 193 194 fldval = CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG))); 195 switch (fldval) { 196 case 3: 197 *eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT; 198 break; 199 case 2: 200 *eccparam = LPDDR4_ECC_ERR_DETECT; 201 break; 202 case 1: 203 *eccparam = LPDDR4_ECC_ENABLED; 204 break; 205 default: 206 *eccparam = LPDDR4_ECC_DISABLED; 207 break; 208 } 209 } 210 return result; 211} 212 213u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam) 214{ 215 u32 result = 0U; 216 u32 regval = 0U; 217 218 result = lpddr4_seteccenablesf(pd, eccparam); 219 if (result == (u32)0) { 220 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 221 222 regval = CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)), *eccparam); 223 CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval); 224 } 225 return result; 226} 227 228u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode) 229{ 230 u32 result = 0U; 231 232 result = lpddr4_getreducmodesf(pd, mode); 233 if (result == (u32)0) { 234 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 235 if (CPS_FLD_READ(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U) 236 *mode = LPDDR4_REDUC_ON; 237 else 238 *mode = LPDDR4_REDUC_OFF; 239 } 240 return result; 241} 242u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode) 243{ 244 u32 result = 0U; 245 u32 regval = 0U; 246 247 result = lpddr4_setreducmodesf(pd, mode); 248 if (result == (u32)0) { 249 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 250 regval = (u32)CPS_FLD_WRITE(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG)), *mode); 251 CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval); 252 } 253 return result; 254} 255 256u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus) 257{ 258 u32 lowerdata; 259 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; 260 u32 result = (u32)0; 261 262 if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) { 263 *mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG))); 264 *mmrvalue = (u64)0; 265 result = (u32)EIO; 266 } else { 267 *mrrstatus = (u8)0; 268 lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG)); 269 *mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG)); 270 *mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata); 271 result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE); 272 } 273 return result; 274} 275 276u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset) 277{ 278 u32 rwmask = 0U; 279 280 switch (dslicenum) { 281 case 0: 282 if (arrayoffset < DSLICE0_REG_COUNT) 283 rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset]; 284 break; 285 case 1: 286 if (arrayoffset < DSLICE1_REG_COUNT) 287 rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset]; 288 break; 289 case 2: 290 if (arrayoffset < DSLICE2_REG_COUNT) 291 rwmask = g_lpddr4_data_slice_2_rw_mask[arrayoffset]; 292 break; 293 default: 294 if (arrayoffset < DSLICE3_REG_COUNT) 295 rwmask = g_lpddr4_data_slice_3_rw_mask[arrayoffset]; 296 break; 297 } 298 return rwmask; 299} 300