Searched refs:frac (Results 1 - 25 of 36) sorted by relevance

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/u-boot/drivers/clk/imx/
H A Dclk-pfd.c49 u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f; local
52 do_div(tmp, frac);
62 u8 frac; local
66 frac = tmp;
67 if (frac < 12)
68 frac = 12;
69 else if (frac > 35)
70 frac = 35;
73 writel(frac << (pfd->idx * 8), pfd->reg + SET);
/u-boot/drivers/video/meson/
H A Dmeson_vclk.c429 unsigned int frac, unsigned int od1,
436 if (frac)
438 0x00004000 | frac);
457 hhi_write(HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
478 hhi_write(HHI_HDMI_PLL_CNTL2, frac);
483 if (frac < 0x10000) {
575 unsigned int frac; local
591 frac = div_u64((u64)pll_freq * (u64)frac_max, parent_freq);
593 if (frac_m > frac)
595 frac
428 meson_hdmi_pll_set_params(struct meson_vpu_priv *priv, unsigned int m, unsigned int frac, unsigned int od1, unsigned int od2, unsigned int od3) argument
600 meson_hdmi_pll_validate_params(struct meson_vpu_priv *priv, unsigned int m, unsigned int frac) argument
628 meson_hdmi_pll_find_params(struct meson_vpu_priv *priv, unsigned int freq, unsigned int *m, unsigned int *frac, unsigned int *od) argument
655 unsigned int od, m, frac; local
670 unsigned int od, m, frac, od1, od2, od3; local
701 unsigned int m = 0, frac = 0; local
[all...]
/u-boot/drivers/pwm/
H A Dpwm-sifive.c70 u32 scale, val = 0, frac; local
92 frac = DIV_ROUND_CLOSEST_ULL(num, period_ns);
93 frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
94 frac = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac;
97 writel(frac, priv->base + regs->cmp0 + channel *
/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dclock.c43 uint8_t clkfrac, frac; local
64 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
66 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
93 uint8_t clkfrac, frac; local
107 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
109 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
124 uint8_t clkfrac, frac; local
137 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
139 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
/u-boot/drivers/clk/starfive/
H A Dclk-jh7110-pll.c49 u32 frac; member in struct:starfive_pllx_rate
56 u32 frac; member in struct:starfive_pllx_offset
136 .frac = 0x20,
153 .frac = 0x28,
170 .frac = 0x30,
250 u64 frac; local
262 frac = (u64)getbits_le32((ulong)pll->base + pll->offset->frac,
285 * NF is fractional frequency dividing ratio, set by frac[23:0], NF =frac[2
[all...]
/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dpcc.c161 int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div) argument
166 (div == 1 && frac != 0))
180 printf("Not permit to set div/frac val = 0x%x\n", val);
184 if (frac)
256 u32 reg, val, rate, frac, div; local
272 frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
279 rate = rate * (frac + 1) / (div + 1);
H A Dscg.c631 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac) argument
637 if (frac < 12 || frac > 35)
700 reg |= (frac << shift) & mask;
/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h69 .frac = _frac, \
93 unsigned int frac; member in struct:rockchip_pll_rate_table
H A Dcru_rk3036.h63 u32 frac; member in struct:pll_div
H A Dcru_rv1108.h60 u32 frac; member in struct:pll_div
H A Dcru_rk322x.h64 u32 frac; member in struct:pll_div
H A Dcru_rk3128.h70 u32 frac; member in struct:pll_div
H A Dcru_rv1126.h144 unsigned int frac; member in struct:pll_rate_table
/u-boot/drivers/phy/
H A Dphy-stm32-usbphyc.c139 u16 frac; member in struct:pll_params
159 unsigned long long fvco, ndiv, frac; local
176 frac = fvco * (1 << 16);
177 do_div(frac, (clk_rate * 2));
178 frac = frac - (ndiv * (1 << 16));
179 pll_params->frac = (u16)frac;
199 if (pll_params.frac) {
201 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIF
[all...]
/u-boot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S37 #define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \
38 (PLL_CPU_NFRAC(frac) | \
47 #define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \
48 (PLL_DDR_NFRAC(frac) | \
/u-boot/drivers/clk/
H A Dclk_pic32.c180 u64 frac; local
192 frac = parent_rate;
193 frac <<= 8;
194 do_div(frac, rate);
195 frac -= (u64)(div << 9);
196 trim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : (u32)frac;
H A Dclk_versal.c441 u32 frac; local
460 frac = ret_payload[1];
462 freq = (fbdiv * parent_rate) >> (1 << frac);
/u-boot/arch/arm/mach-imx/imx8ulp/
H A Dclock.c416 u32 frac, rate, parent_rate, pfd, div; local
437 for (frac = 0; frac < 2; frac++) {
438 if (pcd == 0 && frac == 1)
441 rate = parent_rate * (frac + 1) / (pcd + 1);
448 best_frac = frac;
462 debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_pfd %u, best_div %u\n",
H A Dpcc.c380 int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div) argument
393 if (div > 8 || (div == 1 && frac != 0))
405 printf("Not permit to set div/frac val = 0x%x\n", val);
409 if (frac)
534 u32 val, rate, frac, div; local
558 frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
565 rate = rate * (frac + 1) / (div + 1);
/u-boot/drivers/clk/rockchip/
H A Dclk_pll.c136 rate_table->frac = 0;
145 debug("frac div,fin_hz = %ld,fout_hz = %ld\n",
147 debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n",
152 debug("frac get refdiv = %d, fbdiv = %d\n",
155 rate_table->frac = 0;
162 rate_table->frac = frac_64;
163 if (rate_table->frac > 0)
165 debug("frac = %x\n", rate_table->frac);
306 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac
363 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; local
[all...]
/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c188 u32 freq, div, frac; local
215 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
222 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
230 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
237 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
245 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
252 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
260 frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
267 frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
274 frac
[all...]
/u-boot/drivers/clk/at91/
H A Dclk-sam9x60-pll.c25 #define UBOOT_DM_CLK_AT91_SAM9X60_FRAC_PLL "at91-sam9x60-frac-pll-clk"
59 static long sam9x60_frac_pll_compute_mul_frac(u32 *mul, u32 *frac, ulong rate, argument
90 *frac = nfrac;
145 u32 mul, frac, val; local
154 frac = (val & pll->layout->frac_mask) >> pll->layout->frac_shift;
156 return (parent_rate * (mul + 1) + ((u64)parent_rate * frac >> 22));
/u-boot/arch/arm/include/asm/arch-imx8ulp/
H A Dpcc.h201 int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div);
/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dscg.h325 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
H A Dpcc.h367 int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div);

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