| /u-boot/board/kontron/sl-mx8mm/ |
| H A D | sl-mx8mm.c | 40 u32 ddr_size = readl(MCU_BOOTROM_BASE_ADDR); local
42 if (ddr_size == 4) {
44 } else if (ddr_size == 3) {
46 } else if (ddr_size == 2) {
48 } else if (ddr_size == 1) {
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| /u-boot/board/technexion/pico-imx8mq/ |
| H A D | pico-imx8mq.c | 57 int ddr_size = readl(MCU_BOOTROM_BASE_ADDR); local
59 if (ddr_size == 0x4) {
61 } else if (ddr_size == 0x3) {
63 } else if (ddr_size == 0x2) {
65 } else if (ddr_size == 0x1) {
|
| /u-boot/board/cortina/presidio-asic/ |
| H A D | presidio.c | 112 unsigned int ddr_size; local
114 ddr_size = readl(0x111100c);
115 gd->ram_size = ddr_size * 0x100000;
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| /u-boot/drivers/ram/renesas/rzn1/ |
| H A D | ddr_async.c | 35 u32 ddr_size; member in struct:cadence_ddr_info
217 priv->ddr_size = priv->ddr_size / 2;
222 ddr_start_addr, priv->ddr_size,
240 memset((void *)RZN1_V_DDR_BASE, 0xff, priv->ddr_size);
326 ret = ofnode_read_u32(subnode, "size", &priv->ddr_size);
347 if (cadence_ddr_test((long *)RZN1_V_DDR_BASE, priv->ddr_size)) {
349 gd->ram_size = priv->ddr_size;
354 if (!priv->ddr_size)
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| /u-boot/board/keymile/km83xx/ |
| H A D | km83xx.c | 212 u32 ddr_size; local
236 for (ddr_size = msize << 20, ddr_size_log2 = 0;
237 (ddr_size > 1);
238 ddr_size = ddr_size >> 1, ddr_size_log2++)
239 if (ddr_size & 1)
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| /u-boot/board/freescale/ls1043ardb/ |
| H A D | ddr.c | 181 phys_size_t ddr_size; local
204 ddr_size = (phys_size_t)2048 * 1024 * 1024;
207 return ddr_size;
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| /u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ram.c | 332 u32 ddr_size; local
347 ddr_size = (nb_bytes >> data_bus_width) << nb_bit;
348 if (ddr_size > STM32_DDR_SIZE) {
349 ddr_size = STM32_DDR_SIZE;
350 debug("invalid DDR configuration: size = %x\n", ddr_size);
353 return ddr_size;
|
| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | ddr.c | 210 size_t ddr_size; local
247 ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
252 ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
257 return ddr_size;
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| /u-boot/drivers/ram/sifive/ |
| H A D | sifive_ddr.c | 238 const u64 ddr_size = priv->info.size; local
239 const u64 ddr_end = priv->info.base + ddr_size;
317 ddr_size);
322 if (priv->info.size != ddr_size) {
324 (uintptr_t)priv->info.size, (uintptr_t)ddr_size);
|
| /u-boot/include/renesas/ |
| H A D | ddr_ctrl.h | 37 * @ddr_size Size of the DDR in bytes. The controller will set the port
44 u32 ddr_start_addr, u32 ddr_size,
|
| /u-boot/drivers/ram/cadence/ |
| H A D | ddr_ctrl.c | 305 u32 ddr_start_addr, u32 ddr_size,
368 ddr_start_addr + ddr_size, 0);
389 ddr_start_addr, ddr_size);
303 cdns_ddr_ctrl_init(void *ddr_ctrl_basex, int async, const u32 *reg0, const u32 *reg350, u32 ddr_start_addr, u32 ddr_size, int enable_ecc, int enable_8bit) argument
|
| /u-boot/board/variscite/dart_6ul/ |
| H A D | dart_6ul.c | 177 u8 ddr_size; member in struct:dart6ul_info
257 DART6UL_DDRSIZE(info->ddr_size) / SZ_1M,
|
| /u-boot/board/freescale/lx2160a/ |
| H A D | lx2160a.c | 566 u64 ddr_size = 0; local
570 ddr_size += gd->bd->bi_dram[i].size;
571 print_size(ddr_size, "");
|