1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6#include <common.h> 7#include <fsl_ddr_sdram.h> 8#include <fsl_ddr_dimm_params.h> 9#include <asm/global_data.h> 10#include "ddr.h" 11#include <log.h> 12#include <vsprintf.h> 13#ifdef CONFIG_FSL_DEEP_SLEEP 14#include <fsl_sleep.h> 15#endif 16#include <asm/arch/clock.h> 17 18DECLARE_GLOBAL_DATA_PTR; 19 20void fsl_ddr_board_options(memctl_options_t *popts, 21 dimm_params_t *pdimm, 22 unsigned int ctrl_num) 23{ 24 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 25 ulong ddr_freq; 26 27 if (ctrl_num > 1) { 28 printf("Not supported controller number %d\n", ctrl_num); 29 return; 30 } 31 if (!pdimm->n_ranks) 32 return; 33 34 pbsp = udimms[0]; 35 36 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr 37 * freqency and n_banks specified in board_specific_parameters table. 38 */ 39 ddr_freq = get_ddr_freq(0) / 1000000; 40 while (pbsp->datarate_mhz_high) { 41 if (pbsp->n_ranks == pdimm->n_ranks) { 42 if (ddr_freq <= pbsp->datarate_mhz_high) { 43 popts->clk_adjust = pbsp->clk_adjust; 44 popts->wrlvl_start = pbsp->wrlvl_start; 45 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 46 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 47 popts->cpo_override = pbsp->cpo_override; 48 popts->write_data_delay = 49 pbsp->write_data_delay; 50 goto found; 51 } 52 pbsp_highest = pbsp; 53 } 54 pbsp++; 55 } 56 57 if (pbsp_highest) { 58 printf("Error: board specific timing not found for %lu MT/s\n", 59 ddr_freq); 60 printf("Trying to use the highest speed (%u) parameters\n", 61 pbsp_highest->datarate_mhz_high); 62 popts->clk_adjust = pbsp_highest->clk_adjust; 63 popts->wrlvl_start = pbsp_highest->wrlvl_start; 64 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 65 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 66 } else { 67 panic("DIMM is not supported by this board"); 68 } 69found: 70 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", 71 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); 72 73 /* force DDR bus width to 32 bits */ 74 popts->data_bus_width = 1; 75 popts->otf_burst_chop_en = 0; 76 popts->burst_length = DDR_BL8; 77 78 /* 79 * Factors to consider for half-strength driver enable: 80 * - number of DIMMs installed 81 */ 82 popts->half_strength_driver_enable = 1; 83 /* 84 * Write leveling override 85 */ 86 popts->wrlvl_override = 1; 87 popts->wrlvl_sample = 0xf; 88 89 /* 90 * Rtt and Rtt_WR override 91 */ 92 popts->rtt_override = 0; 93 94 /* Enable ZQ calibration */ 95 popts->zq_en = 1; 96 97 /* optimize cpo for erratum A-009942 */ 98 popts->cpo_sample = 0x46; 99 100 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 101 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 102 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 103} 104 105/* DDR model number: MT40A512M8HX-093E */ 106#ifdef CONFIG_SYS_DDR_RAW_TIMING 107dimm_params_t ddr_raw_timing = { 108 .n_ranks = 1, 109 .rank_density = 2147483648u, 110 .capacity = 2147483648u, 111 .primary_sdram_width = 32, 112 .ec_sdram_width = 0, 113 .registered_dimm = 0, 114 .mirrored_dimm = 0, 115 .n_row_addr = 15, 116 .n_col_addr = 10, 117 .bank_addr_bits = 2, 118 .bank_group_bits = 2, 119 .edc_config = 0, 120 .burst_lengths_bitmask = 0x0c, 121 122 .tckmin_x_ps = 938, 123 .tckmax_ps = 1500, 124 .caslat_x = 0x000DFA00, 125 .taa_ps = 13500, 126 .trcd_ps = 13500, 127 .trp_ps = 13500, 128 .tras_ps = 33000, 129 .trc_ps = 46500, 130 .trfc1_ps = 260000, 131 .trfc2_ps = 160000, 132 .trfc4_ps = 110000, 133 .tfaw_ps = 21000, 134 .trrds_ps = 3700, 135 .trrdl_ps = 5300, 136 .tccdl_ps = 5355, 137 .refresh_rate_ps = 7800000, 138 .dq_mapping[0] = 0x0, 139 .dq_mapping[1] = 0x0, 140 .dq_mapping[2] = 0x0, 141 .dq_mapping[3] = 0x0, 142 .dq_mapping[4] = 0x0, 143 .dq_mapping[5] = 0x0, 144 .dq_mapping[6] = 0x0, 145 .dq_mapping[7] = 0x0, 146 .dq_mapping[8] = 0x0, 147 .dq_mapping[9] = 0x0, 148 .dq_mapping[10] = 0x0, 149 .dq_mapping[11] = 0x0, 150 .dq_mapping[12] = 0x0, 151 .dq_mapping[13] = 0x0, 152 .dq_mapping[14] = 0x0, 153 .dq_mapping[15] = 0x0, 154 .dq_mapping[16] = 0x0, 155 .dq_mapping[17] = 0x0, 156 .dq_mapping_ors = 0, 157}; 158 159int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 160 unsigned int controller_number, 161 unsigned int dimm_number) 162{ 163 static const char dimm_model[] = "Fixed DDR on board"; 164 165 if (((controller_number == 0) && (dimm_number == 0)) || 166 ((controller_number == 1) && (dimm_number == 0))) { 167 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 168 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 169 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 170 } 171 172 return 0; 173} 174#else 175 176phys_size_t fixed_sdram(void) 177{ 178 int i; 179 char buf[32]; 180 fsl_ddr_cfg_regs_t ddr_cfg_regs; 181 phys_size_t ddr_size; 182 ulong ddr_freq, ddr_freq_mhz; 183 184 ddr_freq = get_ddr_freq(0); 185 ddr_freq_mhz = ddr_freq / 1000000; 186 187 printf("Configuring DDR for %s MT/s data rate\n", 188 strmhz(buf, ddr_freq)); 189 190 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { 191 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && 192 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { 193 memcpy(&ddr_cfg_regs, 194 fixed_ddr_parm_0[i].ddr_settings, 195 sizeof(ddr_cfg_regs)); 196 break; 197 } 198 } 199 200 if (fixed_ddr_parm_0[i].max_freq == 0) 201 panic("Unsupported DDR data rate %s MT/s data rate\n", 202 strmhz(buf, ddr_freq)); 203 204 ddr_size = (phys_size_t)2048 * 1024 * 1024; 205 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); 206 207 return ddr_size; 208} 209#endif 210 211#ifdef CONFIG_TFABOOT 212int fsl_initdram(void) 213{ 214 gd->ram_size = tfa_get_dram_size(); 215 if (!gd->ram_size) 216#ifdef CONFIG_SYS_DDR_RAW_TIMING 217 gd->ram_size = fsl_ddr_sdram_size(); 218#else 219 gd->ram_size = 0x80000000; 220#endif 221 return 0; 222} 223#else 224int fsl_initdram(void) 225{ 226 phys_size_t dram_size; 227 228#ifdef CONFIG_SYS_DDR_RAW_TIMING 229#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) 230 puts("Initializing DDR....\n"); 231 dram_size = fsl_ddr_sdram(); 232#else 233 dram_size = fsl_ddr_sdram_size(); 234#endif 235#else 236#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) 237 puts("Initialzing DDR using fixed setting\n"); 238 dram_size = fixed_sdram(); 239#else 240 gd->ram_size = 0x80000000; 241 242 return 0; 243#endif 244#endif 245 erratum_a008850_post(); 246 247#ifdef CONFIG_FSL_DEEP_SLEEP 248 fsl_dp_ddr_restore(); 249#endif 250 251 gd->ram_size = dram_size; 252 253 return 0; 254} 255#endif 256